# SDC2 external SD card routing constraints

Source: [https://docs.qualcomm.com/doc/80-PV086-5P/topic/SDC2 external SD card routing constraints.html](https://docs.qualcomm.com/doc/80-PV086-5P/topic/SDC2%20external%20SD%20card%20routing%20constraints.html)

The following table lists the SDC2 external SD card routing constraints. Note that the guidance of bus length is based on the SD card I/O driver capability and maximum load capacitance per SD card specifications. The QRB5165 SDIO pad capability can drive longer bus if needed.

| Metrics | Metrics | Metrics | Guidance | Guidance | Comments |
| --- | --- | --- | --- | --- | --- |
| Clock frequency | Clock frequency | Clock frequency | 50 MHz DDR/100 MHz SDR | 208 MHz |  |
| Data rate | Data rate | Data rate | 50 Mbps | 104 Mbps |  |
| SD card capacitive load | SD card capacitive load | SD card capacitive load | 10 pF | 5 pF [^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/SDC2%20external%20SD%20card%20routing%20constraints.html#topic_dwn_wlh_5qb__fn_1) | For UHS104 modes, if card capacitance is > 5 pF then trace length must be reduced accordingly. |
| Bus length | Bus length | Bus length | < 150 mm | < 50 mm |  |
| Impedance [^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/SDC2%20external%20SD%20card%20routing%20constraints.html#topic_dwn_wlh_5qb__fn_1) | Impedance [^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/SDC2%20external%20SD%20card%20routing%20constraints.html#topic_dwn_wlh_5qb__fn_1) | Field route | 36 to 50 Ω | 36 to 50 Ω |  |
| Clock to data length matching | Clock to data length matching | Clock to data length matching | 6 mm | 2 mm |  |
| Spacing | To other signals | Field route | 1.5 × line width | 1.5 × line width |  |
| Spacing | Lane-to-lane | Field route | 1.5 × line width | 1.5 × line width |  |
| Component | CLK series termination resistor | CLK series termination resistor | 18 – 27 Ω | 18 – 27 Ω |  |
|  |  |  |  |  |  |

^1^  The range of PCB impedance includes manufacturing variation. The PCB designer is responsible for working with their PCB vendor to ensure each design falls within the published impedance range.

**Parent Topic:** [PCB layout guidelines](https://docs.qualcomm.com/doc/80-PV086-5P/topic/pcb-layout-guidelines.html)

Last Published: Jul 07, 2023