# SPMI layout rules

Source: [https://docs.qualcomm.com/doc/80-PV086-5P/topic/SPMI layout rules.html](https://docs.qualcomm.com/doc/80-PV086-5P/topic/SPMI%20layout%20rules.html)

The following table lists the SPMI routing constraints.

| Metrics | Metrics | Metrics | Guidance | Guidance | Guidance | Guidance |
| --- | --- | --- | --- | --- | --- | --- |
| Date rate | Date rate | Date rate | 19.2 Mbps | 19.2 Mbps | 19.2 Mbps | 19.2 Mbps |
| Bus length | Bus length | Bus length | < 60 mm | < 90 mm | < 120 mm | < 150 mm |
| Routing topology | Routing topology | Routing topology | Star routing<br>                                possible<br><br>. <br>Daisy chain preferred. | Star routing<br>                                possible<br><br>. <br>Daisy chain preferred. | Daisy chain | Daisy chain |
| Stub length | Stub length | Stub length | &lt;5 mm | &lt; 3 mm | &lt; 3 mm | &lt; 3 mm |
| Loading | Bus capacitance | Bus capacitance | Min 5 pF to max 20 pF<br>                            lumped capacitance | Min 5 pF to max 20 pF<br>                            lumped capacitance | Min 5 pF to max 20 pF<br>                            lumped capacitance | Min 5 pF to max 20 pF<br>                            lumped capacitance |
| Impedance [^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/SPMI%20layout%20rules.html#fntarg_1) | SE | Field route | 45 – 55 Ω | 36 – 44 Ω | 36 – 44 Ω | 36 – 44 Ω |
| Length match | Clk to data | Clk to data | &lt;2 mm (15 pS) | &lt;2 mm (15 pS) | &lt;2 mm (15 pS) | &lt;2 mm (15 pS) |
| Spacing | Clk to data | Field route | 1.5 × line<br>                            width | 1.5 × line<br>                            width | 2 × line<br>                            width | 2 × line<br>                            width |
| Spacing | To other signals | Field route | 1.5 × line<br>                            width | 1.5 × line<br>                            width | 2 × line<br>                            width | 2 × line<br>                            width |
|  |  |  |  |  |  |  |

[^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/SPMI%20layout%20rules.html#fnsrc_1)  The range of PCB impedance includes manufacturing
                                variation. The PCB designer is responsible for working with their
                                PCB vendor to ensure each design falls within the published
                                impedance range.

**Parent Topic:** [PCB layout guidelines](https://docs.qualcomm.com/doc/80-PV086-5P/topic/pcb-layout-guidelines.html)

Last Published: Jul 07, 2023