# UFS routing constraints

Source: [https://docs.qualcomm.com/doc/80-PV086-5P/topic/UFS routing constraints.html](https://docs.qualcomm.com/doc/80-PV086-5P/topic/UFS%20routing%20constraints.html)

The following table lists the UFS routing constraints. Note that there is no Rx-to-Tx
            interlane matching requirement.

| Metrics | Metrics | Metrics | Guidance | Guidance | Guidance | Guidance |
| --- | --- | --- | --- | --- | --- | --- |
| Data rate | Data rate | Data rate | 6.0 Gbps (Gear 3) | 6.0 Gbps (Gear 3) | 6.0 Gbps (Gear 3) | 10 Gbps (Gear 4, Rate A) |
| Channel differential insertion<br>                            loss | Channel differential insertion<br>                            loss | Channel differential insertion<br>                            loss | -6 dB at 3 GHz | -6 dB at 3 GHz | -6 dB at 3 GHz | -1.3 dB at 2.9 GHz, -5.0 dB at 5.8 GHz |
| Bus length | Bus length | Bus length | 25 mm | 75 mm | 150 mm | ≤ 70 mm |
| Impedance [^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/UFS%20routing%20constraints.html#fntarg_1) | Differential | Field route | 75 to105 Ω | 75 to105 Ω | 75 to105 Ω | 70 to 110 Ω |
| Length match | Intralane length match | Intralane length match | 5 ps (0.7 mm) | 5 ps (0.7 mm) | 5 ps (0.7 mm) | 5 ps (0.7 mm) |
| Length match | Tx 1 to Tx 2 or Rx 1 to Rx 2 | Tx 1 to Tx 2 or Rx 1 to Rx 2 | 30 ps (4.2 mm) | 30 ps (4.2 mm) | 30 ps (4.2 mm) | 30 ps (4.2 mm) |
| Spacing | Rx-to-Tx | Field route | 1.5 × line width | 2 × line width | 3 × line width | 2.5 × line width |
| Spacing | Rx1-to-Rx2 or<br><br><br>                            <br>Tx1-to-Tx2 | Field route | NA | NA | NA | 2 × line width |
| Spacing | To all other signals | Field route | 2 × line width | 2 × line width | 3 × line width | 3 × line width |
|  |  |  |  |  |  |  |
|  |  |  |  |  |  |  |

[^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/UFS%20routing%20constraints.html#fnsrc_1)  The range of PCB impedance includes manufacturing
                                variation. The PCB designer is responsible for working with their
                                PCB vendor to ensure each design falls within the published
                                impedance range.

**Parent Topic:** [PCB layout guidelines](https://docs.qualcomm.com/doc/80-PV086-5P/topic/pcb-layout-guidelines.html)

Last Published: Jul 07, 2023