# System services Source: [https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_services.html](https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_services.html) ## Memory Protection Unit Source: [https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_services.html](https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_services.html) The Memory Protection Unit (MPU) of QCC730 can enhance the security and reliability of applications by preventing unauthorized or erroneous memory accesses. It also supports memory isolation and can grant different access to different tasks or processes. The MPU splits the memory map into up to eight regions (from 0 to 7) and manages the access rights and attributes of each region. If a range of memory space belongs to multiple MPU regions, the attributes of the region with the highest number take precedence. Accessing a region that is blocked by the MPU may result in the termination of the related task or process. QCC730 has two types of MPU regions: - Read-only and executable regions for text segments - Writable but non-executable regions for data segments This structure ensures that no memory region can be both writable and executable at the same time to protect against malicious or mistaken actions. The MPU is configured for both application images and SBL images. The MPU configuration is consistent with the image memory layout. Modifying the memory map of an SBL or application image may have unexpected results. ### MPU configuration for application image Source: [https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_services.html](https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_services.html) The MPU defines eight regions for application RAM and RRAM. ### Application RAM **Memory layout** The following figure illustrates the memory layout of application RAM. Figure : Application RAM memory layout App_RAM_mem_LO Sheet.1 流程 RAM ISR vector RAM ISR vector 流程.2 PS txt PS txt 流程.4 PS data PS data 流程.5 Sleep data retention region Sleep data retention region 流程.250 Border Border 流程.40 System stack System stack 流程.36 Perf data Perf data 流程.37 App data App data 流程.38 WLAN ctrl & system data WLAN ctrl & system data 流程.39 Packet memory Packet memory 流程.40 HW DS and descriptors HW DS and descriptors 流程.41 Heap Heap Sheet.45 流程.43 Data Data 流程.44 Text Text Sheet.46 流程.43 XN,RW XN,RW 流程.44 X, RO X, RO 流程.90 Perf txt Perf txt 流程.91 App txt App txt **MPU configuration** See the following figure and table for details about the MPU configuration of application RAM. Figure : MPU configuration of application RAM App_RAM_MPU_conf Sheet.1 流程.52 Region 0 Region 0 流程 RAM ISR vector RAM ISR vector 流程.2 PS txt PS txt 流程.4 PS data PS data 流程.5 Sleep data retention region Sleep data retention region 流程.250 Border Border 流程.40 System stack System stack 流程.36 Perf data Perf data 流程.37 App data App data 流程.38 WLAN ctrl & system data WLAN ctrl & system data 流程.39 Packet memory Packet memory 流程.40 HW DS and descriptors HW DS and descriptors 流程.41 Heap Heap Sheet.69 Sheet.59 0x0 0x0 Separator.35 Sheet.73 Sheet.74 0x16000 0x16000 Separator.35 Sheet.79 Sheet.80 0xA0000 0xA0000 Separator.35 流程.48 Border Border 流程.52 RAM_RW RAM_RW 流程.42 RAM_RO RAM_RO 流程.42 Region 1 & 2 Region 1 & 2 流程.49 Region 7 Region 7 流程.90 Perf txt Perf txt 流程.91 App txt App txt Table : MPU regions of application RAM | Region | Start address | Size | AP | XN | Subregion | | --- | --- | --- | --- | --- | --- | | 0 | 0x0 | 0x100000 | RW | 1 | 0t11100000 | | 1 | 0x0 | 0x10000 | RO | 0 | 0t00000000 | | 2 | 0x8000 | 0x8000 | RO | 0 | 0t11000000 | | 7 | 0x0 | 0x400 | RW | 1 | 0t00000001 | ### Application RRAM **Memory layout** The following figure illustrates the memory layout of application RRAM. Figure : Application RRAM memory layout PBL PBL FDT FDT SBL_A SBL_A FLASH_ISR vector FLASH_ISR vector Cal data Cal data INI data INI data PBL_PATCH PBL_PATCH Regdb data Regdb data SBL_B SBL_B PS txt PS txt PS data PS data Perf txt Perf txt App txt App txt Perf data Perf data App data App data WLAN ctrl & system data WLAN ctrl & system data WLAN ctrl & system txt WLAN ctrl & system txt Free space Free space BDF data BDF data Data Data Text Text XN,RW XN,RW X, RO X, RO **MPU configuration** See the following figure and table for details about the MPU configuration of application RRAM. Figure : MPU configuration of application RRAM Region 4 Region 4 RRAM txt RRAM txt Border Border Border Border Board data Board data RRAM data RRAM data Region 6 Region 6 Region 5 Region 5 0x200000 0x200000 0x23FF80 0x23FF80 0x250000 0x250000 0x312668 0x312668 0x37A000 0x37A000 Table : MPU regions of application RRAM | Region | Start address | Size | AP | XN | Subregion | | --- | --- | --- | --- | --- | --- | | 4 | 0x200000 | 0x200000 | RO | 0 | 0t11000000 | | 5 | 0x200000 | 0x80000 | RW | 1 | 0t11100000 | | 6 | 0x370000 | 0x10000 | RW | 1 | 0t00011111 | ### MPU configuration for SBL image Source: [https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_services.html](https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_services.html) The MPU defines five regions for SBL RAM and RRAM. ### SBL RAM **Memory layout** The following figure illustrates the memory layout of SBL RAM. Figure : SBL RAM memory layout BANK A BANK A BANK B BANK B BANK C BANK C BANK D BANK D SBL_RO SBL_RO SBL_RW SBL_RW Data Data Text Text XN,RW XN,RW X, RO X, RO **MPU configuration** See the following figure and table for details about the MPU configuration of SBL RAM. Figure : MPU configuration of SBL RAM Region 0 Region 0 Region 1 Region 1 0x80000 0x80000 0x88000 0x88000 0x90000 0x90000 BANK A BANK A BANK B BANK B BANK C BANK C BANK D BANK D SBL_RO SBL_RO Border Border SBL_RO SBL_RO Border Border Table : MPU regions of SBL RAM | Region | Start Address | Size | AP | XN | Subregion | | --- | --- | --- | --- | --- | --- | | 0 | 0x0 | 0x100000 | RW | 1 | 0t11100000 | | 1 | 0x80000 | 0x8000 | RO | 0 | 0t00000000 | ### SBL RRAM **Memory layout** Some of SBL codes run on RRAM, including shared functions in PBL region and PBL\_PATCH region. PBL\_PATCH region has two parts: PBL\_PATCH\_RO for text and PBL\_PATCH\_RW for data. The following figure illustrates the memory layout of SBL RRAM. Figure : SBL RRAM memory layout Region 0 Region 0 Region 1 Region 1 0x80000 0x80000 0x88000 0x88000 0x90000 0x90000 BANK A BANK A BANK B BANK B BANK C BANK C BANK D BANK D SBL_RO SBL_RO Border Border SBL_RO SBL_RO Border Border **MPU configuration** See the following figure and table for details about the MPU configuration of SBL RRAM. Figure : MPU configuration of SBL RRAM PBL PBL FDT FDT PBL_TATCH_RW PBL_TATCH_RW PBL_TATCH_RO PBL_TATCH_RO SBLA SBLA …… …… Region 2 Region 2 Region 4 Region 4 Region 3 Region 3 0x208000 0x208000 0x20A000 0x20A000 0x200000 0x200000 0x208400 0x208400 0x20A400 0x20A400 Table : MPU regions of SBL RRAM | Region | Start Address | Size | AP | XN | Subregion | | --- | --- | --- | --- | --- | --- | | 2 | 0x200000 | 0x200000 | RW | 1 | 0t11000000 | | 3 | 0x200000 | 0x8000 | RO | 0 | 0t00000000 | | 4 | 0x208000 | 0x2000 | RO | 0 | 0t00000001 | ## Watchdog Source: [https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_services.html](https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_services.html) QCC730 has a hardware watchdog module that can provide protection from certain types of system crashes at the system level. The configuration file of the watchdog is qccsdk\demo\qcli\_demo\prj.conf. The default configuration is as follows: CONFIG_WATCH_DOG_ENABLE=n CONFIG_WATCH_DOG_BITE_TIME=8Copy to clipboard ### Enable watchdog Follow these steps to enable the watchdog: 1. Edit the qccsdk\demo\qcli\_demo\prj.conf file, and change the configuration as follows: CONFIG_WATCH_DOG_ENABLE=y CONFIG_WATCH_DOG_BITE_TIME=8Copy to clipboard 2. Rebuild the application. The watchdog then works after the new application runs. Last Published: Jun 03, 2026 [Previous Topic Hosted mode over SPI](https://docs.qualcomm.com/bundle/publicresource/80-Y8730-2/topics/use_spi_for_hosted_mode.md) [Next Topic Security](https://docs.qualcomm.com/bundle/publicresource/80-Y8730-2/topics/security.md)