# Electrical specifications Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) This topic defines the device electrical performance specifications, including absolute maximum ratings, operating conditions, and subsystem (such as memory and connectivity) parameters, which are useful in deploying the device with optimal processing capabilities and high efficiency. ## Absolute maximum ratings Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) Do not exceed the absolute maximum ratings mentioned in [Table : Absolute maximum ratings](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#jbz1612763758912__table_u21_rls_qpb). **WARNING:** If ratings are exceeded, this may cause permanent damage to the device. Functionality and reliability are guaranteed only within the conditions described in [Operating conditions](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#rkh1612768256411). | Parameter | Description | Min | Max | Unit | | --- | --- | --- | --- | --- | | **Power supply voltages** | **Power supply voltages** | **Power supply voltages** | **Power supply voltages** | **Power supply voltages** | | VDD\_APC0 | Kryo Silver application processor | -0.3 | 1.0472 | V | | VDD\_APC1 | Kryo Gold application processor | -0.3 | 1.2485 | V | | VDD\_MODEM | Modem circuits | -0.3 | 1.0472 | V | | VDD\_GFX | Graphics processor | -0.3 | 1.1299 | V | | VDD\_PX1 | Pad group 1 - DDR pads | -0.3 | 1.287 | V | | VDD\_PX2 | Pad group 2 - SDC2 pads | -0.3 | 3.8984 | V | | VDD\_PX5 | Pad group 5 - UIM1 pads | -0.3 | 3.63 | V | | VDD\_PX6 | Pad group 6 - UIM2 pads | -0.3 | 3.63 | V | | VDD\_PX10 | Pad groups 10 - UFS pads | -0.3 | 1.4344 | V | | VDD\_PX11 | Pad groups 11 - CXO pads | -0.3 | 1.4344 | V | | VDD\_MX | On-chip memory | -0.3 | 1.0472 | V | | VDD\_LPI\_CX | LPI core | -0.3 | 1.0428 | V | | VDD\_A\_USBSSDP\_0\_CORE | USB SS 0.9 V circuit | -0.3 | 1.0175 | V | | VDD\_IO\_EBIx | EBI I/O circuit | -0.3 | 0.715 | V | | VDD\_A\_QREFS\_1P25 | Reference voltage for QREFS 1.25 V circuit | -0.3 | 1.512 | V | | VDD\_A\_USBHS\_3P1 | USB HS 3.1 V circuit | -0.3 | 3.8984 | V | | VDD\_A\_CXO\_1P8 | 1.8 V for clock circuits | -0.3 | 2.178 | V | | VDDPX\_VBIAS\_SDC | Bias voltage for SDC and UIM circuits | -0.3 | 1.512 | V | | VDDPX\_VBIAS\_UIM | Bias voltage for SDC and UIM circuits | -0.3 | 1.512 | V | | VDD\_PX0 | Pad group 3 - control signal pads | -0.3 | 2.2 | V | | VDD\_PX3 | Pad group 3 - I/O pads | -0.3 | 2.2 | V | | VDD\_PX7 | Pad group 7 - SDC1 pads | -0.3 | 2.2 | V | | VDD\_CX | Digital core circuits | -0.3 | 1.129 | V | | VDD\_WPSS\_CX | WPSS circuit | -0.3 | 1.129 | V | | VDD\_D\_EBIx | EBI digital circuits | -0.3 | 1.129 | V | | VDD\_A\_PCIE\_0\_1P2 | PCIe circuit | -0.3 | 1.386 | V | | VDD\_A\_PCIE\_1\_1P2 | PCIe circuit | -0.3 | 1.386 | V | | VDD\_A\_EDP\_1P2 | eDP circuits | -0.3 | 1.386 | V | | VDD\_VREF\_1P2 | PCIe circuit QLink1 circuit | -0.3 | 1.386 | V | | VDD\_A\_CSI\_x\_1P2 | CSI 1.2 V circuits | -0.3 | 1.386 | V | | VDD\_A\_UFS\_0\_1P2 | UFS 1.2 V circuits | -0.3 | 1.386 | V | | VDD\_A\_USBSSDP\_0\_1P2 | USB SS 1.2 V circuits | -0.3 | 1.386 | V | | VDD\_A\_QLINK\_0\_1P2\_CK | QLink 0 clock circuit | -0.3 | 1.386 | V | | VDD\_A\_QLINK\_1\_1P2 | QLink 1 clock circuit | -0.3 | 1.386 | V | | VDD\_A\_DSI\_0\_1P2 | DSI 1.2 V circuit | -0.3 | 1.386 | V | | VDD\_A\_PCIE\_0\_CORE | PCIe circuit | -0.3 | 1.155 | V | | VDD\_A\_PCIE\_1\_CORE | PCIe circuit | -0.3 | 1.155 | V | | VDD\_A\_EDP\_0P9 | eDP circuits | -0.3 | 1.155 | V | | VDD\_VREF\_0P9 | PCIe reference voltage | -0.3 | 1.155 | V | | VDD\_A\_CSI\_x\_0P9 | CSIX 0.9 V circuits | -0.3 | 1.155 | V | | VDD\_A\_QLINK\_x\_0P9 | QLink 0.9 V circuits | -0.3 | 1.155 | V | | VDD\_A\_QLINK\_x\_0P9\_CK | QLink clock circuits | -0.3 | 1.155 | V | | VDD\_A\_UFS\_0\_CORE | UFS 0.9 V circuits | -0.3 | 1.155 | V | | VDD\_A\_USBHS\_CORE | USB HS 0.9 V circuits | -0.3 | 1.155 | V | | VDD\_A\_GNSS\_0P9 | GNSS circuits | -0.3 | 1.155 | V | | VDD\_A\_DSI\_0\_0P9 | DSI 0.9 V circuits | -0.3 | 1.155 | V | | VDD\_A\_DSI\_0\_PLL\_0P9 | DSI PLL 0.9 V circuits | -0.3 | 1.155 | V | | VDD\_A\_QREFS\_0P875 | Reference voltage for QREFS 0.875 V circuit | -0.3 | 1.155 | V | | VDD\_A\_EBIx | EBI PHY voltage circuits | -0.3 | 1.115 | V | | VDD\_A\_PLL\_EBIx | EBI PLL circuit | -0.3 | 1.115 | V | | VDD\_A\_USBHS\_1P8 | USB HS 1.8 V circuits | -0.3 | 2.178 | V | | VDD\_QFPROM | Programming the QFPROM | -0.3 | 2.178 | V | | VDD\_A\_GFX\_CS\_1P8 | GFX 1.8 V circuits | -0.3 | 2.178 | V | | VDD\_A\_TURNING\_Q6\_CS\_1P8 | Power for Q6 current sensor 1.8 V circuits | -0.3 | 2.178 | V | | VDD\_A\_QREFS\_1P8 | Reference voltage for the QREFS 1.8 V circuits | -0.3 | 2.178 | V | | VDD\_A\_APC\_CS\_1P8 | Power for application processor current sensor; 1.8 V circuits | -0.3 | 2.178 | V | | VDD\_LPI\_NAV\_MX | LPI on chip memory – NAV | -0.3 | 1.0043 | V | | VDD\_LPI\_MX | Low-power island memory circuits | -0.3 | 1.0043 | V | | Ts | Storage temperature[^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_absolute-maximum-ratings), [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_2_absolute-maximum-ratings) | -55 | 150 | °C | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_1_absolute-maximum-ratings) The storage temperature range applies when the device is in the OFF state (the device is not assembled in any platform and is not electrically connected to any voltage or I/O signals). Damage may occur when the device is subjected to this temperature for any length of time. [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_2_absolute-maximum-ratings) For devices shipped in tape and reel, the storage temperature range is [+15°C~+35°C] and < 90% relative humidity (RH). QTI recommends allowing the device to return to ambient room temperature before usage. ## Operating conditions Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) Operating conditions include parameters such as power supply voltage, power distribution impedances, and thermal conditions. The QCS6490 and QCS5430 chipsets meet all performance specifications listed in the following table when used within the operating conditions. Note: Keep the thermal mitigation algorithm enabled with default limits to ensure that the operating temperature range is kept within the specification. | Parameter | Parameter | Parameter | Min | Type[^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_operating-conditions) | Max | Unit | | --- | --- | --- | --- | --- | --- | --- | | **Power supply voltages** | **Power supply voltages** | **Power supply voltages** | **Power supply voltages** | **Power supply voltages** | **Power supply voltages** | **Power supply voltages** | | VDD\_APC0 [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#rkh1612768256411__fn_vhf_15v_qgc) | – | Kryo Silver application processor | 0.47 | – | 0.952 | V | | VDD\_APC1 [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#rkh1612768256411__fn_vhf_15v_qgc) | – | Kryo Gold application processor | 0.484 | – | 1.135 | V | | VDD\_MODEM | – | Modem circuits | 0.47 | – | 0.952 | V | | VDD\_GFX [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#rkh1612768256411__fn_vhf_15v_qgc) | – | Graphics processor | 0.47 | – | 1.027 | V | | VDD\_PX1 (LPDDR5) | – | Pad group 1 - DDR pads | 1.01 | 1.05 | 1.12 | V | | VDD\_PX1 (LPDDR4X) | – | Pad group 1 - DDR pads | 1.06 | 1.1 | 1.17 | V | | VDD\_PX2 | Low voltage | Pad group 2 - SDC2 pads | 1.65 | 1.8 | 1.9 | V | | VDD\_PX2 | High voltage | Pad group 2 - SDC2 pads | 2.72 | 2.95 | 3.544 | V | | VDD\_PX5 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_3_operating-conditions) | Low voltage | Pad group 5 - UIM1 pads | 1.62 | 1.8 | 1.9 | V | | VDD\_PX5 [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_3_operating-conditions) | High voltage | Pad group 5 - UIM1 pads | 2.85 | 2.96 | 3.3 | V | | VDD\_PX6 | Low voltage | Pad group 6 - UIM2 pads | 1.62 | 1.8 | 1.9 | V | | VDD\_PX6 | High voltage | Pad group 6 - UIM2 pads | 2.85 | 2.96 | 3.3 | V | | VDD\_PX10 | – | Pad groups 10-UFS pads | 1.1 | 1.2 | 1.304 | V | | VDD\_PX11 | – | Pad groups 11-CXO pads | 1.1 | 1.2 | 1.304 | V | | VDD\_MX [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#rkh1612768256411__fn_vhf_15v_qgc) | Active | On-chip memory | 0.695 | – | 0.952 | V | | VDD\_MX [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#rkh1612768256411__fn_vhf_15v_qgc) | Retention | On-chip memory | 0.512 | – | 0.668 | V | | VDD\_LPI\_CX | – | LPI core | 0.47 | – | 0.948 | V | | VDD\_A\_USBSSDP\_0\_CORE | – | USB SS 0.9 V circuit | 0.825 | 0.875 | 0.925 | V | | VDD\_IO\_EBIx (LPDDR5) | > 1.5 GHz | EBI I/O circuit | 0.47 | 0.5 | 0.57 | V | | VDD\_IO\_EBIx (LPDDR5) | < 1.5 GHz | EBI I/O circuit | 0.27 | 0.3 | 0.37 | V | | VDD\_IO\_EBIx (LPDDR4X) | – | EBI I/O circuit | 0.57 | 0.6 | 0.65 | V | | VDD\_A\_QREFS\_1P25 | – | Reference voltage for QREFS 1.25 V circuit | 1.125 | 1.25 | 1.375 | V | | VDD\_A\_USBHS\_3P1 [^4^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_4_operating-conditions) | – | USB HS 3.1 V circuit | 2.7 | 3.072 | 3.544 | V | | VDD\_A\_CXO\_1P8 | – | 1.8 V for clock circuits | 1.68 | 1.8 | 1.98 | V | | VDDPX\_VBIAS\_SDC | – | Bias voltage for SDC and UIM circuits | 1.125 | 1.25 | 1.375 | V | | VDDPX\_VBIAS\_UIM | – | Bias voltage for SDC and UIM circuits | 1.125 | 1.25 | 1.375 | V | | VDD\_PX0 | – | Pad group 3 - control signal pads | 1.68 | 1.8 | 2 | V | | VDD\_PX3 | – | Pad group 3 - I/O pads | 1.68 | 1.8 | 2 | V | | VDD\_PX7 | – | Pad group 7- SDC1 pads | 1.68 | 1.8 | 2 | V | | VDD\_CX | Active | Digital core circuits | 0.47 | – | 1.027 | V | | VDD\_CX | Retention | Digital core circuits | 0.352 | – | 0.48 | V | | VDD\_WPSS\_CX | – | WPSS circuit | 0.47 | – | 1.027 | V | | VDD\_D\_EBIx | – | EBI digital circuits | 0.47 | – | 1.027 | V | | VDD\_A\_PCIE\_0\_1P2 | – | PCIe circuit | 1.11 | 1.2 | 1.26 | V | | VDD\_VREF\_1P2 | – | PCIe circuit QLink1 circuit | 1.11 | 1.2 | 1.26 | V | | VDD\_A\_CSI\_x\_1P2 | – | CSI 1.2 V circuits | 1.11 | 1.2 | 1.26 | V | | VDD\_A\_UFS\_0\_1P2 | – | UFS 1.2 V circuits | 1.11 | 1.2 | 1.26 | V | | VDD\_A\_USBSSDP\_0\_1P2 | – | USB SS 1.2 V circuits | 1.11 | 1.2 | 1.26 | V | | VDD\_A\_QLINK\_0\_1P2\_CK | – | QLink0 clock circuit | 1.11 | 1.2 | 1.26 | V | | VDD\_A\_QLINK\_1\_1P2 | – | QLink1 clock circuit | 1.11 | 1.2 | 1.26 | V | | VDD\_A\_DSI\_0\_1P2 | – | DSI 1.2 V circuit | 1.11 | 1.2 | 1.26 | V | | VDD\_A\_PCIE\_0\_CORE | – | PCIe circuit | 0.86 | 0.875 | 1.05 | V | | VDD\_VREF\_0P9 | – | PCIe reference voltage | 0.86 | 0.875 | 1.05 | V | | VDD\_A\_CSI\_x\_0P9 | – | CSIX 0.9 V circuits | 0.86 | 0.875 | 1.05 | V | | VDD\_A\_QLINK\_x\_0P9 | – | QLink 0.9 V circuits | 0.86 | 0.875 | 1.05 | V | | VDD\_A\_QLINK\_x\_0P9\_CK | – | QLink clock circuits | 0.86 | 0.875 | 1.05 | V | | VDD\_A\_UFS\_0\_CORE | – | UFS 0.9 V circuits | 0.86 | 0.875 | 1.05 | V | | VDD\_A\_USBHS\_CORE | – | USB HS 0.9 V circuits | 0.86 | 0.875 | 1.05 | V | | VDD\_A\_GNSS\_0P9 | – | GNSS circuits | 0.86 | 0.875 | 1.05 | V | | VDD\_A\_DSI\_0\_0P9 | – | DSI 0.9 V circuits | 0.86 | 0.875 | 1.05 | V | | VDD\_A\_DSI\_0\_PLL\_0P9 | – | DSI PLL 0.9 V circuits | 0.86 | 0.875 | 1.05 | V | | VDD\_A\_QREFS\_0P875 | – | Reference voltage for QREFS 0.875 V circuit | 0.86 | 0.875 | 1.05 | V | | VDD\_A\_EBIx | – | EBI PHY voltage circuits | 0.64 | – | 1.014 | V | | VDD\_A\_PLL\_EBIx | – | EBI PLL circuit | 0.64 | – | 1.014 | V | | VDD\_A\_USBHS\_1P8 | – | USB HS 1.8 V circuits | 1.68 | 1.8 | 1.98 | V | | VDD\_QFPROM | – | Programming the QFPROM | 1.68 | 1.8 | 1.98 | V | | VDD\_A\_GFX\_CS\_1P8 | – | GFX 1.8 V circuits | 1.68 | 1.8 | 1.98 | V | | VDD\_A\_TURNING\_Q6\_CS\_1P8 | – | Power for Q6 current sensor 1.8 V circuits | 1.68 | 1.8 | 1.98 | V | | VDD\_A\_QREFS\_1P8 | – | Reference voltage for the QREFS 1.8 V circuits | 1.68 | 1.8 | 1.98 | V | | VDD\_A\_APC\_CS\_1P8 | – | Power for application processor current sensor; 1.8 V
circuits | 1.68 | 1.8 | 1.98 | V | | VDD\_LPI\_NAV\_MX | – | LPI on chip memory – NAV | 0.695 | – | 0.913 | V | | VDD\_LPI\_MX | – | Low-power island memory circuits | 0.695 | – | 0.913 | V | | **Thermal conditions** | **Thermal conditions** | **Thermal conditions** | **Thermal conditions** | **Thermal conditions** | **Thermal conditions** | **Thermal conditions** | | T | – | Device operating temperature | Tambient = -30 | – | Tjunction = 95 | °C | | T [^5^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_5_operating-conditions) | – | Device operating temperature | Tambient = -30 | – | Tjunction = 105 | °C | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_1_operating-conditions) Typical voltages represent the recommended output settings of the companion PMIC device. ^2^ All voltage rails are optimized and dynamically controlled by software based on system requirements and margins. During boot-up stage, some power rails, for example, VDD\_GFX, VDD\_APC, VDD\_MX might margin close to operation but within absolution maximum. Internal validation has been performed under these conditions. [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_3_operating-conditions) Universal Identity Module (UIM) is not supported on the QCS6490 and QCS5430 chipsets. For more information on supported pins, see [QCM6490/QCS6490+ PM7325 + PM7350C + PM7250B-2 Reference Schematic (80-20659-44)](https://docs.qualcomm.com/bundle/80-20659-44/resource/80-20659-44.pdf) and [QCS6490/QCS5430 Technical Reference Manual (80-20659-5)](https://docs.qualcomm.com/bundle/80-20659-5/resource/80-20659-5.pdf). [^4^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_4_operating-conditions) Software configures L2B VDD\_A\_USBHS\_3P1 to vote 2.704 V. At boot/power-on L7B starts at 2.952 V. Once UFS is enumerated at XBL, software changes this voltage to 2.5 V (for UFS3.1). [^5^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_5_operating-conditions) This thermal condition is applicable only for the 300-AA variant of QCS6490 and QCS5430. Note: Unless otherwise specified, the specifications apply across the device's operating temperature range. ## Power delivery network specification Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) For power delivery network specification, see [QCS6490/QCS5430 Chipset Power Delivery Network Specification (80-20659-1P)](https://docs.qualcomm.com/bundle/80-20659-1P/resource/80-20659-1P.pdf). ## Average operating current Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) For current consumption information and details on operating modes tested, see [QCM6490/QCS6490 Linux Android Current Consumption Data Application Note (80-20659-7)](https://docs.qualcomm.com/bundle/80-20659-7/resource/80-20659-7.pdf). ## Dhrystone maximum power Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The Dhrystone maximum power (tested at 1× Kryo Prime at 2.4 GHz, 3 × Kryo Gold at 2.4 GHz, and 4 × Kryo Silver at 1.8 GHz) at 95°C (Tj) is 6.9 W. QTI recommends measuring the Dhrystone power on the VDD\_APC1 rail, right before PDN capacitors with a small serial sampling resistor inserted, if necessary. The measurement sampling rate is > 1.25 Msps (or < 0.8 μs), and the average window is > 1 ms (or > 1250 samples). Note: The Dhrystone specification applies to QCS6490 and QCS5430 commercial sample (CS) devices only. ## Power sequencing Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The PMIC includes power-on circuits that provide the correct power sequencing for the QCS6490 and QCS5430 chipsets. The supplies are turned on as groups of regulators controlled by the hardware configuration of certain PMIC pins. For more information, see [PM7325 Data Sheet (80-19730-1)](https://docs.qualcomm.com/bundle/80-19730-1/resource/80-19730-1.pdf) and [PM7350C Data Sheet (80-PW237-1)](https://docs.qualcomm.com/bundle/80-PW237-1/resource/80-PW237-1.pdf). A high-level summary of the required default power-on sequence is as follows: | Sequence | Power domain | | :---: | --- | | 1 | VDD\_PX5 (UICC1), VDD\_PX6 (UICC2), | | 2 | VDD\_MX (on-chip memory) | | 3 | VDD\_LPI\_MX (LPI core memory), VDD\_NAV\_LPI\_MX | | 4 | VDD\_A\_EBI\_0P9 (EBI 0.9 V), VDD\_A\_PLL\_EBI\_0P9 | | 5 | VDD\_CX (digital core), VDD\_D\_EBI, VDD\_WPSS\_CX (WPSS core supply) | | 6 | VDD\_LPI\_CX (LPI core) | | 7 | VDD\_PX0 (pad group0), VDD\_PX3 (peripheral), VDD\_PX7 (eMMC pads) | | 8 | VDD\_PX1 (pad group1) | | 9 | VDD\_A\_DSI\_1P2 (DSI 1.2 V), VDD\_A\_PCIe\_0\_PLL\_1P2, VDD\_A\_USB\_SS\_DP\_1P2,
VDD\_A\_UFS\_0\_1P, VDD\_A\_QLINK\_1P2\_CK (QLINK 1.2 V), VDD\_A\_CSI\_X\_1P2 (CSI 1.2 V) | | 10 | VDD\_A\_QREFS\_1P25 (reference voltage for the QREFS 1.25 V circuit),
VDDPX\_VBIAS\_SDC (reference voltage for SDC), VDDPX\_VBIAS\_UIM (reference voltage for
UIM) | | 11 | VDD\_A\_DSI\_PLL\_0P9 (DSI 0.9 V PLL), VDD\_A\_UFS\_0\_CORE (UFS), VDD\_A\_CSI\_X\_0P9 (CSI
0.9 V), VDD\_A\_DSI\_0P9 (DSI 0.9 V), VDD\_USBHS\_CORE (USB HS), VDD\_A\_QREFS\_0P875
(reference voltage for the QREFS 0.875 V), VDD\_A\_QLINK0\_0P9 (QLink0), VDD\_A\_QLINK1\_0P9 (QLink1), VDD\_A\_GNSS\_0P9, VDD\_A\_PCIe0\_CORE,
VDD\_A\_QLINK0\_CK\_0P9 (QLink0 clock), VDD\_A\_QLINK1\_CK\_0P9 (QLink1
clock), | | 12 | VDD\_A\_USB\_SS\_DP\_CORE (USB Core) | | 13 | VDD\_PX11 (CXO pad group) | | 14 | VDD\_A\_QREFS\_VREF\_1P8, VDD\_A\_APC\_CS\_1P8, VDD\_A\_USB\_HS\_1P8, VDD\_A\_GFX\_CS\_1P8,
VDD\_A\_QFPROM, VDD\_A\_TURNING\_CS\_1P8, VDD\_A\_CXO\_1P8 | | 15 | VDD\_IO\_EBI (EBI I/O supply) | | 16 | VDD\_A\_USB\_HS\_3P1 (USB HS 3.1 V) | | 17 | VDD\_PX10 (UFS reference clock, UFS reset ) | | 18 | VDD\_PX2 (SDC2 pads) | | 19 | VDD\_APC0 (Silver application processor) | This sequence includes: - After completing the sequence, the software can power-on other appropriate power supply. - Before the next domain starts increasing, each domain must achieve its 90% value. ## Digital-logic characteristics Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The digital I/O performance specification depends on pad type, usage, supply voltage, or a combination of pad type, usage, and supply voltage. - Some of the I/Os are dedicated for interconnections between the SoC device and other ICs within the QTI chipset; therefore, specifications are not required. - Some of the I/Os conform to existing standards, such as I²C and SPI. QTI devices comply with those standards; therefore, additional specifications are not required. - All other digital I/Os require performance specifications. Note: Unless otherwise specified, all device characterizations are carried out across the specified operating temperature and voltage ranges. Table : DC specification of 1.8 V GPIOs and WCSS WSI I/Os | Parameter | Description | Min | Max | Unit | | :---: | --- | :---: | :---: | :---: | | VIH | High-level input voltage, CMOS/Schmitt (HIHYS\_EN = low) | 0.65 × VDD\_PX3 | VDD\_PX3 + 0.3 V | V | | VIL | Low-level input voltage, CMOS/Schmitt (HIHYS\_EN = low) | -0.3 V | 0.35 × VDD\_PX3 | V | | VIH | High-level input voltage, CMOS/Schmitt (HIHYS\_EN = high) | 0.7 × VDD\_PX3 | VDD\_PX3 + 0.3 V | V | | VIL | Low-level input voltage, CMOS/Schmitt (HIHYS\_EN = high) | -0.3 V | 0.3 × VDD\_PX3 | V | | VHYS | Schmitt hysteresis voltage (HIHYS\_EN= low) | 100 | — | mV | | VHYS | Schmitt hysteresis voltage (HIHYS\_EN = high) | 300 | — | mV | | IIH | Input high leakage current | — | 1.0 | µA | | IIL | Input low leakage current | -1.0 | — | µA | | IIHPD | Input high leakage current with pull-down | 27.5



(60) | 97.5



(20) | µA



(kΩ) | | IILPU | Input low leakage current with pull-up | -97.5
(20) | -27.5



(60) | µA



(kΩ) | | VOH | High-level output voltage, CMOS [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__fn_fdf_kk5_vfc) | VDD\_PX3 - 0.45 | VDD\_PX3 | V | | VOL | Low-level output voltage, CMOS [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__fn_fdf_kk5_vfc) | 0.0 | 0.45 | V | ^1^ VOL and VOH are measured at IOL and IOH respectively, with 16 mA current across min and max voltages and operating temperatures. For more information regarding possible drive strength settings, see [Table : Possible drive strength](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__table_qjc_yj5_vfc) Table : Possible drive strength | BIT configuration | Drive strength (mA) | | :---: | :---: | | 000 | 2 | | 001 | 4 | | 010 | 6 | | 011 | 8 | | 100 | 10 | | 101 | 12 | | 110 | 14 | | 111 | 16 | Table : SDC 3 V mode DC specifications | Parameter | Description | Min | Typ | Max | Unit | | :---: | --- | :---: | :---: | :---: | :---: | | VIH | High-level input voltage | 0.625 × VDD\_PX2 | – | VDD\_PX2 + 0.3 | V | | VIL | Low-level input voltage | -0.3 | – | 0.25 × VDD\_PX2 | V | | VHYS | Schmitt hysteresis voltage | 100 | – | – | mV | | IIH | Input high leakage current | – | – | 10 | µA | | IIL | Input low leakage current | -10 | – | – | µA | | RPULL-UP | Pull-up resistance | 10 | – | 100 | kΩ | | RPULL-DOWN | Pull-down resistance | 10 | – | 100 | kΩ | | RKEEPER-UP | Keeper-up resistance | 10 | – | 100 | kΩ | | RKEEPER-DOWN | Keeper-down resistance | 10 | – | 100 | kΩ | | VOH | High-level output voltage [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__fn_zft_j51_yfc) | 0.75 × VDD\_PX2 | – | VDD\_PX2 | V | | VOL | Low-level output voltage [^2^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__fn_zft_j51_yfc) | 0.0 | – | 0.125 × VDD\_PX2 | V | ^2^ VOL and VOH are measured at IOL and IOH respectively, with 16 mA current across min and max voltages and operating temperatures. For more information regarding possible drive strength settings, see [Table : Possible drive strength](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__table_emt_k51_yfc) Table : Possible drive strength | BIT configuration | Drive strength (mA) | | :---: | :---: | | 000 | 2 | | 001 | 4 | | 010 | 6 | | 011 | 8 | | 100 | 10 | | 101 | 12 | | 110 | 14 | | 111 | 16 | Table : SDC 1.8 V mode DC specifications | Parameter | Description | Min | Typ | Max | Unit | | :---: | --- | :---: | :---: | :---: | :---: | | VIH | High-level input voltage | 1.27 | – | 2 | V | | VIL | Low-level input voltage | -0.3 | – | 0.58 | V | | VHYS | Schmitt hysteresis voltage | 100 | – | – | mV | | IIH | Input high leakage current | – | – | 5 | µA | | IIL | Input low leakage current | -5 | – | – | µA | | RPULL-UP | Pull-up resistance | 10 | – | 100 | kΩ | | RPULL-DOWN | Pull-down resistance | 10 | – | 100 | kΩ | | RKEEPER-UP | Keeper-up resistance | 10 | – | 100 | kΩ | | RKEEPER-DOWN | Keeper-down resistance | 10 | – | 100 | kΩ | | VOH | High-level output voltage [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__fn_uq2_cy1_yfc) | 1.4 | – | – | V | | VOL | Low-level output voltage [^3^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__fn_uq2_cy1_yfc) | – | – | 0.45 | V | ^3^ VOL and VOH are measured at IOL and IOH respectively, with 16 mA current across min and max voltages and operating temperatures. For more information regarding possible drive strength settings, see [Table : Possible drive strength](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__table_a31_zx1_yfc) Table : Possible drive strength | BIT configuration | Drive strength (mA) | | :---: | :---: | | 000 | 2 | | 001 | 4 | | 010 | 6 | | 011 | 8 | | 100 | 10 | | 101 | 12 | | 110 | 14 | | 111 | 16 | Table : UICC 3 V mode DC specifications for (VDD_PX5 and VDD_PX6) | Parameter | Description | Min | Typ | Max | Unit | | :---: | --- | :---: | :---: | :---: | :---: | | VDDPX | Supply voltage | 2.7 | 2.95 | 3.05 | V | | VIH | High-level input voltage [^4^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_4_digital-logic-characteristics) | 0.7 × VDDPX | – | VDDPX + 0.3 | V | | VIL | Low-level input voltage | -0.3 | – | 0.2 × VDDPX | V | | VHYS | Schmitt hysteresis voltage [^5^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_5_digital-logic-characteristics) | 100 | – | – | mV | | IIH | Input high leakage current | -20 | – | 20 | µA | | IIL | Input low leakage current | – | – | 1000 | µA | | RPULL-UP | Pull-up resistance | 10 | – | 100 | kΩ | | RPULL-DOWN | Pull-down resistance | 10 | – | 100 | kΩ | | RKEEPER-UP | Keeper-up resistance | 10 | – | 100 | kΩ | | RKEEPER-DOWN | Keeper-down resistance | 10 | – | 100 | kΩ | | VOH | High-level output voltage [^6^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_6_digital-logic-characteristics) | 0.8 × VDDPX | – | VDDPX | V | | VOL | Low-level output voltage [^7^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_7_digital-logic-characteristics) | 0.0 | – | 0.4 | V | [^4^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_4_digital-logic-characteristics) VIH and VIL are only applicable for the I/O signal. VHYS is not a required specification for UICC. [^5^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_5_digital-logic-characteristics) VHYS is not a required specification for UICC. [^6^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_6_digital-logic-characteristics) UICC specifies VOH = 0.8 × VDDPX (RST) and 0.7 × VDDPX (clock, I/O). The worse-case VOH is used in this table. VOL and VOH are measured at IOL and IOH respectively, with 16 mA current across min and max voltages and operating temperatures. [^7^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_7_digital-logic-characteristics) UICC specifies VOL = 0.2 × VDDPX (RST, clock) and 0.4 V (I/O). The worse-case VOL is used in this table. VOL and VOH are measured at IOL and IOH respectively, with 16 mA current across min and max voltages and operating temperatures. For more information regarding possible drive strength settings, see [Table : Possible drive strength](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__table_c4g_4y1_yfc) Table : Possible drive strength | BIT configuration | Drive strength (mA) | | :---: | :---: | | 000 | 2 | | 001 | 4 | | 010 | 6 | | 011 | 8 | | 100 | 10 | | 101 | 12 | | 110 | 14 | | 111 | 16 | Table : UICC 1.8 V mode DC specifications for (VDD_PX5 and VDD_PX6) | Parameter | Description | Min | Typ | Max | Unit | | :---: | --- | :---: | :---: | :---: | :---: | | VDDPX | Supply voltage [^8^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_8_digital-logic-characteristics) | 1.65 | 1.8 | 1.95 | V | | VIH | High-level input voltage [^9^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_9_digital-logic-characteristics) | 0.7 × VDDPX | – | VDDPX + 0.3 | V | | VIL | Low-level input voltage | -0.3 | – | 0.2 × VDDPX | V | | VHYS | Schmitt hysteresis voltage | 100 | – | – | mV | | IIH | Input high leakage current | -20 | – | 20 | µA | | IIL | Input low leakage current | – | – | 1000 | µA | | RPULL-UP | Pull-up resistance | 10 | – | 100 | kΩ | | RPULL-DOWN | Pull-down resistance | 10 | – | 100 | kΩ | | RKEEPER-UP | Keeper-up resistance | 10 | – | 100 | kΩ | | RKEEPER-DOWN | Keeper-down resistance | 10 | – | 100 | kΩ | | VOH | High-level output voltage [^10^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__fn_lj5_tz1_yfc) | 0.8 × VDDPX | – | VDDPX | V | | VOL | Low-level output voltage [^10^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__fn_lj5_tz1_yfc) | 0.0 | – | 0.4 | V | [^8^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_8_digital-logic-characteristics) The UICC supply range for class C is 1.62 V 1.98 V. [^9^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_9_digital-logic-characteristics) VIH, VIL, are only applicable for I/O signal. VHYS is not a required specification for UICC. ^10^ VOL and VOH are measured at IOL and IOH respectively, with 16 mA current across min and max voltages and operating temperatures. For more information regarding possible drive strength settings, see [Table : Possible drive strength](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603__table_grn_qz1_yfc) Table : Possible drive strength | BIT configuration | Drive strength (mA) | | :---: | :---: | | 000 | 2 | | 001 | 4 | | 010 | 6 | | 011 | 8 | | 100 | 10 | | 101 | 12 | | 110 | 14 | | 111 | 16 | Table : Digital I/O characteristics for VDD_PX10 nominal (UFS) | Parameter | Description | Min | Max | Unit | | :---: | --- | :---: | :---: | :---: | | VOL | Output low-level voltage | 0 | 0.25 × VDD\_PX10 | V | | VOH | Output high-level voltage | 0.75 × VDD\_PX10 | VDD\_PX10 | V | | RPULL-UP | Pull-up resistance | 20 | – | kΩ | | RPULL-DOWN | Pull-down resistance | 20 | – | kΩ | ## Timing characteristics Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) Specifications for the device timing characteristics are included (where appropriate) under each function along with all its other performance specifications. Some general comments about timing characteristics and pertinent pad design methodologies are included here. Note: QCS6490 and QCS5430 devices are characterized with actively terminated loads, so all baseband timing parameters assume no bus loading. For more information, see [Rise and fall time specifications](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#kfb1612783228904). ### Timing diagram conventions Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The following figure shows the conventions used within timing diagrams throughout this document. Figure : Timing diagram conventions Page-1 Sheet.35 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Keeper Keeper Sheet.8 Sheet.9 Don't care or bus is driven Don't care or bus is driven Sheet.10 Signal is changing from low to high Signal is changing from low to high Sheet.11 Signal is changing from high to low Signal is changing from high to low Sheet.12 Bus is changing from invalid to valid Bus is changing from invalid to valid Sheet.13 Bus is changing from valid to keeper Bus is changing from valid to keeper Sheet.14 Waveform Waveform Sheet.15 Description Description Sheet.16 Denotes multiple clock periods Denotes multiple clock periods Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Bus is changing from Hi-Z to valid Bus is changing from Hi-Z to valid Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 For each signal in the diagram: - One clock period (T) extends from one rising clock edge to the next rising clock edge. - The high level represents 1, the low level represents 0, and the middle level represents the floating (high impedance) state. - When both the high and low levels are shown over the same time interval, the meaning depends on the signal type: - For a bus type signal (multiple bits), the processor or external interface is driving a value, but that value may or may not be valid. - For a single signal, it indicates *don’t care*. ### Rise and fall time specifications Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) QCS6490 and QCS5430 chipsets characterization testing uses actively terminated loads, making the rise and fall times quicker (mimicking a no-load condition). The impact of different external load conditions on rise and fall times is shown in the following figure. Figure : Rise and fall times under different load conditions Page-1 Sheet.40 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Specified switch low points (active terminated load) Specified switch low points(active terminated load) Sheet.10 Simulated driving 30 pF signal load Simulated driving 30 pF signal load Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Actual switch low point at 30 pF Actual switch low point at 30 pF Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 0V 0V Sheet.23 Simulated driving 80 pF signal load Simulated driving 80 pF signal load Sheet.24 0V 0V Sheet.25 Sheet.26 VOH VOH Sheet.27 VOL VOL Sheet.28 VOH VOH Sheet.29 VOL VOL Sheet.30 Specified switch high points (active terminated load) Specified switch high points(active terminated load) Sheet.31 Sheet.32 Actual switch high point at 30 pF Actual switch high point at 30 pF Sheet.33 Actual switch high point at 80 pF Actual switch high point at 80 pF Sheet.34 Actual switch low point at 80 pF Actual switch low point at 80 pF Sheet.35 Sheet.36 VDD_PX VDD_PX Sheet.37 VDD_PX VDD_PX Sheet.38 Sheet.39 To account for external load conditions, add the rise or fall times to the parameters that start timing at the QCS6490 and QCS5430 chipsets and terminate at an external device (or vice versa). Adding these rise and fall times is equivalent to applying capacitive load derating factors. ### Pad design methodology Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The QCS6490 and QCS5430 chipsets use a generic CMOS pad driver design. The pad design creates a pin response and behavior that is symmetric, regarding the associated VDD_PXDD_PX/2% or 50% of Vsupply. The input switchpoint for pure input-only pads is a VDD_PX supply. The documented switchpoints (guaranteed over worst-case combinations of process, voltage, and temperature by both design and characterization) are 35% of VDD_PX for VIL and 65% of VDD_PX for VIH. Figure : Digital input-signal switchpoints Page-1 Sheet.23 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 0 V 0 V Sheet.6 VDD_PX VDD_PX Sheet.7 Sheet.8 50% 50% Sheet.9 VIL VIL Sheet.10 VIH VIH Sheet.11 Switch points Switch points Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 65% VDD_PX 65% VDD_PX Sheet.19 35% VDD_PX 35% VDD_PX Sheet.20 Input Input Sheet.21 Sheet.22 Outputs (such as addresses, chip selects, and clocks) are designed and characterized to source or sink a large DC output current (several mA) at the documented VOH (min) and VOL(max) levels over worst-case process/voltage/temperature. The pad output structures are essentially CMOS drivers. They may have a small amount of IR loss (estimated at <50 mV under worst-case conditions), the expected zero DC load outputs are estimated to be: - VOH~ VDDPX- 50 mV or more - VOL~ 50 mV or less Figure : Output pad equivalent circuit Page-1 Sheet.103 Sheet.1 Sheet.2 Sheet.3 output pad output pad Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 P_out P_out Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Sheet.90 Sheet.91 P_out = high IR loss < 50 mV P_out = highIR loss < 50 mV Sheet.92 Sheet.93 Sheet.94 Sheet.95 Sheet.96 Sheet.97 Sheet.98 P_out = low IR loss < 50 mV P_out = lowIR loss < 50 mV Sheet.99 VDD_Px VDD_Px Sheet.100 SDM pad SoC pad Sheet.101 Pad voltage: High (max) > VDD_Px – 50 mV Low (min) < 50 mV Pad voltage: High (max) > VDD_Px -50 mV Low (min) < 50 mV Sheet.102 The output pads are essentially CMOS outputs with a corresponding FET-type output voltage/current transfer function. When an output pad is shorted to the opposite power rail, the pad is capable of sourcing or sinking ISC (SC = short-circuit) of current, where the magnitude of ISC is larger than the current capability at the intended output logic levels. The DC output drive strength can be approximated by linear interpolations between VOH (min) and VDDPX - 50 mV, and between VOL (max) and 50 mV. For example, an output pad driving low that guarantees 4.5 mA at VOL (max) provides approximately 3.0 mA or more at 2/3 × [VOL (max) - 50 mV], and 1.5 mA or more at 1/3 × [VOL (max) - 50 mV]. Likewise, an output pad driving high that guarantees 2.5 mA at VOH (min) provides approximately 1.25 mA or more at ½ × [VDDPX - 50 mV + VOH (min)]. The target application includes a radio, output pads are designed to minimize output slew rates. Decreased slew rates limit high-frequency spectral components that tend to desensitize the companion radio. ## Memory support Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) All timing parameters in this document assume no bus loading. Rise/fall time numbers must factor into the numbers in this document. For example, setup time numbers get worse, and hold time numbers may improve. ### EBI0 and EBI1 memory support Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The EBI0 and EBI1 ports are dedicated to the non-PoP LPDDR4X/LPDDR5 SDRAM memory that is attached to the QCS6490 and QCS5430 chipsets. ### eMMC on SDC1 Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) eMMC NAND flash supports the SDC1 port. For more information, see [Secured digital interfaces](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#won1612791672430). ## Multimedia Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) This topic addresses the performance specification of multimedia parameters. ### Camera interfaces Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The QCS6490 and QCS5430 chipsets support five 4-lane MIPI-CSI: CSI0, CSI1, CSI2, CSI3, and CSI4. Table : Supported MIPI-CSI standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *MIPI Alliance Specification for D-PHY v1.2* | Supports only unidirectional data receiving | | *MIPI Alliance Specification for C-PHY v1.0* | None | ### Audio support Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) A dedicated audio codec, such as the WCD9370/WCD9375/WCD9380/WCD9385, uses the industry standard SoundWire interface. Other audio-related interface options include: - Digital microphone: [Digital microphone PDM interface](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#mhz1612792085502) - SWR: [SoundWire (SWR) interface](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#ixa1612792117268) - SLIMbus: [SLIMbus interface](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fhj1612792152597) - I²S: [I²S interfaces](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#qnl1612792195661) - I²C/I3C: [I²C/I3C interface](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#arb1612792921091) - SPI: [Serial peripheral interface](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#pzl1612792942013) For more information on performance characteristics, see [Qualcomm Aqstic™ WCD9370 Device Specification (80-PG244-1)](https://docs.qualcomm.com/bundle/80-PG244-1/resource/80-PG244-1.pdf), [Qualcomm Aqstic WCD9375 Device Specification (80-PG245-1)](https://docs.qualcomm.com/bundle/80-PG245-1/resource/80-PG245-1.pdf), and [Qualcomm Aqstic WCD9380/WCD9385 Device Specification (80-PL335-1)](https://docs.qualcomm.com/bundle/80-PL335-1/resource/80-PL335-1.pdf). ### Display support Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The QCS6490 and QCS5430 chipsets support one D-PHY display. Table : Supported MIPI-DSI standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *MIPI Alliance Specification for Display Serial Interface* | None | | *MIPI Alliance Specification for D-PHY v1.2* | None | | *MIPI Alliance Specification for C-PHY v1.0* | None | ### Digital media broadcast (DMB) support Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The QCS6490 and QCS5430chipsets support an external DMB solution using the following interface options: - SPI: [Serial peripheral interface](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#pzl1612792942013) - SD: [Secured digital interfaces](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#won1612791672430) ## Connectivity Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The connectivity functions that require electrical specifications for this chipset are as follows: - SD, including SD cards and multimedia cards (MMC) - USB host/slave support with built-in physical layer (PHY) - Universal integrated circuit card (UICC) interface - DisplayPort support over USB Type-C - Serial low-power interchip media bus (SLIMbus) interface for Bluetooth, FM - Inter-IC sound (I²S) interfaces - Touchscreen connections - Dedicated I²C interfaces for camera (CCI I²C) - Through proper configuration of QUP ports: - Universal asynchronous receiver/transmitter (UART) ports - Inter-integrated circuit (I²C) interfaces - Serial peripheral interface (SPI) ports The pertinent specifications for these functions are detailed in the following topics. Note: In addition to the following hardware specifications, see the latest software release notes for software-based performance features or limitations. ### Secured digital interfaces Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The supported secure digital (SD) interface standards and their exceptions are listed here. Table : Supported SD standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *MultiMediaCard Host Specification version 5.1* | None | | *Secure Digital: Physical Layer Specification version 3.0* | None | | *SDIO Card Specification version 3.0* | None | Figure : Secured digital interface timing Page-1 Sheet.356 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 t t Sheet.54 ( ( Sheet.55 dhrd dhrd Sheet.56 ) ) Sheet.57 t t Sheet.58 ( ( Sheet.59 chrd chrd Sheet.60 ) ) Sheet.61 t t Sheet.62 ( ( Sheet.63 dsurd dsurd Sheet.64 ) ) Sheet.65 t t Sheet.66 ( ( Sheet.67 csurd csurd Sheet.68 ) ) Sheet.69 t t Sheet.70 ( ( Sheet.71 ) ) Sheet.72 t t Sheet.73 ( ( Sheet.74 ) ) Sheet.75 t t Sheet.76 ( ( Sheet.77 t t Sheet.78 SDC_CLK SDC_CLK Sheet.79 Read Read Sheet.80 Write Write Sheet.81 Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Sheet.90 Sheet.91 Sheet.92 Sheet.93 Sheet.94 Sheet.95 Sheet.96 Sheet.97 Sheet.98 Sheet.99 Sheet.100 Sheet.101 t t Sheet.102 ( ( Sheet.103 dvdrd dvdrd Sheet.104 ) ) Sheet.105 t t Sheet.106 ( ( Sheet.107 cvdrd cvdrd Sheet.108 ) ) Sheet.109 Single data rate – SDR mode Single data rate – SDR mode Sheet.110 Sheet.111 Sheet.112 Sheet.113 Sheet.114 Sheet.115 Sheet.116 Sheet.117 Sheet.118 Sheet.119 Sheet.120 Sheet.121 Sheet.122 Sheet.123 Sheet.124 Sheet.125 Sheet.126 Sheet.127 Sheet.128 Sheet.129 Sheet.130 Sheet.131 Sheet.132 Sheet.133 Sheet.134 Sheet.135 Sheet.136 Sheet.137 Sheet.138 Sheet.139 Sheet.140 Sheet.141 Sheet.142 Sheet.143 Sheet.144 Sheet.145 Sheet.146 Sheet.147 Sheet.148 Sheet.149 Sheet.150 Sheet.151 Sheet.152 Sheet.153 t t Sheet.154 ( ( Sheet.155 pdcwr pdcwr Sheet.156 ) ) Sheet.157 Sheet.158 Sheet.159 Sheet.160 t t Sheet.161 ( ( Sheet.162 chrd chrd Sheet.163 ) ) Sheet.164 Sheet.165 Sheet.166 t t Sheet.167 ( ( Sheet.168 csurd csurd Sheet.169 ) ) Sheet.170 Sheet.171 t t Sheet.172 ( ( Sheet.173 ) ) Sheet.174 Sheet.175 t t Sheet.176 ( ( Sheet.177 ) ) Sheet.178 Sheet.179 t t Sheet.180 ( ( Sheet.181 Sheet.182 t t Sheet.183 SDC_CLK SDC_CLK Sheet.184 CMD read CMD read Sheet.185 CMD write CMD write Sheet.186 Sheet.188 Sheet.189 Sheet.190 Sheet.191 Sheet.192 Sheet.193 t t Sheet.194 ( ( Sheet.195 pddwr pddwr Sheet.196 ) ) Sheet.197 Data read Data read Sheet.198 Data write Data write Sheet.199 Sheet.200 Sheet.201 Sheet.202 Sheet.203 Sheet.204 Sheet.205 Sheet.206 Sheet.207 Sheet.208 t t Sheet.209 ( ( Sheet.210 dhrd dhrd Sheet.211 ) ) Sheet.212 t t Sheet.213 ( ( Sheet.214 dsurd dsurd Sheet.215 ) ) Sheet.216 Sheet.217 Sheet.218 Sheet.219 Sheet.220 Sheet.221 Sheet.222 Sheet.223 Sheet.224 t t Sheet.225 ( ( Sheet.226 dhrd dhrd Sheet.227 ) ) Sheet.228 t t Sheet.229 ( ( Sheet.230 dsurd dsurd Sheet.231 ) ) Sheet.232 Sheet.233 Sheet.234 Sheet.235 Sheet.236 Sheet.237 Sheet.238 Sheet.239 Sheet.240 Sheet.241 Sheet.242 t t Sheet.243 ( ( Sheet.244 pddwr pddwr Sheet.245 ) ) Sheet.246 Sheet.247 Sheet.248 Sheet.249 Sheet.250 Sheet.251 Sheet.252 Double data rate – DDR mode Double data rate – DDR mode Sheet.253 HS400 mode input timing HS400 mode input timing Sheet.254 Sheet.255 SDC_RCLK SDC_RCLK Sheet.256 Sheet.257 t(pddwr) t(pddwr) Sheet.258 Data read Data read Sheet.259 Data write Data write Sheet.260 Sheet.261 HS400 mode output timing HS400 mode output timing Sheet.262 Sheet.263 CMD write CMD write Sheet.264 Sheet.265 Sheet.266 Sheet.267 Sheet.268 Sheet.269 Sheet.270 Sheet.271 Sheet.272 Sheet.273 Sheet.274 Sheet.275 Sheet.276 Sheet.277 VIH VIH Sheet.278 VIL VIL Sheet.279 Sheet.280 Sheet.281 Sheet.282 t RQ t RQ Sheet.283 VT VT Sheet.284 Sheet.285 Sheet.286 Sheet.287 t t Sheet.288 ( ( Sheet.289 dvdrd dvdrd Sheet.290 ) ) Sheet.291 Sheet.292 Sheet.293 Sheet.294 Sheet.295 Sheet.296 Sheet.297 Sheet.298 Sheet.299 Sheet.300 Sheet.301 Sheet.302 Sheet.303 Sheet.304 VOH VOH Sheet.305 VOL VOL Sheet.306 SDC_CLK SDC_CLK Sheet.307 Sheet.308 Sheet.309 Sheet.310 Sheet.311 Sheet.312 Sheet.313 Sheet.314 Sheet.315 VT VT Sheet.316 Sheet.317 Sheet.318 Sheet.319 Sheet.320 Sheet.321 Sheet.322 Sheet.323 Sheet.324 Sheet.325 Sheet.326 Sheet.327 Sheet.328 Sheet.329 Sheet.330 t RQH t RQH Sheet.331 Sheet.332 Sheet.333 t(pdcwr) max t(pdcwr) max Sheet.334 Sheet.335 Sheet.336 Sheet.337 Sheet.338 VOH VOH Sheet.339 VOL VOL Sheet.340 Sheet.341 Sheet.342 Sheet.343 Sheet.344 Sheet.345 Sheet.346 Sheet.347 Sheet.348 Sheet.349 Sheet.350 t(pdcwr)min t(pdcwr)min Sheet.351 Sheet.352 t(pddwr) t(pddwr) Sheet.353 Sheet.354 t(pddwr) t(pddwr) Sheet.355 t(pdcwr) t(pdcwr) | SDCC modes | Frequency | Parameter | Description | Min (ns) | Max (ns) | | --- | --- | --- | --- | --- | --- | | HS400 (DDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_secured-digital-interfaces) | 200 MHz | TclkH | Clock high time | 2.25 | 2.75 | | HS400 (DDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_secured-digital-interfaces) | 200 MHz | Tcidv | Command input valid window | N/A | 2.4 | | HS400 (DDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_secured-digital-interfaces) | 200 MHz | Tcodly | Command output delay | -1.45 | 0.85 | | HS400 (DDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_secured-digital-interfaces) | 200 MHz | tRQ | DQS to DQ valid setup | 0.4 | N/A | | HS400 (DDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_secured-digital-interfaces) | 200 MHz | tRQH | DQS to DQ valid hold | N/A | -0.4 | | HS400 (DDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_secured-digital-interfaces) | 200 MHz | Tdodly | Data output delay | 0.4 | 1.85 | | HS200(SDR 200 MHz) | 200 MHz | TclkH | Clock high time | 2.25 | 2.75 | | HS200(SDR 200 MHz) | 200 MHz | Tcidv | Command input valid window | N/A | 2.4 | | HS200(SDR 200 MHz) | 200 MHz | Tcodly | Command output delay | -1.45 | 0.85 | | HS200(SDR 200 MHz) | 200 MHz | Tidv | Data input valid window | N/A | 2.4 | | HS200(SDR 200 MHz) | 200 MHz | Tdodly | Data output delay | -1.45 | 0.85 | | DDR52 | 52 MHz | TclkH | Clock high time | 8.65 | 10.57 | | DDR52 | 52 MHz | Tcisu | Command input setup | N/A | 5.53 | | DDR52 | 52 MHz | Tcih | Command input hold | N/A | 1.50 | | DDR52 | 52 MHz | Tcodly | Command output delay | -7.85 | 2.65 | | DDR52 | 52 MHz | Tisu | Data input setup | N/A | 1.65 | | DDR52 | 52 MHz | Tih | Data input hold | N/A | 1.50 | | DDR52 | 52 MHz | Tdodly | Data output delay | 2.50 | 6.15 | | SDR 104 | 202 MHz | TclkH | Clock high time | 1.5 | 3.5 | | SDR 104 | 202 MHz | Tcidv | Command input valid window | N/A | 2.4 | | SDR 104 | 202 MHz | Tcodly | Command output delay | -1.45 | 0.85 | | SDR 104 | 202 MHz | Tidv | Data input valid window | N/A | 2.4 | | SDR 104 | 202 MHz | Tdodly | Data output delay | -1.45 | 0.85 | | DDR 50 | 50 MHz | TclkH | Clock high time | 9 | 11 | | DDR 50 | 50 MHz | Tcisu | Command input setup | N/A | 6.3 | | DDR 50 | 50 MHz | Tcih | Command input hold | N/A | 1.5 | | DDR 50 | 50 MHz | Tcodly | Command output delay | -8.2 | 3 | | DDR 50 | 50 MHz | Tisu | Data input setup | N/A | 2 | | DDR 50 | 50 MHz | Tih | Data input hold | N/A | 1.5 | | DDR 50 | 50 MHz | Tdodly | Data output delay | 0.8 | 6 | | SDR 50 | 100 MHz | TclkH | Clock high time | 3 | 7 | | SDR 50 | 100 MHz | Tcisu | Command input setup | N/A | 2.5 | | SDR 50 | 100 MHz | Tcih | Command input hold | N/A | 1.5 | | SDR 50 | 100 MHz | Tcodly | Command output delay | -3.7 | 1.5 | | SDR 50 | 100 MHz | Tisu | Data input setup | N/A | 2.5 | | SDR 50 | 100 MHz | Tih | Data input hold | N/A | 1.5 | | SDR 50 | 100 MHz | Tdodly | Data output delay | -3.7 | 1.5 | | SDR 25 | 50 MHz | TclkH | Clock high time | 9 | 11 | | SDR 25 | 50 MHz | Tcisu | Command input setup | N/A | 6 | | SDR 25 | 50 MHz | Tcih | Command input hold | N/A | 1.5 | | SDR 25 | 50 MHz | Tcodly | Command output delay | -7 | 3 | | SDR 25 | 50 MHz | Tisu | Data input setup | N/A | 6 | | SDR 25 | 50 MHz | Tih | Data input hold | N/A | 2.5 | | SDR 25 | 50 MHz | Tdodly | Data output delay | -7 | 3 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_1_secured-digital-interfaces) For DDR200, DDR52 and SD DDR50, command input/output is only in single data rate (with respect to controller CLK falling edge). Only data input/ output is running at DDR. ### USB interfaces Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The supported USB standards and their exceptions are listed here. Table : Supported USB standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *Universal Serial Bus Specification, Revision 3.1* (August 11, 2014 or later) | SS Gen 1 | | *On-The-Go and Embedded Host Supplement to the USB 3.0 Specification* (May 10, 2012, Revision 1.1 or later) | Attach detection protocol (ADP), role swap protocol (RSP), session request protocol (SRP), and host negotiation protocol (HNP) | ### DisplayPort Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The supported DisplayPort standards and their exceptions are listed here. Table : Supported DisplayPort standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *VESA DisplayPort V1.4* | None | ### PCIe interface Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The supported PCIe standards and their exceptions are listed here. Table : Supported PCIe standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | PCI Express Base Specification Revision 3.0 | Link configure capability | ### UFS interface Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The supported UFS standards and their exceptions are listed here. Table : Supported UFS standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *Universal Flash Storage (UFS), Version 3.1* | None | | *Universal Flash Storage (UFS), Version 2.1* | None | ### Digital microphone PDM interface Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The following figure shows the digital microphone PDM interface timing. Figure : Digital microphone PDM interface timing ![Digital microphone PDM interface timing](data:image/png;base64,UklGRuIGAABXRUJQVlA4TNYGAAAvYQNVABcgEEjaH3oNAUGR/6MJBJL83WZ6/gN/FYqCtm2kmj/vfXcAImIC8nOojGv0hcrDBFNP+nYAtbJt27YCqfPex4X/wQ/1nSIR//8x6bRdE6f7vdeI/k8A3EhyI0lWNoT2APAHc4/eF4F2k3O7mBNPiuj/BPA3q/747x+KPu/22Zq/m/+QSID8/c6KUFna3gHv5G8gL4XYn+KtkLszvBd2h6J5J6jse0PVuEPt32n8wqKdugbAN2dvxs1R3yu3R3mr4P74Us43KFuseyw7/PHfj//+kQjK7kGx3HeAurkFWYcN2MthX6Q5q2rUA8z50BoaZcxPR/LVNI6E2IHkzsC6kmdj/m7gmWjUM9+ZRiHzlwKSTrolJTrqVFJpMST5ahpFnKC5pQEdIDuauyDqSZYIyo2mJkkLi45wGKws+VZ602gXJXs+ZP5uYJX8NbVdGL12sdiHRjXzKnYT7DaSF80hjVLmhyEclnw1jToRbQU2QlST3E0OgbUlz+L/MWL+bmChFivoG9GoZV5G2WtkkFSydWREo5j561n2oqMjkq+mUcYZms1SUy8WdpP7IGpJFgHuDOAVSIUrLQbA6pLvlDdEdMTZod+ZvxtY5Jkb0KhkvjONcuavZ4AvkXw1jaMhKkluYTlYX/JMzN8NPBuNOuY709iA+ZlIvprG4RB1JHcG7lDyLAxdH9IamhTUJduGdIWU0TpO+oasF1uww1itU/uftT6/XfwvG0Z+GklxBpX5nC+aJRlUOxUls5EGdD7Pafy6YR6K0C6ampf2HGe7i1OwnOOFjMvXjCyQgc/d5xQwg9AxnfIpRc+QcdcOQZYluQYxYTgXxZSwXcx7llPIMdzRLe/0CAzLCF+GIVkA4BAwGyOGvMP0AAbPx0docWPPCuqZxEAj73hmBiA5vmRYANcBFwDsHwd1mZLhlCUc4slQlqWm0FfkhJ0M50IpCANSEVTOBCeod8gwoNNOwWa0R3Eacq5xinIjB7LQOPw1c50Z/fD2cy451J7U7uJYMPZ50tddnstnKJ9kN8Zz+fa9x/7bMP0Nkz9iSX4UIMXZaJnPSX4UoJLxORNLpgJpQOfzGEumAnn5OhNNS6WFpualPUbTUmlx0VOQOSoZSsbla8JizmKASnbsEBQT4jqhM8gp3IjrSB6BYVmSazAjB4MpzUalhXnPcsrHFHeajUrrME5AFgFJ+CrEyP8xA6QCZ4DpvCMNeaOYHcF93PF0GCQtCjCo5JvZAxobWaK93agLAI73ZGzYAMTI/wEEuz05CK7SVDKEusI5kjqleRC2yFJTU1O4gGOUGTsJ6pTrJQxIg1M5kzMccL3ExfIMKBPWYVCcRMwFp+zGOjyLeeP410R3YtR4bzyVHGtPyjs9FU58HsSBr2P5jOWTPnefY/n+dSt/GNEG+Fvjyf+8Y5j1jqFsdgRVvWOY9SI6hY7WiQ7qdnQKu8iL1PGLFcqLbGJekiTBsiBJc1bV6CS/tY7GDjTq+AXckzlJ8zqSJCXL2MW2plFHoxZx8U0ROwALJamxK0lSso45aV5IkpStgYVRTIOU3JVGPY1KToIPAZJOuiUlLgonNQ1waq4wp/miBNA3HQD0vSNJySUJoH8RgA4gFsxp/hwnaG5pQA/5bRrfoFfGOxrfoXd6g3hQUG40NS+0YAsyyBYriMek1sBvO/dS4zl602g9fpekZCVz81KSkg/KX1PbhdFzunfcF4FrnXAMVUdX21whFjnbGKoAjaDv64eqDY0n2U2wq2RjtE60JRqL5GpzOD7G157GCrnkGI4BWbAv15KD+zL4IpSQAjvQkR0p7ApyCSpBgR1QCNTF6dgw+KMi2oylXix1UaxJ5EsE13RNIl+Bmn2Fdrg1fgO6BMxhP8FFEAXMXTwRtRRIBhXIJZLL2iWMnzJfJVMYPyf5rBbPwjdUCnMdBPawjMf1B+JByl4joxdK69AWxTIhBfZTuixBgf0cvITlTSODwUbGCoM/ocA1QT6Be/YoZ2g2S03taX6T/rpoUEIJ1DEde7/EikFlH7oBted4DHBnAC9ABtkYDLItCayRq13i+JAjxR3oErlkiuM7+6gNDeRz8oaInvObJCWXwNlWc0h0dCF7x9x8BZyqbA55o+8rhBVJeUxFcNVfNSeWvN+BZUmNnWlU0nhEh7ANqpcwwL/PnOaVJCn5AHvLnLYvjXoa34fhA0SJZ2qQqAQ+Y1+DRO5KkpSsY06aF5IkZVtgPaKYxs406mgUA0n1TZmTNK8jSVKyjDlJ25XGDjRqETsj6oC1NDq5B8N0XgRl/WKomxfBrBfROe6A1XQKRWyR1olqXONFDvzHfz/++wcg) The supported Digital microphone timings are listed here. | Parameter | Parameter | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | | 1/T | DMIC clock frequency | 0.6 | – | 6.144 | ns | | 1/T | DMIC clock duty cycle | 45 | – | 55 | – | | t(LSU) | Data left setup time to clock falling edge | – | – | – | ns | | t(LH) | Data left hold time to clock falling edge | 0 | – | – | ns | | t(RSU) | Data right setup time to clock rising edge | 10 | – | – | ns | | t(RH) | Data right hold time to clock rising edge | 0 | – | – | – | | | | | | | | ### SoundWire (SWR) interface Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The QCS6490 and QCS5430 chipsets SoundWire PHY timing parameters comply with clock and data specifications, as specified in the MIPI Alliance Specification for SoundWire Version 0.8, Revision 04. Figure : PHY timing – clock output/input and data input ![PHY timing – clock output/input and data input](data:image/png;base64,UklGRgIeAABXRUJQVlA4TPUdAAAvxsOdAB8gEEjxaJktEEhGy2x1gUAyWmarz39U4QfQ7P5/HEm2E0BuDxCvUkDi7NKQ32D+J4Fq5+HKUx/PdnnOy6fIRzhDSeijlWf3VQIB78qQJ+IuvRq1CkCmB0GMPy75JyX+KTK6+twhov8WZdsW27ZZnD5HEMCeB+CBFw/iD+D9fTV3x3+9w8QfMGHvL2XuL5nL/H5nnREf8a4iS57urac7rMHmfK07yCLLHlG6HlQWYx5QD7IgthqEzmHOs0fAVAOYYghdC5/A5rDmIaEWAJDf6T0TBVALe35z3P1RD6YgohqKev2WS57pptqvogtSkR/KoarhE9g8ql7dmoJ+IXTF71IREet+lyoz/aLuMxGqIBWZUSyHrvvTH5lp5boT9qtRcz+d3hFnnAPN+4zryKE5XRFXnyKWtp4aJFbq0jgzSzNiIJa2upCa0Vl5xdLWtzl9ePA7z3lCRg8NrnOYtrqe8GldqS+c1qeILzUj9ng4XR2cqesm7SizT4Pz07wGaWtW68HOJurLJnAkgy8Vq+fVXuupCT1ts8KK/R4fMUhbsXs2ub9x9l7twQgLKSKb1eu+XOjdjfth7ye60OIV7N5V1nHEMG295l7A7G4eveb94X0dd0yUvQDucro+oLM3LUqo3HNrvyxpMhR01Z/iAvJDx1R9nlzvcDqR7VZsTu+7H2rsOSF9yEiAP8D0FFcC3LOnuAmb3dunuABg7t5T3DVTrVeN6nbkfop7et9wmnEdST2fZQzq8pxPa9zDE464pj/FbTDujFdcZ3rPlmMMmgKbGaOa9RHHhjzF5TSS+216X57jN7Z4rh1HlEYxaK7r+QnXYF7iic69ZIGFeh/xfR4bxNGbURpkMI7r/Bjxhc6v5aAL1TRj08SsZA6VAa6rnymkrnQONQdTKhzHZnwcqTN6yPDDup6uEV8yPuEr9YfreD5FjCsTnNcVIzOFT9U1jiM2j3O4mMtIRDarrYYKNyN4VpnHMVIH5FPyKriu0ToAkeeNVgJPfm40X1PyG+G6klrv9AXXr9K/P1E2g9MJI3OjFXY+/WlDPZzWO9js2LE/OlB3mLR3mPnaEt9LSjsZ0iJUF0QBI4izlaU2WDZqg6ksCRjfZ9LkSCt0ZQm9sc+kyZFWQmWB2dhn0uRIqwCq6hPYjX32YrI8FKssANzaZyZLWlFZenOfmSxpZWWb7ZfJk/bHanVfJddmlX+jPHVA7SufXLVe1avbXPV83e9gct2z1f0uNdd9ed1nInLNvVR9tinX/NqdnFGUUbq2dgTJkva3liSkvfSxpHXSFERC6ksfi0o6pAWB9Jc9FMHoiufDkgz0gfh/+X64HFj6LacCOJDUmY9t41F9ApOeFV4OBDRyuuA7rrginq9rg/NxsMwqAByHAsPojJdzsxLX0VkPRHPsoAORgKzmEakV16bBAzEM1IEIzes64+w16IxHwrLTDgQMp2bdMNMPNKO0bxFIK6xvpWEOBBuBgAYiOQWJI10csR2IRNL7kyZ0GWBPoCSrczoFVjrNpSX4VsGray0Y3wrNHEhvBXolrSGtJoEgQ6CULsOeQAnwad1oKBDEC/GJdhZ0rkCHI/d1GXZ0OcmHDSMhXavAtwjWt8KQM501EPAklfCa0DfeQAB7AiXBY26mwPCkBXuQVWBX3BQPeMw6QLIxx6AAucVqvdMHnEujy1DGXervibLIKgDGvzE6BpHJ+XQtkgFbmCueD9zIogCjSw0IcwyC03hcuiiK1+XhdH7H8wdscD4YoywTqQ9BMzrjBdexwevZWY+GLa06BKmR0+zgujYYL2vJXeG+20XWQJYvKbD0zUJiBwD2Bdrt6j2hMzYP5/VhXVfEhLuqcgN9Ss0JsC/QTs0aM/spiXV+xLzy3Nu+HOBuGHYFSrD6xY3nb15mJBLuClkCqXggQQLJaCDcEQhedwfSii8QwK5Ae3/AJ+f8Tszew/Uo82sO30uYA6yyt5N7ffANEqO3zkchy6KYoYdkM+qxPLI0DwStA568a4n0Aegczh9OT/joF8/regyCkzoA6WS+Ly8PHICpAuCEByDuMVtf9i5QvER+UAeal8kPa0Dyktmpe0zXgeGl7wLBS2UnK8GWxVQY3AXAC7MTlYBlsTVm7wDFTeQGdaALgzVm7gDJTWamKsGURVeZvr/UPSBsUaT5OoJwB0BZhK0D/OFD2B9YoAqULgx+JZGm+qQpitJfS5T+CiNsUaT5WoKAtvIgB2XyEbYO8McJ4rXylC4LYLXpu0t+qjtxj0lTFKW5XbBZ761zNSgoCu4w3jtn+p3Y69rgfBjCFkUabs16pt+JHdcGV2f2y++dkX4nFtfgO7GlwqJc6DdEnRF/8nSdH6+43jd4jZldiHG+jAcAWBRh+c3kO7Heius8znPT4J0zX8l3YklTNlGQizMiMQbGu4d8CxjJZsehywLI7kwEdQA130nn6+kDzkWTRUh4rXWlKsGURR8C/lCmiiesMNK3WvkWkLRWWJ5A8GlfIJJTIw0kSCAZDaT2B8LUQBJSkvICA1r4FiRpX0lrwDAFetkXiOZUJI6lgcQhAr0kJS3LC/GJxiFAeEcMBAlJuQnjW6l9q8C3CNa3PIHgNSEpYyBJAilN4yCJsyuQhZekDpS0is2zCuRaRZgqbAZYFvt1xZbigs1aecDvfESqNJgD3l/n8+lpbfDhCUdcy2ZK0axnnJu5adZHHBu8k0YKGxzHg5BlUTqHizM2ozeP7w/4sK7rfYPXqPXcuCXzIxZKl2N2GuLsf71iZckc5quDT7TxHq5jbqIwJoNL1Oyt8/2zeo90M+qxUBqKcaZoHUBc60rkc8aHp9MX/OIXz9nfCERZLB7kLvUHM2GrTRUGsAr0jxpIblNl0mSlNDelv7ro+0vVm7BFkeZrC8IPI6IOAMtiv7oIW2lKlwXwq4s0lSbLoirBlEVXn76/VK0JWxRpvr4gVBqURVQClsXWn60ylZfgB3WgC4P1Z6pM5iXZqUowZdF3gK4ykZdiJyvBlsXcAVBlECFyQHaiErAs9h54rTCVm+AGdaBz+8QNa0DmJpmpSjBl0XcBVJjITTGTmTQrXo7FlsVkaq4HA7khM5HPfCxYFpvNh9P1iuv5ujY4Z6cKA7lc8DriF1yvo7M6c9lEIVZixbVpoieqsNL4VmlytwyuFXvjgIsTBPoEPhBEA20lTQqkSCAB24FMEsylcZ5c64z4k6fr/HhFBANGaN9K8K2CV7Bgd8UhgUwQCGB3IC24Ar3sCKRTSr1szlEzXi/jfBkJTQD1SloDJi0QIYgX4hONAyQnUyDYCJRM54Mjriux4jqP89wgCuNbqX2rwLdIGpsYiDRaAlNSEkdoGU1q4XVHoBQym+bszbQJZFxF2OyrKOBcRZpsfhIz5gdlEfl88Ua62QHgAVhGYHPBdyKoA3JTVdWs5+vpA865SX0Eho8CxAPdpZZNV5YwRZH6bgBGJqsLNusxgD0ADcBG5HU+ik+ARQGbGx4CHINgo7I74wPO3mnEuclHFwazatZzs169M37BeczHHIJkI3VuY4OzN+JIAghyqyXJrZYit1pIb7W2AyENJHwLLySQAh8ox1wEApI7Nx/HkjgkEGqEnWvmdhlx9GZvRWS/nTakBYjfsGebi7AkDgkkNYlDp0G2A8GeQKzwGveIGXyiMiTVe46NoYFEeiDYDsRujrpg0g9pgXQQyP2QMHeRGoicKzoIFJ+kOGAzXzeaXC8weIhVkGvDffuV1yVuXnNteSCG511NduvGZpmIAwGew2pzO68HqAMkHMcLGI5/NeaHD/jw7mu98ymt1hOQ8no5jFdgeZkscl0VU2h5GFawwGKoJFbZw1As/x5Fc3rP2JABfRASUXL8m8nhXntIs2t/MmB6VYvYBe4c2MfeNTv3Khhpm9MVcX1Y7xAJ+zJpaXFEZ50R59C804pjZQm9i4QIRJz3Nf6Tap5xrq/ddyIKXiLO6+kLPj00D+d1fvxbEQ1uGWvK7q0kAjPO8zzi0/q0Xuf58qeiatY8nBDHZke5BIG9hyF0xpXARx9gbnY4r+v5y+P1fRzfa9KszthEO9HE7K/KQ7ieronmeZ0vl3MznhvHVMVGJ1jNK6Z4OF3XcV3HeWzGEVdUujLez+/r+Hh1Z37TPPBKbCqmwaZpcB0v4+XsEqwrm3X2+7dxq2yRP93jL9i6wOtIzM08+n0+p64S8bCeXfvu3miL2MdUxng+7WXjAcdYHbCz/yoEP42vEtCV0Yy4109P1x2f6BJkKgV/Iv5GAagkoUfcMtJ6nsx57CdhZ4X4WpfNGrJ/L5dxk4QNsXu2PcVh1N4pf/hUl83e0bW+Ktuk4N8HHjCs2v4k2G1Kh4R1wCCeTjuOBRzD4V5zeCKEEP5deLVfI1Ub4A4QAmf3H2PIalGGIgEECuLB/0Ve+Pmm/ssullLU3kcBFfFwWuM0/l9COhJl0DxG/e8dEIyIvH/ChHFFmh0DQ3vhXOK4A657CE0JXWcWCOAlgQJTYwiGUGCp+Cr70WsGef8qE5qQgFT8jRJgKO3KWC8SCJG0W3YRkW1TNqsXRYHhJDeGTEIdUC8YsLFnhkl23b77t985TGtFBhMNG08dmekK1vOYstNsnh+MMvvv2SoFNmRYBcJaYt9Zq2rYIKdIHUBTmF10Rew7TegSToqIvL/Yx6j6bZZif3UbeX+5j1W1qwOESbH/Dga1TDsl60VSUvMCI8L3rzGhgzsYVgqsoLu8zsB4AsHywoCoMQUWgus8Kx2SdYaUZIUYQqwxHVD3E2IA8Y/998f++6O5dS20/vUR9r2CTJ+ng+jb/a+i9C31EfZ6o9olD8b/tbejGZI61QZg/+szsSPuM+1EUtj227fNc6YtSJ/Sqz7wbYI3auuf1kk9PoE2fsCT4MG1G79fENxyAWb35RTs0H60w0baPvCcAELLRh/J8qGdjr/KkHLquk47iKATvrFisP9osdtIS30LKT4H2q0+uhy+C6Vs1ruednR5NMsNB1hSvhNHj8HH/4VDu8SPHAq3XO4/PiRR/61GjB1Wn5ymb6dy3qgLjmvbbkTpATHhe4800jefXcRw/9Dwwi9PSEsi/fztFh85fUuW+2N2fJsH159Q8RO8c4Tej5x28vPN76R42ufJD7TEtOpt8ccycnwmurxvS6p82ilYvkTc3HIn5WdEMMTQ3uJH7PmGMjWtM2H0sJKt/L6fSrB1Pkf7OviT21GAKYR2yF6Kx39OPCF9KKclOzjsIzlazlKGeGejA6P3B9+ROokElN+RkRAfFg6YJAq8m48bP8zkfC7CxuBZYgOj8yZAkUZ5fjdN8WHhpP3sUyntE/ZtvI/kfC5K54dv5BfBcF4AwaTuM/k9OStjx2twFGAaYZTunCFE+ugPWCHio4cMjOi5dnNs6j6TliYkBjIsBEqdSGql3V6NxA2Td4UZ2nBHxWI46WeJlpaeGdHDJVCYVKD00JL3DfoYWAoTHODBiwxnkKmk008RHYnAQBG3cPgMbeRX5QhO6XB5bHA5OnmfUf1ELT63SB6CiPCqMYYGL1G3hMtpCir5LEGHnBpUeyMUYCrxSSNdkfYxsmWB+imCDGcWLxbDwYBBAj7kbNrYsiSxczrsb+vdENLHhQAbG4MDLQmE1KG0+7aJiPQxh6NsGOH3gIcculA/UcIkU05sw9iWWVywWa8XvBDv/IINY7udg/QWspfCwcir929BYDbnuDnXhsQU0BwiVx26y28o0ocg6U+wYdhHsmUuGIH8wo+18ELCQgV6wh8rRp0zTOGvyAqZnInMb+UtAcMh3F2RM1MAphNesFofvlcmzUo1Dx9OOI+nlVHY4+j/y8ICvTZ2cgyeZtIH79B5fq9PuYzU9XRe5/PTdd9jCAVIWit8a6RvtdJ/0wXqAd1yKz4/W/GLj0bCiwu0MymJoxEAEFrhkgorf+EC/TelBQlEWkGSyo2kvpVgxXfPLpDr2y9+R6u3f6wRpoSkm4F8HBNxwevD6b1ZL42Du0iQ8EpaQ1otfAsSwkB/HQz8Agy8Pbs4ABJ2JqVxlPMKn2lSEQQSPhDJaWlSESaNBHoBA/8sCPT2M5DwM1DwjxKS7gqkwzrgGkBvzOQ1ThAvxCea04kFIv6iFwskEpLGAnmRQMTL79tImt7piJn8kESBbxGsb4XxrdS+DQN9DxY+uzi/cIHAB0pMKgHhs0/6TAJ94+KIPUklSao0jYP+XBH2mQZ6k+4HH2hJ2Be7AkWa+bolUyEQ+WhWwBBWBte+7hb5gGF4L9Kh8OM3uEclkfNUt5fMwo/y8KNZspmchVa5fGxYCAyRMiCbdUuuQoB8QLIBpIVAAB1k1UYLn0zO2fXkV8TCbcKWUkxMePsSKXyKFPa5X7qAYBKUPqTw4dUTscIng4PcmQ+UL+35WEQiLPkkE3LZ8chtRLGG0BReO4ELfR/yNrwGr4vMQ5SpDQdGi5zIlYAKhmA2S6mQ/IoG4PIS+s3CC0jXos+5uiJh2OmQYuQ/WbzuxkZvoIVPkciJ7U3B1V7zCIu9NgCcyGWjbF3cxOY1Iiz1BI+w2IuVegXzOy0guQTVA4F8RCBa6h1GrmIv+HwzPHyxF6XYmKB/bdn6uIWNjQgvOkykL/aIoNQr2RQj+GCkgmAVuewExW2JgrEc6DzLxG6QXOjdbfmGkF9+4yNC4UWHifLFHkWL23KRndYGgI1PGUx5Z9C2C7UUqo1pPWRiiD4g2EDQx75sGPLLkY8M3YKLDhOMIX3sStbdhoDi1C/UjR2ZbQqK21LdiKkNPtG5aKILAB9L+zgUrgu55YxUaAkuOlxEBC3nS9Yv/dQRktVE7lJbzAlLtXh+fo1+onMh5a2fiSDzicwWv3bZ+oCfN2aEgX6iQ5ANudASffkm9195DPnQ4rZYE+Lgfk8Jy6kdHDIEmU2d85uiDaGpYyUskv9u6QnJR9M+YteWr+1ufg9kgNxUBJlmKxq2LVLA63dzaUNLqbANtR6yMUirAHpC8gHaR+xrgN7DcJKBruWFMVi8rkzdrVy+oJ8opXm1AchgKFwXmjj5gPQelZ6QbGh5O9VDl0efC71lK1sfkIWIzHHlcKhbmIDhA7EZVKU5kZnyeugXVphL5GlIDUzZDNmQyGXrAsIeX9DH9la0IXiHjpmwkR+kYaR0ZUx5tJl0FdC2JeqXcmEbA8gpUusJbm1LbgWqoG15SRO4obCMEGriVpi2L52fbSrP5G5gCubn1iilWdG5FweQF+3jUAH0iRcrpaluYSYs6WMdLG4P5NHnEHmqWbR+6glZkrZs/dIvAcOKPvvpF6WZ0T5i8cKWFUJgYiYN6WEdTNkMWQTPccvmRjQhbEl+t2jDlIm/CPhLgTS8NO0jduWjy3mJ76mWmSK6KsA2G8zk5r/oULYWKcCStEXDNpPvFnL/0grLC2gfsS9esJyX/EXgmRcSbR10+XT8Ik+uyzZR3+qSDIXrcvFDwgUGZPa/XB+rgC7/OS/1lomoiD6fnl/kqWbZFuqbomDh+pDhBfShwt/U3PwzviqgyyUvzEXWxJSN4hf8UIvFmZpsit8sXJxhFSfPZhWpA8rZrBq1Xklarxb1fKZaL5vi79ny3sFAnnu2ut+Xd8/MqjIT0d3KMVB1mF/LNfciMpi8f138HGqe+bXJP8N1uGcUWzKjWId58rJmjfulDvqlnCcDPVWH512ZTDks3q38Z5o5nnfRb9I5mpU09HuKdXhuXdZT3GGqg2Eq50l9VwHdLfxrjDyWHG5eBf7GiJ/S2Gb6i5s++BujCriV9VdV2NYBtpl0ObQV0GKev44M3XJArwJ/85uBwS7rX8D+QP+7bsSuHFNgKtcw5f62Ai+lw9m8BYfCdVOgpO/gVIMoRl+4PtBnMuWwBH990hZsCSy8APOQphZiy6VhNzhKM+sJrIMpowzNULjuFqyVR58P6XDRuomd0uQiQIcFMBLW98+Z6kHpMpTftIG2zaLLoY1YikU63bKTETdegFTv9WVrQ8DHkNsQSlhOkb9/rYQbYgmGChgmjzxbzaLtMphCw1Sywa0xTKzope83k59fcwwbpT1/2amAqQsIy2pwSE3MK/w+Ssl6gj5pzGDIoV8i2mItxNIvvMDiEDz9cTQbaSgyo4hYNPeEL2TYkMFA/gNR8SL9a/upEnxBX4COfj+0aN2N8CtzUl7wtwmshHeL6G7FIk+8QpoJvfTRSgARgY8lpmGqBXKaFKClTzTbkrVItTcsAHgYsxTM/65FVnQOhT7xujmWDRJtT/VFQ4LcwnC6YR8QzLD1p+WtXENUd3j0kyVqKpQvbr2JF7n0UbRe4qIDLTWUzP/OI+UtIzKLSkhm9LKzlKuP6g9Pkk8WqvfaQi3BE6+Fl7+BCdB6iYvZgkUK93Ds/0UYHuTSF6O4xJ52+XcoXmQ8ywxaB5jQcp4aiBu7AxW33hQODBavTj9FH02ysYEp0JWp9W6x+XrFhFz6MolMrLUF878KIJ+XyMV+CSpE4AGW9rOPWMoULm8DwINe+sg0GS32uGAgPLx9kYbA0Ia9Z3TjB/46GwrK2/LEP9vIhYQNmGAI/oZUiHx0eKEMDQUKL9dex8sGQ3CYgmKPT0+RD6bS9U5Q7DFrfXROQYkXbjG0RYqUet3CKyx6wmKPiQmFfUR+Byv1aHnLJrzXy6Aj+iVS7GVyRrxempV4yFfq3cJxJVmEpZ5zw6HlY4Pr5AE0a8yYr9S70U8LLjochjQzIjKJlHrkqJJiL6PVyV3qBccaUXFbgurBcoiVeqSPxJJN42UufJyWVTAEF3rtcQSLSOGzDJFiLxe8Uj95P61j83BlFlse9p5FWOrdIpMYwnCZ6AkVK/byQe/94ek6Ntf3faU0agQygS+ssH4OVBpllP6bLtAACMMzis/PVn7+mZHw6gLtTRoEEoDQPluS9L+RQFr4QECTWpLU0EAqEsj9IL5zSc03Rv7id7R6+8caYUpLut1lE3Mmrmd01suukwGUa1/ButaAEUZooaWW4AP9TRfoO7DwCxfoF89awIsLlJhUuECfwZCkbyQQCBLolSQ1JKmmgWQk0EuQVLu+vf0MJHwEBX81KemOLuuIC7USuJOEV9Ia0pI++Z3zDUj4685fB+PBmwfgvZCcn2hOIDlFEAicv0ho8MBFSkxKQJDUg2fi5fclJN0XKGaMS2gQrG8FOVySHK6fg3LLLXz2zTNpJICmORVY2kSS0kCOhf8FFv6boEnfpBYJSSOBIOjbP/NJP7pA34KCbxOS7gqkI8bLBu4yIPLBFpY+oDk+3sLCB2khwFQhCh2UASRyptIn4pxVbDktffjQijw8To5NB0Twu0jps+Qyb8hTBkRDAHDcwIRlAIaFgBDplDO0QdKgEMiouTqnay5DICwEOAjvRkvToBBwDI8pPJ1C/VSafgqXR2p7zzIIhiA5WCS2kDr9jHR6esmIrJHBMe5RI9UaBiOEA7zY4ITk1y2hLjC05QmXR/c7CMOI7DifQChIJj5RQxvpI93wCLJtGRlXkHyaKJA2HIKRDQUynJGvOnLFCN68LU6kq+FZQk8YBlJT3cJLOW7LLSR2WfrIlvEdDwoYRIZgeP0RKEwypftw10bX6KYjyLYl6TmRfJoII20wBGMrCmQ4I50p6Fx8w6IE7xYZF+HFMx1Y+T0dgoEb9q0DqWsapcmaoSXcsCzkDCHDP0DOM0gdGIqgQzHcZ0P7jCr5+Djtjcbd3LAc5DDT5aHeayF1YChA+R0dgrHj4yAkHx/1Fl4vtjZcStK34fLIrnfLPUgiNcrPZM1o/M4ROi0toHqjOzbaR7piSdopODGmjeEFqQNDGI+MgugvHAlpv9HORHZuJC3d7X1bkKFdIsujA6OD1IEB1okOQXKkhucFVUpan8lZgseZsRXpvi9H1wZ/3hh2le6H3hE6bVjgN5/ju4wEfyY39Ik3PT9/88dn2ugj/UUpSKeHto13nl4/YUEJNmlY4Mf/FR+C2LsMwu0vASbtDvVbTf58I5bW7Xi6egGGduu1bF1SYEoZGCRR//H/Yx8fAy77s1v+LaS8fuFivflOxo90+G3R2/H1mzZHGNDJo6R78o8Wt9JS7XOKNjBt9bEj16+pOMtWpAlcFLn75hwA3Jn58fuNXYaDl/jPL0K3jT4uLvHkD1RZP2weWBcEfJqkfeZ8brdGQE+1H3d7awPLRh9TXnnkPO8gbZ9BS005uqT09qhOcSsJdlS72+fA7RCwEg0i13fpMBPG1x/PC80dhr9t83t1U/DrRy0NAA==) Figure : PHY timing – clock output and data output ![PHY timing – clock output and data output](data:image/png;base64,UklGRmIUAABXRUJQVlA4TFYUAAAvo0OEAB8gEEjxaJktEEhGy2x1gUAyWmarz39U4QfArP6fI0mSAvLa4K8y4lrgT/Evg2yy7T7ylLOysKeoRxhR7ix+Wi08Ia4FfjLmCVbFKcCxEY6b/1m3v0m3+HtXr4rov0TJtqpWamtIGR+zQYxocn8A/9/3yVC/PT9KU/A/kAhImhKS2kP8nhkS0ugoaQ6hmQGpkz0fMpk+HwJsWjCA8wGprSDB1EJBxmQei0p59SLpWgg2SMBUAiqhgA3CpEcDWweRxT6WnFqCqQMAF6sowHRCV0GB4YLUGWQdJCAXRA4FVRCaD1ntBrYGYNgAtnIKLB8whzAV2JewSOoKCM0HXT3DB5MXDioAlkdYAahgyR2bWthMlgHXByEqoGsw1UEBZjLHMzW4Pl2aN2zua4tzvSQHGrziOrV4n3brgWQ2fTxbg3mH64pr20aP/l5q5UpAUlrhShMLpEmgF9gD5SR9BRoIXCADFkgcUahmpASaNLMt8t2dd7ib2qdmbe4z3bXQewmSlB9IaUipY4GABAIXKCcpgBfoZQ/zCq80DhSqGSnBC5SXNFe7hsztur8zTXTXQHjtQrwWkZTTBQLIkJY0gU6QkjPf6t5uHbd4Rh/t0KGejn5PDwQCV2oXx8nMCTplJiVpeiALGkgckZcze8G7XfNGzM6eofQqhQYSwh68iqziVuJ7rkBicubpEKoAczBRB3SQbEZN6xF0NsmBJ4Jev98510PI6kFNmvvle/hD9/bnea6SrgATt4fSZFMHU4wQBcDBNCNsNjyYZARUzzACC7CHEqwSJ0EVYY5l+aALkMcCPsj6IR9MCfpIilfqWJoP4kTZEuBIkld4LMMHqJ3gBBZhz4AqQxzK8kHXDrhljoRskGXIc2Aqp9ilD6T5IMpQ58BWTrILDmT4AGXgOcDKiRNluSUs/5SuHZwoZJfhnzSFyMOoE6W/hRO2EKWPIk+U+RYOaic4gYUgHMZ+h0XpcuxBAPklvpxIUzmlOWZOk3xsDeL9cKJ2shbtWgNbO1OPNcVaKaUfXPvucr+seJlwbk8N3tt1wnVu8DPOk2tx8n5ZgJUTth64myackP5VxolpiNlZf3h/a6c3nGqF8NiuIT/cQ7Rt05YG1YN6TM7sXPfFbetSlP5TmOphLabr7rKS4uQ0zor0bc9aLWEf20zQzQ5iKqd0Ndo7Qa/f1Ds8NXhpLnPLmyqnqV7SHEFywtbO1Ay/DdJMUYCktMKVRrpSq72MBQIaCNxTSBpIkEAkjtlzBgPpWKBiNSNxvEB5NTuOhA+kNKTUwpUg9zIWCGgg2OMoEsfSQCSO3nMGA+lYoMSa5QbKq5mtmyaAeiFevUCaBpLBQDohUBGBCmTW7FAKXAe1rhTGlVKTnguxQEADQTxQqKfTOOiKjApkBILMpJGa1f+YFQuugnDEKoAFN/vOkdLVaFe8HkyWJewDw/uZms/T/fJ2xbl9m3GdGCJNPa54b93juGu7m48gypLmsa3EjLv13LS7eZ3X3Tv86t29fZumc9IEfcb7dZraduaEsDXB3Uzc98UTlgZlKf3I2saZaOG0F1xPylch75ypPS2fndbbzKl7BvIom1StiuAb4V2/naYsVRjmSA4EWBu8t29Pb+vk3v7eNPGk0unbIGFLU4yQr7XT3yGSpjTJCPGhduY7REqXJhgBqnb2CwiwTRWHQc1lRWzvE7Y5APmgj0S+mrg2p2luW5zOibAxK75jkqzBus4ZlGaE+RbDODqJOBvSURHz6vWxFJIRwh5Dhswt+kwSwzm9EyHXBhuk9MlQDpiA9u6TwBs4xivYxFHsSwLBCSwPUEJqRoAUlnHoaE97eQu35hkxqZ+PrFH6IMlTCkDOCfsFypSkGCHNAeTOpl7xUmjmZWx2OrSE1NYSZ0PpkiMyyQhhD1FyjC0N78DdNSUukScDd0Kn1UGzBo4iE5kEghN4iBejEtkUlnfixWAi5JIuKHmcgqxR1QPkgz6E/LIhj6EKUpwwtdOVuWK7PhZ8XM2RBL/S+zaS0gpXGulKrfYyFkjTQKD39qCBBAlE4pg9ZzwQkEDRCqSRpjrN06XBCS8Tzm3kY/kDKQ0ptXAlyL1MCiQB9jiKxLE0kPACydRA0Qo8hHZtcJ3WqcHPOE8uSFmaAEG8EK+xQDIz0IOZiAn3Yo79dsl1Z1cK40qpXanAD/SBBNIuEJmBaFJpSE4dr4COVsCVaUR9rrt5mp11entq26dyFyg8ZpXEm8NEtrbr9z3kh9i067t2XYu11FGgGIhoLiu2F7xcjjTvJuKKU4vvWpyLXb6rh5FiRmzxju2B5vuupUVh4ji2EJVmxulA15B5LQts7XSSCecjrTv8TDd7EKYQmWo9UEPR63dRCrBywqRp8XBXvDSXuS1K6uPoYz3kw+TjvEIhYNNMD/lEzhzIHmieH5ACexhTiAJMu36vj/hYAzDR08WthyvOGYQpQuoEdET2iEtS4YrYrvcQZeOkLkJEedNvH3JJOu8cXgPtlvJdexFgEulHnLc5JpzyKLAF7Nnimsv9IQnATFOLGRBMARKQiUKCPpTQBQj9WATkTCZO2DQijYQCwPAB4yCinfyvW5MoMInSloSPnzSPyMSpoBbnAJMEQWcTgFHg6Grl/YouTkLk+o13/ycRaQSYTBJ0lCLgAVfBBEKH4BP6JKRRkD+ZKAn0ROIAmOSh+EsSFPnQFzl+YBgA6Q9mANKogq+R4yc0CzB0O7GGP0gToSz3L3L8JDAgo+YyTYExdgp6AnIgp1tUwm9YXil7DC+TYBXiMTP+dJ54W+WEipK/UDv2bVYHKojHbsbq0BOR+ev374VOXiKPwdmIDCWkLtFHYWuMTW/dEpmjMHbXhJjMHoav+2BEkQoPw9CTjfwaHyf1WdUJ+r339PE8FJj+33//15+ni3v/q7czLFa33ud2PUnthGdpmnA+SfN5Wj3SfjFq8fQI6/8lHNkMTgx4Zpxax54WRQVGZGBOi4T470hPi4jWWcJpARP7AzEFLycl5Uf8AKcl4e8xTotOaKjTKlKm73Sd6CpnuqMvvYGKBhNv8pcvvJsJNGd4e5j8V39gTgvG2fMiorB2nEz/B5Kho9PzL9127yFp0udg7MJ+BImTOQV9xPtUQPQFuhwAWL50YT+C9GaLn1vPkBGRJ27+RjJ0N3cmSO/kcHkW2nk29ON0YZBBc2XokO5scwQEQvW3wO5oniHsOQfwhLQj7THogPF4Le/nkmBJpyKbf2Miz6L93ugFE2CYQnqK25OjwAZbbQvubtf5XYsciUgD9l2w14HmydghtTkSwq22BHcnTKDBo0fCCxfqdQJ4MhBud47QQcPN62Mkog6cQtEjEQxHornG58i+xGtMykS6B90tBb3f3sGAwU/M4G65snitSICNnQeh3Sro/DMoGDDhE5NeGgxLui1IxU4EavRW/OR9JgYCZiyQmjPd5ousGCQ+Bc+t+BJE/9LAlzGwJmk3HTsPFq/tiH/1ulwgYMbBUMCSW5gwMbfwitr7WA8ETMvor8iQwd8yIH3Drz2bAzaFl5Evi3dyEGCjgm33Y+11uVRjbEOG+PvyIKZtSPwIaAbnFVLqED4YkiX+lont1gd31REDpXdZB0NqhnQROs7bkKwKNnBuwS5zQ44E9uW3W/quxptwesqkQ29Xh7tiuzYXbLChP22uj0n+CA/pNl/mro7X7J6+uvumCvyz55Zq9K9Vrv2ECbEZ+nrgG775sAaBy7ffbom7chZJoC9zV2CP1+AdrzX5K8+S6+YaTurQuYVpglUQR3PL25X66u2yTu3T/XDe5duTfFEenU05N1/uBVyY402+t6d396m9v9HPVlJa4UojXanVXqYHAhrIwgv8UZg90C+/0XsggECgPWcw0McfAcIGeo/zn6QCOq1mn967ev31M4nzCjpSgT1roMrJgXTEdTc1lwveG9ytV3JgP5DSkFILV4Lcy4xALyTOK4CLswf6+B5cIAgEMrFAzyQO5Nbsl3sgklSSKkCwAiRnoMrpgcIv94CVwDLCtUwm8r2UA9WYvZmwUD9Mmcntty/gnRkyfeaZJP0RCQShKqTN/JLMaDoDR8/gfI87epVP4Q9qd91KG5K5bdz/Jiy9OpMncrkjFQWHDz2vd7xX6Zbh5hmoLiB7pFKBdXevltilD8mGheSiXQ6cnIx1aFZ8aqryn7QP5BsIacaA/JEK2Ao0F6zQkqHz9NQtC8aGZPXdHlYFTM4wq992mlK5bjz5I72F9WU8ryCUHoJyn20Iw5StgI5a8vRBkhtf+7x2y2i0riPBvLurXB1PrHdSZ0MCoQ/KeIhDaX4tEVueIUixRqYZPLfgF3ki28aRZ2LMFfytgOfFYP7YUwFPblluEZhnDA+yWSPAZA2cgyDbwpCRGjwvObz/9ZeUNJg3yObMkqUL+9eAEoNspmSdCVRf1o0/MlX0xx+odK6RIwPVb8X8PKTEIJtXoVDdqVCZuhCZDTuG9BG6BKA3RBkWvnxDdJhnCelDStxN8GtwxlthG3OkybQFCJutZ0hHjGX0Tvfe+orcTfBCErdMLtXgEadmJJbCFuYIm2dYAgCzDfwYb8RQzthJkwljX4YwZMnkGq2nbucGia2wG3MA84w3n9L5Rn4MVF+Ky6l0rn4LMpxYqC3XHqujlpPTO1hYxxulM2HnkyYf8qM/AuQaliDNiY3osBCS4NwMy77SqZAmj3vHI2wB/XZ+xlsQcHLThM54K6dz7xSkuUVyDcu5WjyABQwLa4TNNZSBHU/GGzGU446ENCUJy44lF3bYn6gtSBdxYw1gHpeSUkWM3Biq1G8h0vBhIfqtGHcklD4xLliHp0Ln6yhpSsCOMyofFjIsLOk3oiuH3guVpDQ7MNvwDyfqFmbL2BgjTb6+I0QZ/QkabyEIbOhwtzdJQfQ3tmdm7JaThkUMC2OEzTeUgR1D9v3VT1heDEs55EjIU4PddioAi9HZvDqxbiyk34LMQ1BQeipXqHydP33snvPqqashq9KHZ76NYW9GQsm3peF6s+409YV0yB5hc3g3E4WHnjwbPeyPscdbQRu9D+YXdqV1pyj89DHTXgv+SFPCAQ/luFLuebIp+ayK48es3nc+J2m8lTEs/FE6xxL+XraQ7kQhT1+FbNn6zXOj37QzbFiIvpzxFJGUZfQbfxCy0B9ylf3ZD9M6DEMoRxqWf8hF4nVsG8va3y+jQwYJm2GP5hO2jOFELfRXpfz+IDpgc4TlF3bEWFB/kjoswNWBQ9Jk2KP5ALOF/j8N7BqWGGnKQUZ4fypWikvAtr4YujAuNSOHlM6BnUfpQjrkWb/FKF0KaE4sRL+Vsr/PtqGooQRSBQ4hZHDvD4sjTRkj17o4KOBGGIYsuTCgI8k4Nt6IoQxyFArokEXCZln6zRGFDEwbncFnHZtvISxDbpluQe8dwTDsiLGMzumzjTceSZOMrNehA4X0TBsi0DH5NgIZ0mVaQgZCcqz/hnTrIrpChoVHSufA7ub8XBfSOYpffZAilM5HM/LimdrybCX1fBmovhyZb+MRQpZ+IX5JQK6RHgx+dRiHjBuWanR8GWNe8ol89LDxR6QZIz5tNGAumpEntyy3kkbGIDV6IFVoR5DtxiWZZojwdgumyL0ET7osSxhNIZMNnPma3pTnondNZSxn4OYoPdw8Je4lWKPS9BHjzQtY5F6CG3/0OnmOjZ713VbExhhZztLvpBk7T4khNmswTRfhnVzJujDDjf/0Pr08OUPsfonIG2IzbfRsLprYbSXQwQxXvLFnPuudXCLRGGGPdsV2fXrDph6faNPk8Eae/+VGLVTeyLMSze7ytNZKphg8JBr43USaEiPPGrT39l6fLsNyHDxe065YFTq28OiMIbabUxB6alHgsfnx2rVp0GmfvnfBp7d2vVaud8i7O404ekqMPCswee6XZr037f1OagOkFNaV0uylVjotjlGRQC/wRxLol9+4QADhpMFAH3+0B9pA74E+kUAQqEIw56dvXM3++kckjgadUeXkQDrmupsbF6BdscH7iihBwYe9tGBcKfRegoS0OFpGAoEX6ON7EghCSWOBnkkg2AP9kgSCQBWCOX/5Xrukz0CrABlVTg8Uebn7kHoiPhCG0CHhQBpIHEG8EK+EBgeE4wfyku72pMQLjUPs8SFWM4rW7H3Qa2KVkwNFzW7G0+zrkE8c13OtK4VxpdSuVFAg0Av8Kwn08XkPRAtFcwLN+ZHm/PM9zgJmj/PpvQsEL0k1+yVN+kwCvQJEqkxySlDxmolQBWLme9B1L47e7J/ppci/kbfpAzL3WS6sf9GSUOCBrD18Fbze2zXg3uD31qN1tHE8JnlA5tyoJd1wC4IarO1ehtzvB7OezpM8ICNtDc5A6QzdRuDxmhXfntbm8o54atfK6NRxCtEBbcZ0/VKfpzf0PF3a9Xq4zWsW51VnjFMQqbEjASGd9+xjx83toe0jIPVJFfGjbN0WpDmyeN3AMZD8AIfQXhQS0CYKDMI5MsTYnCvV11TvydyXNBzxL+CESNRthPFakAQ0mfsSHBmpsaNMzpVK/KuXxZE6d1+WI12Y1En2aMQnqqOSt2QMUthtSfol2EfAewpCKMjcEpAlG7XQdsv4AFcQutRLg/EVx9iWLAntKqHdRmJPRgUSOvEVh8itBFP8DSmTvqXUNOEelNDRJd6aBBiWDIENabulrOltaYbO6zOOhOiS4JoKLEsCG2603VLWpMHAjH4jLtKQRkw6u7ybEmRJcMV4u3mN5q1psfNOIfIXY6Aj8134JxaaKf4p3zn+guB+af+R4KLdaMLnnQAbfPUTbfR2miv+Kb85AoKfa14ev3eMnTc9/7LrfgQ5k2VK4JS/OdJ78fOQ88SPE9bl0MgU7Ap1EOvaPOw555UtfaSDvM/rHWOAS5jxypYxKOPFRuKazDoxhX7OFeggGvlXrt3+FxJkjT1NCotRlmX/42JC) The supported PHY timing parameters for 1.8 V systems are listed here. Table : PHY timing parameters (1.8 V systems) | Name | Description | Min | Max | Unit | | --- | --- | --- | --- | --- | | f\_Clock\_small\_1V8 | Frequency of clock signal in small systems | – | 12.288 | MHz | | t\_High\_Clock\_small\_1V8 | Duration of high half-period on clock output signal in small systems | 35.3 | – | ns | | t\_Low\_Clock\_small\_1V8 | Duration of Low half-period on Clock output signal in small systems | 35.3 | – | ns | | t\_DZ\_Data\_1V8 | Time to disable data output signal after positive or negative edge on clock input signal | – | 4 | ns | | t\_ZD\_Data\_1V8 | Time to enable data output signal after positive or negative edge on clock input signal | 7.9 | – | ns | | t\_OV\_Data\_small\_1V8 | Time to valid data output signal after positive or negative edge on clock input signal in small systems | – | 27.6 | ns | | t\_OH\_Data\_1V8 | Time for the data output signal to remain enabled and valid after first becoming
valid | 6.7 | – | ns | | t\_ISetup\_min\_Data\_1V8 | Input setup time | 4 | – | ns | | t\_IHold\_min\_Data\_1V8 | Input hold time | – | 5 | ns | | DC\_Out\_Clock | Duty cycle generated at clock output signal. Calculated from
t\_Low\_Clock/(t\_Low\_Clock + t\_High\_Clock) | 46% of the SWR clock | 54% of the SWR clock | ns | ### SLIMbus interface Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The supported SLIMbus standards and their exceptions are listed here. Table : Supported SLIMbus standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *MIPI Alliance Specification for Serial Low-power Interchip Media Bus Version 1.01.01* | None | ### I²S interfaces Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) There are two supported I²S interface types: - Legacy I²S interfaces for primary and secondary microphones and speakers - The multiple I²S (MI2S) interface for microphone and speaker functions The following information applies to both interface types. The supported I²S standards and their exceptions are listed here. Table : Supported I²S standards and exceptions | Applicable standards | Feature exceptions | | :---: | :---: | | *Philips I²S Bus Specifications revised June 5, 1996* | None | Figure : I²S timing diagram Page-1 Sheet.49 Sheet.449 Sheet.450 High-level I2S timing High-level I2S timing Sheet.288 Sheet.289 Sheet.290 Sheet.291 Sheet.292 Sheet.293 Sheet.294 Sheet.295 Sheet.296 Sheet.302 Sheet.306 SCK SCK Sheet.307 SD and WS transmitter SD and WS transmitter Sheet.308 T T Sheet.309 Sheet.310 Sheet.312 Sheet.313 Sheet.314 t(HC) t(HC) Sheet.315 Sheet.316 Sheet.317 Sheet.318 Sheet.319 Sheet.320 Sheet.321 Sheet.322 Sheet.323 Sheet.326 Sheet.327 Sheet.328 Sheet.329 t(htr) t(htr) Sheet.336 Sheet.337 Sheet.338 Sheet.339 Sheet.340 Sheet.341 Sheet.342 Sheet.343 Sheet.344 Sheet.345 Sheet.346 Sheet.451 Sheet.452 Sheet.453 Sheet.454 Sheet.455 Sheet.456 Sheet.457 Sheet.458 Sheet.459 Sheet.460 Sheet.461 Sheet.462 Sheet.463 Sheet.464 Sheet.465 Sheet.466 Sheet.467 Sheet.468 Sheet.469 Sheet.470 Sheet.471 Sheet.472 Sheet.473 Sheet.474 Sheet.475 Sheet.476 Sheet.477 Sheet.478 Sheet.479 Sheet.480 Sheet.481 Sheet.482 Sheet.483 SCK SCK Sheet.484 Sheet.485 Sheet.490 Sheet.486 Sheet.487 Sheet.488 Sheet.489 Sheet.491 Sheet.492 Sheet.493 Sheet.494 Sheet.495 Sheet.496 WS WS Sheet.497 Sheet.498 Sheet.499 Sheet.500 Sheet.501 Sheet.502 Sheet.503 Sheet.504 Sheet.505 Sheet.506 Sheet.507 Sheet.508 Sheet.509 Sheet.510 Sheet.511 SD SD Sheet.512 Sheet.513 Sheet.514 Sheet.515 Sheet.516 Sheet.517 Sheet.518 Sheet.519 Sheet.520 Sheet.521 Sheet.522 Sheet.523 Sheet.524 Sheet.525 Sheet.526 LSB LSB Sheet.527 MSB MSB Sheet.528 Sheet.529 Sheet.530 Sheet.531 Sheet.532 Sheet.533 Sheet.534 Sheet.535 Sheet.536 Sheet.537 Sheet.538 Sheet.539 Sheet.542 Sheet.543 Sheet.546 LSB LSB Sheet.547 MSB MSB Sheet.540 Sheet.541 Sheet.544 Sheet.545 Sheet.548 Sheet.549 Sheet.550 Sheet.551 Sheet.552 Sheet.553 Sheet.554 Word (n – 1) right channel Word (n – right channel Sheet.555 Word (n) left channel Word (n) left channel Sheet.556 Word (n + 1) right channel Word (n + 1) right channel Sheet.351 Sheet.349 Sheet.350 Sheet.352 Sheet.353 Sheet.354 Sheet.355 Sheet.356 Sheet.357 Sheet.358 Sheet.359 Sheet.360 Sheet.298 Sheet.300 Sheet.301 Sheet.305 Sheet.361 Sheet.362 Sheet.363 Sheet.364 Sheet.365 Sheet.366 Sheet.367 Sheet.368 Sheet.297 V(hi) = 2.0 V V(hi) = 2.0 V Sheet.369 V(lo) = 0.8 V V(lo) = 0.8 V Sheet.370 Sheet.371 Sheet.372 Sheet.373 Sheet.374 Sheet.375 Sheet.376 t(LC) t(LC) Sheet.377 Sheet.347 Sheet.348 Sheet.378 Sheet.379 Sheet.380 Sheet.381 Sheet.382 Sheet.383 Sheet.384 Sheet.385 Sheet.386 Sheet.387 Sheet.388 Sheet.389 Sheet.390 Sheet.335 Sheet.391 Sheet.392 Sheet.393 t(dtr) t(dtr) Sheet.324 Sheet.325 Sheet.330 Sheet.331 Sheet.332 Sheet.333 Sheet.334 Sheet.394 Sheet.395 Sheet.396 Sheet.397 Sheet.398 Sheet.399 Sheet.400 Sheet.401 Sheet.402 Sheet.1 SD and WS receiver SD and WS receiver Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 t(sr) t(sr) Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 t(hr) t(hr) Sheet.50 I2S timing details – Tx and Rx I2S timing details – Tx and Rx The supported I²S interface timings are listed here. | Parameter | Parameter | Comments | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | --- | | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | | Frequency [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_I2S-interfaces) | Frequency [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_I2S-interfaces) | – | – | – | 24.576 | MHz | | T | Clock period | – | 40.69 | – | – | ns | | **t**(HC) | Clock high | – | 0.45 × T | – | 0.55 × T | ns | | **t**(LC) | Clock low | – | 0.45 × T | – | 0.55 × T | ns | | **t**(sr) | SD and WS input setup time | – | 8.14 | – | – | ns | | **t**(hr) | SD and WS input hold time | – | 1.5 | – | – | ns | | **t**(dtr) | SD and WS output delay | – | – | – | 6.1 | ns | | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | | Frequency | Frequency | – | – | – | 24.576 | MHz | | T | Clock period | – | 40.69 | – | – | ns | | **t**(HC) | Clock high | – | 0.40 × T | – | 0.60 × T | ns | | **t**(LC) | Clock low | – | 0.40 × T | – | 0.60 × T | ns | | **t**(sr) | SD and WS input setup time | – | 8.14 | – | – | ns | | **t**(hr) | SD and WS input hold time | – | 1.5 | – | – | ns | | **t**(dtr) | SD and WS output delay | – | – | – | 6.1 | ns | [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_1_I2S-interfaces) Load capacitance is between 10 pF and 40 pF. ### Touchscreen connections Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) Touchscreen panels are supported using I²C buses ([I²C/I3C interface](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#arb1612792921091)) and GPIOs configured as discrete digital inputs ([Digital-logic characteristics](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603)). Additional specifications are not required. ### I²C/I3C interface Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The supported I²C standards and their exceptions are listed here. Table : Supported I²C standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *I²C Specification, version 3.0* | HS mode, slave mode, multi-master mode, and 10‑bit addressing are not supported. | | *I3C Specification, version 1.0* | Ternary, multi-master, HCI are not supported. | ### Serial peripheral interface Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The QCS6490 and QCS5430 chipsets support SPI as a master only. Figure : SPI master timing diagram Page-1 Sheet.93 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 50% clock duty cycle is shown, but is not a requirement. 50% clock duty cycle is shown, but is not a requirement. Sheet.8 SPI_CLK SPI_CLK Sheet.9 SPI_DATA_MOSI SPI_DATA_MOSI Sheet.10 T T Sheet.11 Sheet.12 t(mov) t(mov) Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 SPI_DATA_MISO SPI_DATA_MISO Sheet.60 Sheet.61 t(mis) t(mis) Sheet.62 Sheet.63 Sheet.64 Sheet.65 t(mih) t(mih) Sheet.66 Sheet.67 t(mov) value is positive if after clock transition (shown); n... t(mov) value is positive if after clock transition (shown); negative if before. Sheet.68 Sheet.69 SPI_CS_N SPI_CS_N Sheet.70 SPI_CS_N to SPI_CLK timing is fixed at 1 clock period. SPI_CS_N to SPI_CLK timing is fixed at 1 clock period. Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 T T Sheet.83 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Sheet.90 Sheet.91 Sheet.92 The supported SPI master timing characteristics are listed here. Table : SPI master timing characteristics | Parameter | Comments | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | | T (SPI clock period) [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_serial-peripheral-interface) | 50 MHz maximum | 20 | – | – | ns | | t(ch) | Clock high | 8 | – | – | ns | | t(cl) | Clock low | 8 | – | – | ns | | t(mov) | Master output valid | -5 | – | 5 | ns | | t(mis) | Master input setup | 5 | – | – | ns | | t(mih) | Master input hold | 1 | – | – | ns | [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_1_serial-peripheral-interface) The minimum clock period includes 1% jitter of maximum frequency. ## Internal functions Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) Some internal functions require external interfaces to enable their operation. These include clock generation, modes and resets, and JTAG functions. ### Clocks Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) Clocks that are specific to particular functions are addressed in the corresponding topics of this document. Others are specified here. ### 19.2 MHz CXO input Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The following figure shows the XO timing parameters. Figure : XO timing parameters Page-1 Sheet.57 Sheet.1 XO XO Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 T T Sheet.44 t(xol) t(xol) Sheet.45 t(xol) t(xol) Sheet.46 t(xoh) t(xoh) Sheet.47 T T Sheet.48 t(xoh) t(xoh) Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Average Average Sheet.56 (DC component) (DC component) The supported XO timing parameters are listed here. | Parameter | Parameter | Comments[^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_19-2-MHz-CXO-input) | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | --- | | t(xoh) | XO logic high | – | 22.6 | – | 29.5 | ns | | t(xol) | XO logic low | – | 22.6 | – | 29.5 | ns | | T | XO clock period | – | – | – | – | ns | | 1/T | Frequency | 19.2 MHz must be used. | – | – | – | MHz | [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_1_19-2-MHz-CXO-input) For more information, see the [GPS Quality, 19.2 MHz 2520 Package Size, Crystal and TH+Xtal Mini-Specification (80-V9690-24).](https://docs.qualcomm.com/bundle/80-V9690-24/resource/80-V9690-24.pdf) ### Sleep clock Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The following figure shows the sleep-clock timing parameters. Figure : Sleep-clock timing parameters Page-1 Sheet.61 Sheet.1 Sleep clock Sleep clock Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 T T Sheet.43 t(xol) t(xol) Sheet.44 t(xol) t(xol) Sheet.45 t(xoh) t(xoh) Sheet.46 T T Sheet.47 t(xoh) t(xoh) Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Average Average Sheet.54 (DC component) (DC component) Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Vpp Vpp The supported sleep-clock timing parameters are listed here. | Parameter | Parameter | Comments | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | --- | | t(xoh) | Sleep-clock logic high | – | 4.58 | – | 25.94 | µs | | t(xol) | Sleep-clock logic low | – | 4.58 | – | 25.94 | µs | | T | Sleep-clock period | – | – | 30.518 | – | µs | | F | Sleep-clock frequency | F= 1/T | – | 32.768 | – | kHz | | Vpp | Peak-to-peak voltage | – | – | 1.8 | – | V | ### Modes and resets Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) Mode and reset functions are basic digital I/Os that meet the performance specifications in [Digital-logic characteristics](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#nmg1612775927603). ### JTAG Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The following figure shows the JTAG interface timing diagram. Figure : JTAG interface timing diagram Page-1 Sheet.95 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.71 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 t(do) t(do) Sheet.84 t(htdi) t(htdi) Sheet.85 t(sutdi) t(sutdi) Sheet.86 t(htms) t(htms) Sheet.87 t(sutms) t(sutms) Sheet.88 t(tckl) t(tckl) Sheet.89 t(tckh) t(tckh) Sheet.90 t(tckcy) t(tckcy) Sheet.91 TCK TCK Sheet.92 TMS TMS Sheet.93 TDI TDI Sheet.94 TDO TDO The supported JTAG interface timing characteristics are listed here. | Parameter | Parameter | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | | t(tckcy) | TCK period | 50 | – | – | ns | | t(tckh) | TCK pulse width high | 20 | – | – | ns | | t(tckl) | TCK pulse width low | 20 | – | – | ns | | t(sutms) | TMS input setup time | 5 | – | – | ns | | t(htms) | TMS input hold time | 20 | – | – | ns | | t(sutdi) | TDI input setup time | 5 | – | – | ns | | t(htdi) | TDI input hold time | 20 | – | – | ns | | t(do) | TDO data output delay | – | – | 15 | ns | ### SWD Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The following figure shows the SWD write and read AC timing diagram. Figure : SWD write and read AC timing diagram Page-1 Sheet.1 The supported AC timing parameters are listed here. | Parameter[^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_SWD) | Parameter[^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fntarg_1_SWD) | Min | Max | Unit | | --- | --- | --- | --- | --- | | **T**os | SWDIO output skew to the falling edge of SWDCLK | -1 | T - 7.5 | ns | | **T**su | Input setup time between SWDIO and the rising edge of SWDCLK | 6.5 | s | ns | | **T**hd | Input hold the time between SWDIO and the rising edge of SWDCLK | 6.5 | – | ns | [^1^](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html#fnsrc_1_SWD) SWDCLK runs at 20 MHz or lower. ## RF front end (RFFE) Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The supported RFFE standards and their exceptions are listed here. Table : Supported RFFE standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *MIPI Alliance Specification for RF Front-End Control Interface version 2.0* | None | ## System power management interface (SPMI) Source: [https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-23889-1/topic/electrical-specifications.html) The supported SPMI standards and their exceptions are listed here. Table : Supported SPMI standards and exceptions | Applicable standard | Feature exceptions | | :---: | :---: | | *MIPI Alliance Specification for System Power Management Interface (SPMI) version 1.0* | None | Last Published: Sep 23, 2025 [Previous Topic Pin definitions](https://docs.qualcomm.com/bundle/publicresource/80-23889-1/topics/pin-definitions.md) [Next Topic Mechanical information](https://docs.qualcomm.com/bundle/publicresource/80-23889-1/topics/mechanical-information.md)