# Introduction
Source: [https://docs.qualcomm.com/doc/80-30843-1/topic/Introduction.html](https://docs.qualcomm.com/doc/80-30843-1/topic/Introduction.html)
This topic provides the functional block diagram and the device features.
**Document updates**
See the [Revision history](https://docs.qualcomm.com/doc/80-30843-1/topic/Revision_history.html) for details on the changes included in this revision.
## Functional block diagram
Source: [https://docs.qualcomm.com/doc/80-30843-1/topic/Introduction.html](https://docs.qualcomm.com/doc/80-30843-1/topic/Introduction.html)
This functional block diagram shows the overall representation of the subsystems on this
chipset.
Figure : QRB2210 functional block diagram
## QRB2210 features
Source: [https://docs.qualcomm.com/doc/80-30843-1/topic/Introduction.html](https://docs.qualcomm.com/doc/80-30843-1/topic/Introduction.html)
This table lists the comprehensive features of the QRB2210 chipset
and its capabilities.
Note: Some hardware features integrated within the QRB2210 chip must be enabled by software. See the latest revision of the
applicable software release notes to identify the enabled QRB2210
features.
### Processors
| Function | Description |
| :---: | :---: |
| Applications | 64‑bit applications processor
Arm Cortex-A53 quad-cores at 2.0 GHz with 512 kB L2 cache
|
| Always-on system | Always-on subsystem with always-on processor power management (RPM) for voltage control and regulation, clock management, and resource communication |
| LPASS | QDSP6 v66 K
512 kB L2 cache
Audio and sensor processing
|
### Memory support
| Function | Description |
| :---: | :---: |
| System memory via EBI |
Dual-channel non-PoP high-speed memory – LPDDR4X SDRAM designed for a 1804 MHz clock (2 × 16-bit)
Single-channel non-PoP high-speed memory – LPDDR3 SDRAM designed for a 933 MHz clock (1 × 32-bit)
|
### External memory
| Function | Description |
| :---: | :---: |
| Via | eMMC 5.1 and SD 3.0 |
### RF support
| Function | Description |
| :---: | :---: |
| WLAN/Bluetooth | Yes (with WCN3910 and WCN3950) |
| Antenna sharing | Antenna shared between Wi-Fi and WAN |
### Multimedia
| Function | Description |
| --- | --- |
| ***Display support*** | ***Display support*** |
| MIPI-DSI | One 4-lane DSI D-PHY 1.2 port, up to 1.5 Gbps per lane with split link support |
| General display features |
HD+, 720 × 1680 at 60 Hz, 10-bit end-to-end, and up to four hardware layer composition
Features Qualcomm® Low-Power Picture Enhancement (SVI, CABL, VRR, and Q-Sync) and Qualcomm® True Palette Display (color tuning, picture adjust, and gamut mapping)
|
| Mobile display processor | Adreno DPU 920 |
| ***Camera support*** | ***Camera support*** |
| Camera interfaces | 2x ISP (13 MP + 13 MP or 25 MP) at 30 fps ZSL |
| MIPI-CSI | MIPI combination D-PHY 1.2 /C-PHY 1.0 configurable in 4/4 or 4/2/1
D-PHY: 2.5 Gbps/lane
C-PHY: ~10 Gbps (3.42 Gbps/trio on three trios per port)
SWR: SoundWire interface (two Tx and two Rx data lines) for codec
Digital mic: Four DMICs
4 × MI2S: Three MI2S with 2x data lanes to support full duplex stereo, or up to 4 channel Tx/Rx application
One MI2S supports four data lanes for up to eight channels Tx/Rx application |
| Voice codec | EVS, EVRC, EVRC-B, EVRC-WB
G.711 and G.729A/AB
GSM-FR, GSM-EFR, and GSM-HR
AMR-NB and AMR-WB |
| Voice processing | Qualcomm® Noise and Echo Cancellation and Qualcomm® Voice Suite |
| Audio codec support | MP3; AAC; HE AAC v1, v2; FLAC; APE; ALAC; AIFF |
| Enhanced audio | DSP-offload for low-power audio playback |
| Sensors | QUP (×4 in LPI) dedicated for sensors |
### Connectivity
| Interface | Description |
| :---: | :---: |
| Qualcomm universal peripheral (QUP) ports | 10 serial engines |
| UART | UART interface; six on GPIO and three on LPI GPIO |
| I^2^C | I^2^C interface; six on GPIO and three on LPI GPIO for touch, sensors, and NFC; dedicated controller for each port |
| I3C | I3C interface; one on GPIO and two on LPI GPIO |
| SPI | SPI interfaces; six on GPIO and one on LPI GPIO for sensors and so on. |
| CCI I^2^C | Two dedicated I^2^C interfaces for camera. |
| USB | USB 3.1 Type-C/Micro USB |
| PWM | Nine |
| Secure digital interfaces |
8‑bit port SDC1 and 4‑bit port SDC2; eMMC5.1 and SD 3.0