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# Pin definitions Source: [https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html) This topic explains the pin assignments of the QRB2210 chipsets. The figure and table within this topic provide details on pinouts, pad attributes, and their corresponding definitions. ## I/O parameter definitions Source: [https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html) | **Symbol** | **Description** | | --- | --- | | ***Pad attribute*** | ***Pad attribute*** | | AI | Analog input (does not include pad circuitry) | | AO | Analog output (interfaces does not include pad circuitry) | | B | Bidirectional digital with CMOS input | | DI | Digital input (CMOS) | | DO | Digital output (CMOS) | | H | High-voltage tolerant | | S | Schmitt trigger input | | Z | High impedance (Hi-Z) output | | ***Pad pull details for digital I/Os*** | ***Pad pull details for digital I/Os*** | | nppdpukp | Programmable pull resistor. The default pull direction is indicated using capital letters and is a prefix to other programmable options:

NP: pdpukp = default no-pull with programmable options following the colon (:)

PD: nppukp = default pull-down with programmable options following the colon (:)

PU: nppdkp = default pull-up with programmable options following the colon (:)

KP: nppdpu = default keeper with programmable options following the colon (:) | | KP | Contains an internal weak keeper device (keepers cannot drive external buses) | | NP | Contains no internal pull | | PU | Contains an internal pull-up device | | PD | Contains an internal pull-down device | | ***Pad voltage groupings for baseband circuits*** | ***Pad voltage groupings for baseband circuits*** | | EBI | Pad group for EBI pads | | P2 | Pad group 2 (SDC2); 1.8 V or 2.95 V | | P3 | Pad group 3 (most peripherals); 1.8 V | | P5 | Pad group 5; 1.8 V or 2.95 V | | P6 | Pad group 6; 1.8 V or 2.95 V | | P7 | Pad group 7 (eMMC); tied to VDD\_P7 pins (1.8 V only) | | P11 | Pad group 11 (CXO); 1.8 V | | CSI | Supply voltage for MIPI\_CSI circuits and I/Os; tied to VDD\_MIPI\_CSI\_1P2 (1.2 V) | | DSI | Supply voltage for MIPI\_DSI circuits and I/Os; tied to VDD\_MIPI\_DSI\_1P2 (1.2 V) | ## Pin assignments Source: [https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html) ### Pin map Source: [https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html) The QRB2210 is available in the package NSP752. A high-level view of the pin assignments is shown in the following figure. For more information about package details and to create printed circuit board (PCB) footprint, see [Mechanical information](https://docs.qualcomm.com/doc/80-30843-1/topic/Mechanical_information.html). [QRB2210 Pin Assignment and GPIO Configuration Spreadsheet (80-30843-1A)](https://docs.qualcomm.com/bundle/80-30843-1A/resource/80-30843-1A.xlsm) lists all QRB2210 pad numbers (in alphanumeric order), pad names, pad voltages, pad types, and functional descriptions. Figure : QRB2210 pin assignments ### Pin descriptions Source: [https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html) The pins are described in [Table : Pin descriptions – general pins](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__table_z14_znd_kkb) through [Table : Pin descriptions – DNC, ground, and power-supply pins](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__table_l3s_tff_kkb). | Pad number | Pin name | Pad name or alternate function | Pad characteristics | Pad characteristics | Functional description | | --- | --- | --- | --- | --- | --- | | Pad number | Pin name | Pad name or alternate function | Pad voltage | Pad type | Functional description | | N2 | CSI0\_A0\_CLK\_M | – | CSI | AI, AO | MIPI CSI 0 (DPHY), differential clock – minus

MIPI CSI 0 (CPHY), trio lane 0 – A | | P2 | CSI0\_A1\_LN1\_P | – | CSI | AI, AO | MIPI CSI 0 (DPHY), differential lane 1 – plus

MIPI CSI 0 (CPHY), trio lane 1 – A | | R2 | CSI0\_A2\_LN2\_M | – | CSI | AI, AO | MIPI CSI 0 (DPHY), differential lane 2 – minus

MIPI CSI 0 (CPHY), trio lane 2 – A | | N3 | CSI0\_B0\_LN0\_P | – | CSI | AI, AO | MIPI CSI 0 (DPHY), differential lane 0 – plus

MIPI CSI 0 (CPHY), trio lane 0 – B | | P3 | CSI0\_B1\_LN1\_M | – | CSI | AI, AO | MIPI CSI 0 (DPHY), differential lane 1 – minus

MIPI CSI 0 (CPHY), trio lane 1 – B | | R3 | CSI0\_B2\_LN3\_P | – | CSI | AI, AO | MIPI CSI 0 (DPHY), differential lane 3 – plus

MIPI CSI 0 (CPHY), trio lane 2 – B | | N4 | CSI0\_C0\_LN0\_M | – | CSI | AI, AO | MIPI CSI 0 (DPHY), differential lane 0 – minus

MIPI CSI 0 (CPHY), trio lane 0 – C | | R1 | CSI0\_C1\_LN2\_P | – | CSI | AI, AO | MIPI CSI 0 (DPHY), differential lane 2 – plus

MIPI CSI 0 (CPHY), trio lane 1 – C | | R4 | CSI0\_C2\_LN3\_M | – | CSI | AI, AO | MIPI CSI 0 (DPHY), differential lane 3 – minus

MIPI CSI 0 (CPHY), trio lane 2 – C | | N1 | CSI0\_NC\_CLK\_P | – | CSI | AI, AO | MIPI CSI 0 (DPHY), differential clock – plus

MIPI CSI 0 (CPHY), no connect | | T2 | CSI1\_A0\_CLK\_M | – | CSI | AI, AO | MIPI CSI 1 (DPHY), differential clock – minus

MIPI CSI 1 (CPHY), trio lane 0 – A | | U2 | CSI1\_A1\_LN1\_P | – | CSI | AI, AO | MIPI CSI 1 (DPHY), differential lane 1 – plus

MIPI CSI 1 (CPHY), trio lane 1 – A | | V2 | CSI1\_A2\_LN2\_M | – | CSI | AI, AO | MIPI CSI 1 (DPHY), differential lane 2 – minus

MIPI CSI 1 (CPHY), trio lane 2 – A | | T3 | CSI1\_B0\_LN0\_P | – | CSI | AI, AO | MIPI CSI 1 (DPHY), differential lane 0 – plus

MIPI CSI 1 (CPHY), trio lane 0 – B | | U3 | CSI1\_B1\_LN1\_M | – | CSI | AI, AO | MIPI CSI 1 (DPHY), differential lane 1 – minus

MIPI CSI 1 (CPHY), trio lane 1 – B | | V3 | CSI1\_B2\_LN3\_P | – | CSI | AI, AO | MIPI CSI 1 (DPHY), differential lane 3 – plus

MIPI CSI 1 (CPHY), trio lane 2 – B | | T4 | CSI1\_C0\_LN0\_M | – | CSI | AI, AO | MIPI CSI 1 (DPHY), differential lane 0 – minus

MIPI CSI 1 (CPHY), trio lane 0 – C | | V1 | CSI1\_C1\_LN2\_P | – | CSI | AI, AO | MIPI CSI 1 (DPHY), differential lane 2 – plus

MIPI CSI 1 (CPHY), trio lane 1 – C | | V4 | CSI1\_C2\_LN3\_M | – | CSI | AI, AO | MIPI CSI 1 (DPHY), differential lane 3 – minus

MIPI CSI 1 (CPHY), trio lane 2 – C | | T1 | CSI1\_NC\_CLK\_P | – | CSI | AI, AO | MIPI CSI 1 (DPHY), differential clock – plus

MIPI CSI 1 (CPHY), no connect | | U29 | CXO | – | PX\_11 | DI | Core crystal oscillator (digital 19.2 MHz system clock) | | D26 | DDR\_RESET\_N | – | EBI | DO | LPDDRx reset (shared by EBIs) | | P27 | DSI0\_CLK\_M | – | DSI | AI, AO | MIPI DSI0 (DPHY), differential clock ‒ minus | | R28 | DSI0\_CLK\_P | – | DSI | AI, AO | MIPI DSI0 (DPHY), differential clock ‒ plus | | P30 | DSI0\_LN0\_M | – | DSI | AI, AO | MIPI DSI0 (DPHY), differential lane 0 ‒ minus | | R30 | DSI0\_LN0\_P | – | DSI | AI, AO | MIPI DSI0 (DPHY), differential lane 0 ‒ plus | | M30 | DSI0\_LN1\_M | – | DSI | AI, AO | MIPI DSI0 (DPHY), differential lane 1 ‒ minus | | M29 | DSI0\_LN1\_P | – | DSI | AI, AO | MIPI DSI0 (DPHY), differential lane 1 ‒ plus | | N29 | DSI0\_LN2\_M | – | DSI | AI, AO | MIPI DSI0 (DPHY), differential lane 2 ‒ minus | | P29 | DSI0\_LN2\_P | – | DSI | AI, AO | MIPI DSI0 (DPHY), differential lane 2 ‒ plus | | N28 | DSI0\_LN3\_M | – | DSI | AI, AO | MIPI DSI0 (DPHY), differential lane 3 ‒ minus | | N27 | DSI0\_LN3\_P | – | DSI | AI, AO | MIPI DSI0 (DPHY), differential lane 3 ‒ plus | | L30 | DSI0\_REXT\_PLL | – | DSI | AI, AO | DSI external resistor | | M27 | DSI1\_CLK\_M | – | DSI | AI, AO | MIPI DSI1 (DPHY), differential clock ‒ minus | | M28 | DSI1\_CLK\_P | – | DSI | AI, AO | MIPI DSI1 (DPHY), differential clock ‒ plus | | F14 | EBI01\_CAL | – | EBI | AI | EBI01 calibration resistor | | D9 | EBI0\_LP4X\_CA0\_LP3\_CS0 | – | EBI | DO | EBI0 LPDDR4X command/address 0

LP3 chips select 0 | | B10 | EBI0\_LP4X\_CA1\_LP3\_CS1 | – | EBI | DO | EBI0 LPDDR4X command/address 1

LP3 chips select 1 | | A8 | EBI0\_LP4X\_CA2 | – | EBI | DO | EBI0 LPDDR4X command/address 2 | | B8 | EBI0\_LP4X\_CA3\_LP3\_CA3 | – | EBI | DO | EBI0 LPDDR4X command/address 3

LP3 command/address 3 | | B9 | EBI0\_LP4X\_CA4\_LP3\_CA4 | – | EBI | DO | EBI0 LPDDR4X command/address 4

LP3 command/address 4 | | E7 | EBI0\_LP4X\_CA5\_LP3\_CA1 | – | EBI | DO | EBI0 LPDDR4X command/address 5

LP3 command/address 1 | | E8 | EBI0\_LP4X\_CKE0\_LP3\_CKE0 | – | EBI | DO | EBI0 LPDDR4X clock enable 0

LP3 clock enable 0 | | E9 | EBI0\_LP4X\_CKE1 | – | EBI | DO | EBI0 LPDDR4X clock enable 1 | | E10 | EBI0\_LP4X\_CK\_C | – | EBI | DO | EBI0 LPDDR4X differential clock ‒ minus | | D10 | EBI0\_LP4X\_CK\_T | – | EBI | DO | EBI0 LPDDR4X differential clock ‒ plus | | D7 | EBI0\_LP4X\_CS0\_LP3\_CA0 | – | EBI | DO | EBI0 LPDDR4X chip select 0

LP3 command/address 0 | | D8 | EBI0\_LP4X\_CS1\_LP3\_CA2 | – | EBI | DO | EBI0 LPDDR4X chip select 1

LP3 command/address 2 | | D5 | EBI0\_LP4X\_DMI0\_LP3\_DQ21 | – | EBI | B | EBI0 LPDDR4X data mask 0

LP3 data bit 21 | | A11 | EBI0\_LP4X\_DMI1\_LP3\_DQ2 | – | EBI | B | EBI0 LPDDR4X data mask 1

LP3 data bit 2 | | A5 | EBI0\_LP4X\_DQ0\_LP3\_DQ20 | – | EBI | B | EBI0 LPDDR4X data bit 0

LP3 data bit 20 | | B13 | EBI0\_LP4X\_DQ10\_LP3\_DQ3 | – | EBI | B | EBI0 LPDDR4X data bit 10

LP3 data bit 3 | | B11 | EBI0\_LP4X\_DQ11\_LP3\_DQ1 | – | EBI | B | EBI0 LPDDR4X data bit 11

LP3 data bit 1 | | B12 | EBI0\_LP4X\_DQ12\_LP3\_DQ4 | – | EBI | B | EBI0 LPDDR4X data bit 12

LP3 data bit 4 | | A10 | EBI0\_LP4X\_DQ13\_LP3\_DQ0 | – | EBI | B | EBI0 LPDDR4X data bit 13

LP3 data bit 0 | | E11 | EBI0\_LP4X\_DQ14\_LP3\_DQ5 | – | EBI | B | EBI0 LPDDR4X data bit 14

LP3 data bit 5 | | D11 | EBI0\_LP4X\_DQ15\_LP3\_DQ6 | – | EBI | B | EBI0 LPDDR4X data bit 15

LP3 data bit 6 | | B5 | EBI0\_LP4X\_DQ1\_LP3\_DQ19 | – | EBI | B | EBI0 LPDDR4X data bit 1

LP3 data bit 19 | | B6 | EBI0\_LP4X\_DQ2\_LP3\_DQ23 | – | EBI | B | EBI0 LPDDR4X data bit 2

LP3 data bit 23 | | A7 | EBI0\_LP4X\_DQ3\_LP3\_DMI2 | – | EBI | B | EBI0 LPDDR4X data bit 3

LP3 data mask 2 | | D4 | EBI0\_LP4X\_DQ4\_LP3\_DQ18 | – | EBI | B | EBI0 LPDDR4X data bit 4

LP3 data bit 18 | | B7 | EBI0\_LP4X\_DQ5\_LP3\_DQ22 | – | EBI | B | EBI0 LPDDR4X data bit 5

LP3 data bit 22 | | E5 | EBI0\_LP4X\_DQ6\_LP3\_DQ16 | – | EBI | B | EBI0 LPDDR4X data bit 6

LP3 data bit 16 | | C4 | EBI0\_LP4X\_DQ7\_LP3\_DQ17 | – | EBI | B | EBI0 LPDDR4X data bit 7

LP3 data bit 17 | | E13 | EBI0\_LP4X\_DQ8\_LP3\_DQ7 | – | EBI | B | EBI0 LPDDR4X data bit 8

LP3 data bit 7 | | D13 | EBI0\_LP4X\_DQ9\_LP3\_DMI0 | – | EBI | B | EBI0 LPDDR4X data bit 9

LP3 data mask 0 | | D6 | EBI0\_LP4X\_DQS0\_C\_LP3\_DQS2\_C | – | EBI | B | EBI0 LPDDR4X differential data strobe 0 – minus

LP3 differential data strobe 2 – minus | | E6 | EBI0\_LP4X\_DQS0\_T\_LP3\_DQS2\_T | – | EBI | B | EBI0 LPDDR4X differential data strobe 0 – plus

LP3 differential data strobe 2 – plus | | E12 | EBI0\_LP4X\_DQS1\_C\_LP3\_DQS0\_C | – | EBI | B | EBI0 LPDDR4X differential data strobe 1 – minus

LP3 differential data strobe 0 – minus | | D12 | EBI0\_LP4X\_DQS1\_T\_LP3\_DQS0\_T | – | EBI | B | EBI0 LPDDR4X differential data strobe 1 – plus

LP3 differential data strobe 0 – plus | | E21 | EBI1\_LP4X\_CA0\_LP3\_CA5 | – | EBI | DO | EBI1 LPDDR4X command/address 0

LP3 command/address 5 | | B20 | EBI1\_LP4X\_CA1 | – | EBI | DO | EBI1 LPDDR4X command/address 1 | | A22 | EBI1\_LP4X\_CA2\_LP3\_CA8 | – | EBI | DO | EBI1 LPDDR4X command/address 2

LP3 command/address 8 | | B22 | EBI1\_LP4X\_CA3 | – | EBI | DO | EBI1 LPDDR4X command/address 3 | | B21 | EBI1\_LP4X\_CA4 | – | EBI | DO | EBI1 LPDDR4X command/address 4 | | D23 | EBI1\_LP4X\_CA5\_LP3\_CA9 | – | EBI | DO | EBI1 LPDDR4X command/address 5

LP3 command/address 9 | | D22 | EBI1\_LP4X\_CKE0 | – | EBI | DO | EBI1 LPDDR4X clock enable 0 | | D21 | EBI1\_LP4X\_CKE1\_LP3\_CKE1 | – | EBI | DO | EBI1 LPDDR4X clock enable 1

LP3 clock enable 1 | | D20 | EBI1\_LP4X\_CK\_C\_LP3\_CK\_C | – | EBI | DO | EBI1 LPDDR4X differential clock – minus

LP3 differential clock – minus | | E20 | EBI1\_LP4X\_CK\_T\_LP3\_CK\_T | – | EBI | DO | EBI1 LPDDR4X differential clock – plus

LP3 differential clock – plus | | E23 | EBI1\_LP4X\_CS0\_LP3\_CA7 | – | EBI | DO | EBI1 LPDDR4X chip select 0

LP3 command/address 7 | | E22 | EBI1\_LP4X\_CS1\_LP3\_CA6 | – | EBI | DO | EBI1 LPDDR4X chip select 1

LP3 command/address 6 | | E25 | EBI1\_LP4X\_DMI0\_LP3\_DQ26 | – | EBI | B | EBI1 LPDDR4X data mask 0

LP3 data bit 26 | | A19 | EBI1\_LP4X\_DMI1\_LP3\_DQ14 | – | EBI | B | EBI1 LPDDR4X data mask 1

LP3 data bit 14 | | A25 | EBI1\_LP4X\_DQ0\_LP3\_DQ27 | – | EBI | B | EBI1 LPDDR4X data bit 0

LP3 data bit 27 | | B17 | EBI1\_LP4X\_DQ10\_LP3\_DQ12 | – | EBI | B | EBI1 LPDDR4X data bit 10

LP3 data bit 12 | | B19 | EBI1\_LP4X\_DQ11\_LP3\_DQ13 | – | EBI | B | EBI1 LPDDR4X data bit 11

LP3 data bit 13 | | B18 | EBI1\_LP4X\_DQ12\_LP3\_DQ11 | – | EBI | B | EBI1 LPDDR4X data bit 12

LP3 data bit 11 | | A20 | EBI1\_LP4X\_DQ13\_LP3\_DQ15 | – | EBI | B | EBI1 LPDDR4X data bit 13

LP3 data bit 15 | | D19 | EBI1\_LP4X\_DQ14\_LP3\_DQ10 | – | EBI | B | EBI1 LPDDR4X data bit 14

LP3 data bit 10 | | E19 | EBI1\_LP4X\_DQ15\_LP3\_DQ9 | – | EBI | B | EBI1 LPDDR4X data bit 15

LP3 data bit 9 | | B25 | EBI1\_LP4X\_DQ1\_LP3\_DQ28 | – | EBI | B | EBI1 LPDDR4X data bit 1

LP3 data bit 28 | | B24 | EBI1\_LP4X\_DQ2\_LP3\_DQ24 | – | EBI | B | EBI1 LPDDR4X data bit 2

LP3 data bit 24 | | A23 | EBI1\_LP4X\_DQ3\_LP3\_DMI3 | – | EBI | B | EBI1 LPDDR4X data bit 3

LP3 data mask 3 | | A26 | EBI1\_LP4X\_DQ4\_LP3\_DQ29 | – | EBI | B | EBI1 LPDDR4X data bit 4

LP3 data bit 29 | | B23 | EBI1\_LP4X\_DQ5\_LP3\_DQ25 | – | EBI | B | EBI1 LPDDR4X data bit 5

LP3 data bit 25 | | D25 | EBI1\_LP4X\_DQ6\_LP3\_DQ31 | – | EBI | B | EBI1 LPDDR4X data bit 6

LP3 data bit 31 | | B26 | EBI1\_LP4X\_DQ7\_LP3\_DQ30 | – | EBI | B | EBI1 LPDDR4X data bit 7

LP3 data bit 30 | | D17 | EBI1\_LP4X\_DQ8\_LP3\_DQ8 | – | EBI | B | EBI1 LPDDR4X data bit 8

LP3 data bit 8 | | E17 | EBI1\_LP4X\_DQ9\_LP3\_DMI1 | – | EBI | B | EBI1 LPDDR4X data bit 9

LP3 data mask 1 | | E24 | EBI1\_LP4X\_DQS0\_C\_LP3\_DQS3\_C | – | EBI | B | EBI1 LPDDR4X differential data strobe 0 – minus

LP3 differential data strobe 3 – minus | | D24 | EBI1\_LP4X\_DQS0\_T\_LP3\_DQS3\_T | – | EBI | B | EBI1 LPDDR4X differential data strobe 0 – plus

LP3 differential data strobe 3 – plus | | D18 | EBI1\_LP4X\_DQS1\_C\_LP3\_DQS1\_C | – | EBI | B | EBI1 LPDDR4X differential data strobe 1 – minus

LP3 differential data strobe 1 – minus | | E18 | EBI1\_LP4X\_DQS1\_T\_LP3\_DQS1\_T | – | EBI | B | EBI1 LPDDR4X differential data strobe 1 – plus

LP3 differential data strobe 1 – plus | | AF25 | MODE\_0 | – | PX\_3 | DI | Mode control bit 0 – unconnected for native mode | | AE25 | MODE\_1 | – | PX\_3 | DI | Mode control bit 1 – unconnected for native mode | | AH19 | SPMI\_CLK | – | PX\_0 | B | Slave and PBUS interface for PMICs – clock | | AJ19 | SPMI\_DATA | – | PX\_0 | B | Slave and PBUS interface for PMICs – data | | AH27 | PS\_HOLD | – | PX\_3 | DO | Power–supply hold signal to PMIC | | T30 | QREFS\_CXO\_REXT | – | – | AI, AO | External resistor for on-die clocking | | AJ20 | RESIN\_N | – | PX\_3 | DI | Reset input | | AJ26 | RESOUT\_N | – | PX\_3 | DO | Reset output | | AH11 | SDC2\_CLK | – | PX\_2 | BH-NP: pdpukp | Secure digital controller 2 clock | | AJ10 | SDC2\_CMD | – | PX\_2 | BH-PD: nppukp | Secure digital controller 2 command | | AH12 | SDC2\_DATA0 | – | PX\_2 | BH-PD: nppukp | Secure digital controller 2 data bit 0 | | AJ11 | SDC2\_DATA1 | – | PX\_2 | BH-PD: nppukp | Secure digital controller 2 data bit 1 | | AH13 | SDC2\_DATA2 | – | PX\_2 | BH-PD: nppukp | Secure digital controller 2 data bit 2 | | AJ13 | SDC2\_DATA3 | – | PX\_2 | BH-PD: nppukp | Secure digital controller 2 data bit 3 | | AH26 | SLEEP\_CLK | – | PX\_3 | DI | Sleep clock | | AD28 | JTAG\_SRST\_N | – | PX\_3 | DI-PU | JTAG reset for debug | | AD30 | JTAG\_TCK | – | PX\_3 | DI-PU | JTAG clock input | | AE30 | JTAG\_TDI | – | PX\_3 | DI-PU: nppdkp | JTAG data input | | AD29 | JTAG\_TDO | – | PX\_3 | DO-Z | JTAG data output | | AE29 | JTAG\_TMS | – | PX\_3 | DI-PU: nppdkp | JTAG mode select input | | AC29 | JTAG\_TRST\_N | – | PX\_3 | DI-PD: nppukp | JTAG reset | | AC12 | BBRX\_CH0\_I | – | – | AI | Baseband receiver input, channel 0, inphase | | AF11 | BBRX\_CH1\_I | – | – | AI | Baseband receiver input, channel 1, in-phase | | AC8 | BBRX\_CH2\_I | – | – | AI | Baseband receiver input, channel 2, in-phase | | AE9 | BBRX\_CH3\_I | – | – | AI | Baseband receiver input, channel 3, in-phase | | AD12 | BBRX\_CH0\_Q | – | – | AI | Baseband receiver input, channel 0, quadrature | | AE11 | BBRX\_CH1\_Q | – | – | AI | Baseband receiver input, channel 1, quadrature | | AD8 | BBRX\_CH2\_Q | – | – | AI | Baseband receiver input, channel 2, quadrature | | AF9 | BBRX\_CH3\_Q | – | – | AI | Baseband receiver input, channel 3, quadrature | | AE13 | TX\_DAC\_IM | – | – | AO | TXDAC in-phase ‒ minus | | AF13 | TX\_DAC\_IP | – | – | AO | TXDAC in-phase ‒ plus | | AE14 | TX\_DAC\_QM | – | – | AO | TXDAC quadrature ‒ minus | | AF14 | TX\_DAC\_QP | – | – | AO | TXDAC quadrature ‒ plus | | K29 | USB0\_HS\_DM | – | – | AI, AO | USB 0 high-speed data ‒ minus | | K28 | USB0\_HS\_DP | – | – | AI, AO | USB 0 high-speed data ‒ plus | | K30 | USB0\_HS\_REXT | – | – | AI | USB 0 high-speed external resistor | | J30 | USB0\_SS\_REXT | – | – | AI | USB 0 super-speed external resistor | | F30 | USB0\_SS\_RX0\_M | – | – | AI | USB 0 super-speed receive 0 ‒ minus | | G30 | USB0\_SS\_RX0\_P | – | – | AI | USB 0 super-speed receive 0 ‒ plus | | G29 | USB0\_SS\_RX1\_M | – | – | AI | USB 0 super-speed receive 1 ‒ minus | | H29 | USB0\_SS\_RX1\_P | – | – | AI | USB 0 super-speed receive 1 ‒ plus | | H27 | USB0\_SS\_TX0\_M | – | – | AO | USB 0 super-speed transmit 0 ‒ minus | | G27 | USB0\_SS\_TX0\_P | – | – | AO | USB 0 super-speed transmit 0 ‒ plus | | J28 | USB0\_SS\_TX1\_M | – | – | AO | USB 0 super-speed transmit 1 ‒ minus | | J27 | USB0\_SS\_TX1\_P | – | – | AO | USB 0 super-speed transmit 1 ‒ plus | | AC14 | VREF\_TXDAC | – | – | AI, AO | Transmitter DAC voltage reference | | G2 | WLAN0\_DAC\_REXT | – | – | AI, AO | WLAN chain 0 external resistor | | K4 | WLAN\_WSI\_CLK | – | – | DO | WLAN baseband clock | | L4 | WLAN\_WSI\_DATA | – | – | B | WLAN baseband data | | L5 | WLAN\_COEX\_CLK | – | – | DO | WLAN coexistence module command clock | | M5 | WLAN\_COEX\_DATA | – | – | B | WLAN coexistence module command data | | A3 | WLAN\_RX\_I\_M | – | – | AI | WLAN receive in-phase ‒ minus | | A2 | WLAN\_RX\_I\_P | – | – | AI | WLAN receive in-phase ‒ plus | | B1 | WLAN\_RX\_Q\_M | – | – | AI | WLAN receive quadrature ‒ minus | | C1 | WLAN\_RX\_Q\_P | – | – | AI | WLAN receive quadrature ‒ plus | | H4 | WLAN\_TX\_I\_M | – | – | AO | WLAN transmits in-phase ‒ minus | | G4 | WLAN\_TX\_I\_P | – | – | AO | WLAN transmits in-phase ‒ plus | | G3 | WLAN\_TX\_Q\_M | – | – | AO | WLAN transmit quadrature ‒ minus | | H3 | WLAN\_TX\_Q\_P | – | – | AO | WLAN transmit quadrature ‒ plus | | K3 | WLAN\_XO\_CLK | – | – | AI | WLAN reference clock | | | | | | | | | Note:

GPIO pins can support multiple functions. To assign GPIOs to particular functions (such as the options listed in the preceding table), designers must identify all their application’s requirements and map each GPIO to its function – carefully avoiding conflicts in GPIO assignments. See [Table : Pin descriptions – general-purpose input/output ports](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__table_l4l_jdn_w3b) for a list of all supported functions for each GPIO.

Note:

Handset designers must examine each GPIOs external connection and programmed configuration, and take steps necessary to avoid excessive leakage current. Combinations of the following factors must be controlled properly:

GPIO configuration
- Input vs. output
- Pull-up or pull-down

External connections
- Unused inputs
- Connections to high-impedance (tri-state) outputs
- Connections to external devices that may not be attached

To help designers define their products’ GPIO assignments, Qualcomm Technologies,
Inc. (QTI) provides an Excel spreadsheet that lists all QRB2210 GPIOs (in numeric order), pad numbers, pad voltages,
pull states, and available configurations.

Note:

Click [QRB2210 Pin Assignment and GPIO Configuration
Spreadsheet (80-30843-1A)](https://docs.qualcomm.com/bundle/80-30843-1A/resource/80-30843-1A.xlsm) to download the document from the
Qualcomm website. | | :--- | | Pad number | Pad name | Wake-up function | Configurable functions | Pad characteristics | Pad characteristics | Functional description | | --- | --- | --- | --- | --- | --- | --- | | Pad number | Pad name | Wake-up function | Configurable functions | Voltage | Type | Functional description | | T27 | GPIO\_0 | Y | SPI\_MISO

UART\_CTS

I2C\_SDA

I3C\_SDA

QDSS\_GPIO\_TRACEDATA\_LOCB[8] | PX\_3 | B-PD:nppukp

DI

DI

B

B

DO | Configurable I/O

QUP 0 SE0, lane 0: SPI\_MISO

QUP 0 SE0, lane 0: UART\_CTS

QUP 0 SE0, lane 0: I2C\_SDA

QUP 0 SE0, lane 0: I3C\_SDA

QDSS trace data bit 8 B | | T28 | GPIO\_1 | N | SPI\_MOSI

UART\_RFR

I2C\_SCL

I3C\_SCL

QDSS\_GPIO\_TRACEDATA\_LOCB[9] | PX\_3 | B-PD:nppukp

DO

DO

DO

DO

DO | Configurable I/O

QUP 0 SE0, lane 1: SPI\_MOSI

QUP 0 SE0, lane 1: UART\_RFR

QUP 0 SE0, lane 1: I2C\_SCL

QUP 0 SE0, lane 1: I3C\_SCL

QDSS trace data bit 9 B | | U27 | GPIO\_2 | N | SPI\_SCLK

UART\_TX

QDSS\_GPIO\_TRACEDATA\_LOCB[10] | PX\_3 | B-PD:nppukp

DO

DO

DO | Configurable I/O

QUP 0 SE0, lane 2: SPI\_SCLK

QUP 0 SE0, lane 2: UART\_TX

QDSS trace data bit 10 B | | V27 | GPIO\_3 | Y | SPI\_CS\_N\_0

UART\_RX

QDSS\_GPIO\_TRACEDATA\_LOCB[11] | PX\_3 | B-PD:nppukp

DO

DI

DO | Configurable I/O

QUP 0 SE0, lane 3:SPI\_CS\_N

QUP 0 SE0, lane 3: UART\_RX

QDSS trace data bit 11 B | | AB30 | GPIO\_4 | Y | SPI\_MISO

UART\_CTS

I2C\_SDA | PX\_3 | B-PD:nppukp

DI

DI

B | Configurable I/O

QUP 0 SE1, lane 0: SPI\_MISO

QUP 0 SE1, lane 0: UART\_CTS

QUP 0 SE1, lane 0: I2C\_SDA | | AB29 | GPIO\_5 | N | SPI\_MOSI

UART\_RFR

I2C\_SCL | PX\_3 | B-PD:nppukp

DO

DO

DO | Configurable I/O

QUP 0 SE1, lane 1: SPI\_MOSI

QUP 0 SE1, lane 1: UART\_RFR

QUP 0 SE1, lane 1: I2C\_SCL | | Y28 | GPIO\_6 | Y | SPI\_MISO

UART\_CTS

I2C\_SDA | PX\_3 | B-PD:nppukp

DI

DI

B | Configurable I/O

QUP 0 SE2, lane 0: SPI\_MISO

QUP 0 SE2, lane 0: UART\_CTS

QUP 0 SE2, lane 0: I2C\_SDA | | AA28 | GPIO\_7 | N | SPI\_MOSI

UART\_RFR

I2C\_SCL | PX\_3 | B-PD:nppukp

DO

DO

DO | Configurable I/O

QUP 0 SE2, lane 1:SPI\_MOSI

QUP 0 SE2, lane 1:UART\_RFR

QUP 0 SE2, lane 1:I2C\_SCL | | E1 | GPIO\_8 | Y | SPI\_MISO

UART\_CTS

I2C\_SDA

QDSS\_GPIO\_TRACECLK\_LOCA | PX\_3 | B-PD:nppukp

DI

DI

B

DO | Configurable I/O

QUP 0 SE3, lane 0: SPI\_MISO

QUP 0 SE3, lane 0: UART\_CTS

QUP 0 SE3, lane 0: I2C\_SDA

QDSS trace clock A | | F1 | GPIO\_9 | N | SPI\_MOSI

UART\_RFR

I2C\_SCL

QDSS\_GPIO\_TRACECTL\_LOCA | PX\_3 | B-PD:nppukp

DO

DO

DO

DO | Configurable I/O

QUP 0 SE3, lane 1: SPI\_MOSI

QUP 0 SE3, lane1:UART\_RFR

QUP 0 SE3, lane1: I2C\_SCL

QDSS trace control A | | G1 | GPIO\_10 | N | SPI\_SCLK

UART\_TX

QDSS\_GPIO\_TRACEDATA\_LOCA[0] | PX\_3 | B-PD:nppukp

DO

DO

DO | Configurable I/O

QUP 0 SE3, lane 2: SPI\_SCLK

QUP 0 SE3, lane 2: UART\_TX

QDSS trace data bit 0 A | | H1 | GPIO\_11 | Y | SPI\_CS\_N

UART\_RX

QDSS\_GPIO\_TRACEDATA\_LOCA[1] | PX\_3 | B-PD:nppukp

DO

DI

DO | Configurable I/O

QUP 0 SE3, lane 3: SPI\_CS\_N

QUP 0 SE3, lane 3: UART\_RX

QDSS trace data bit 1 A | | AF29 | GPIO\_12 | N | UART\_TX

SPI\_SCLK | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

QUP 0 SE4, lane 2: UART\_TX

QUP 0 SE4, lane 2: SPI\_SCLK | | AG30 | GPIO\_13 | Y | UART\_RX

SPI\_CS\_N | PX\_3 | B-PD:nppukp

DI

DO | Configurable I/O

QUP 0 SE4, lane 3: UART\_RX

QUP 0 SE4, lane 3: SPI\_CS\_N | | W30 | GPIO\_14 | Y | SPI\_MISO

UART\_CTS

I2C\_SDA

QDSS\_GPIO\_TRACEDATA\_LOCB[4] | PX\_3 | B-PD:nppukp

DI

DI

B

DO | Configurable I/O

QUP 0 SE5, lane 0: SPI\_MISO

QUP 0 SE5, lane 0: UART\_CTS

QUP 0 SE5, lane 0: I2C\_SDA

QDSS trace data bit 4B | | Y29 | GPIO\_15 | N | SPI\_MOSI

UART\_RFR

I2C\_SCL

QDSS\_GPIO\_TRACEDATA\_LOCB[5] | PX\_3 | B-PD:nppukp

DO

DO

DO

DO | Configurable I/O

QUP 0 SE5, lane 1: SPI\_MOSI

QUP 0 SE5, lane 1: UART\_RFR

QUP 0 SE5, lane1: I2C\_SCL

QDSS trace data bit 5 B | | AA29 | GPIO\_16 | N | UART\_TX

SPI\_SCLK

QDSS\_GPIO\_TRACEDATA\_LOCB[6] | PX\_3 | B-PD:nppukp

DO

DO

DO | Configurable I/O

QUP 0 SE5, lane 2: UART\_TX

QUP 0 SE5, lane 2 :SPI\_SCLK

QDSS trace data bit 6 B | | AA30 | GPIO\_17 | Y | UART\_RX

SPI\_CS\_N

QDSS\_GPIO\_TRACEDATA\_LOCB[7] | PX\_3 | B-PD:nppukp

DI

DO

DO | Configurable I/O

QUP 0 SE5, lane 3: UART\_RX

QUP 0 SE5, lane 3 :SPI\_CS\_N

QDSS trace data bit 7 B | | M1 | GPIO\_18 | Y | QDSS\_GPIO\_TRACEDATA\_LOCA[2]

PWM[0] | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

QDSS trace data bit 2 A

PWM output 0 | | AE3 | GPIO\_19 | Y | QDSS\_GPIO\_TRACEDATA\_LOCA[3] | PX\_3 | B-PD:nppukp

DO | Configurable I/O

QDSS trace data bit 3 A | | L2 | GPIO\_20 | N | CAM\_MCLK0

QDSS\_GPIO\_TRACEDATA\_LOCA[4] | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

Camera master clock 0

QDSS trace data bit 4 A | | M2 | GPIO\_21 | N | CAM\_MCLK1

QDSS\_GPIO\_TRACEDATA\_LOCA[5] | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

Camera master clock 1

QDSS trace data bit 5 A | | AD4 | GPIO\_22 | N | CCI\_I2C\_SDA0

QDSS\_GPIO\_TRACEDATA\_LOCA[6] | PX\_3 | B-PD:nppukp

B

DO | Configurable I/O

Dedicated camera control interface I^2^C 0 serial data

QDSS trace data bit 6 A | | AD5 | GPIO\_23 | N | CCI\_I2C\_SCL0

QDSS\_GPIO\_TRACEDATA\_LOCA[7] | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

Dedicated camera control interface I^2^C 0 clock

QDSS trace data bit 7 A | | AC5 | GPIO\_24 | Y | CCI\_TIMER1

GCC\_GP1\_CLK\_MIRA

QDSS\_GPIO\_TRACEDATA\_LOCA[8] | PX\_3 | B-PD:nppukp

DO

DO

DO | Camera control interface timer 1

Global general–purpose clock 1

QDSS trace data bit 8 A | | AC2 | GPIO\_25 | Y | CCI\_ASYNC\_IN0

CCI\_TIMER0

QDSS\_GPIO\_TRACEDATA\_LOCA[9] | PX\_3 | B-PD:nppukp

DI

DO

DO | Configurable I/O

Camera control interface async 0

Camera control interface timer 0

QDSS trace data bit 9 A | | AC3 | GPIO\_26 | N | QDSS\_GPIO\_TRACEDATA\_LOCA[10] | PX\_3 | B-PD:nppukp

DO | Configurable I/O

QDSS trace data bit 10 A | | M3 | GPIO\_27 | Y | CAM\_MCLK2

QDSS\_CTI\_TRIG0\_IN\_MIRB | PX\_3 | B-PD:nppukp

DO

DI | Configurable I/O

Camera master clock 2

QDSS trigger input 0 B | | M4 | GPIO\_28 | Y | CAM\_MCLK3

CCI\_TIMER2

QDSS\_CTI\_TRIG0\_OUT\_MIRB

PWM[1] | PX\_3 | B-PD:nppukp

DO

DO

DO

DO | Configurable I/O

Camera master clock 3

Camera control interface timer 2

QDSS trigger output 0 B

PWM output 1 | | AC4 | GPIO\_29 | N | CCI\_I2C\_SDA1 | PX\_3 | B-PD:nppukp

B | Configurable I/O

Dedicated camera control interface I^2^C 1 serial data | | AB2 | GPIO\_30 | N | CCI\_I2C\_SCL1 | PX\_3 | B-PD:nppukp

DO | Configurable I/O

Dedicated camera control interface I^2^C 1 clock | | AB5 | GPIO\_31 | Y | GP\_PDM\_MIRB[0] | PX\_3 | B-PD:nppukp

DO | Configurable I/O

General-purpose PDM\_Mirror\_B 0 | | AB4 | GPIO\_32 | Y | CCI\_TIMER3

GP\_PDM\_MIRB[1] | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

Camera control interface timer 3

General-purpose PDM\_Mirror\_B 1 | | AA4 | GPIO\_33 | Y | GP\_PDM\_MIRB[2] | PX\_3 | B-PD:nppukp

DO | Configurable I/O

General-purpose PDM\_Mirror\_B 2 | | AA5 | GPIO\_34 | Y | – | PX\_3 | B-PD:nppukp | Configurable I/O | | AE5 | GPIO\_35 | Y | – | PX\_3 | B-PD:nppukp | Configurable I/O | | AD2 | GPIO\_36 | Y | – | PX\_3 | B-PD:nppukp | Configurable I/O | | AH1 | GPIO\_37 | N | | PX\_3 | B-PD:nppukp | Configurable I/O | | AH2 | GPIO\_38 | N | | PX\_3 | B-PD:nppukp | Configurable I/O | | AG2 | GPIO\_39 | Y | | PX\_3 | B-PD:nppukp | Configurable I/O | | AF3 | GPIO\_40 | N | | PX\_3 | B-PD:nppukp | Configurable I/O | | AF4 | GPIO\_41 | N | | PX\_3 | B-PD:nppukp | Configurable I/O | | AG4 | GPIO\_42 | N | NAV\_GPIO\_1\_MIRA | PX\_3 | B-PD:nppukp

B | Configurable I/O

Generic I/O | | AF2 | GPIO\_43 | N | BOOT\_CONFIG[8] | PX\_3 | B-PD:nppukp

DI | Configurable I/O

Boot configuration control bit 8 | | AF5 | GPIO\_44 | N | BOOT\_CONFIG[9] | PX\_3 | B-PD:nppukp

DI | Configurable I/O

Boot configuration control bit 9 | | AE1 | GPIO\_45 | N | BOOT\_CONFIG[10] | PX\_3 | B-PD:nppukp

DI | Configurable I/O

Boot configuration control bit 10 | | AG1 | GPIO\_46 | Y | BOOT\_CONFIG[11] | PX\_3 | B-PD:nppukp

DI | Configurable I/O

Boot configuration control bit 11 | | AE2 | GPIO\_47 | N | NAV\_GPIO\_0\_MIRA

QDSS\_GPIO\_TRACEDATA\_LOCA[14] | PX\_3 | B-PD:nppukp

B

DO | Configurable I/O

Generic I/O

QDSS trace data bit 14 A | | AH9 | GPIO\_48 | N | QDSS\_GPIO\_TRACEDATA\_LOCA[15]

BOOT\_CONFIG[0] | PX\_3 | B-PD:nppukp

DO

DI | Configurable I/O

QDSS trace data bit 15 A

Boot configuration control bit 0 | | AJ8 | GPIO\_49 | N | PA\_INDICATOR\_OR | PX\_3 | B-PD:nppukp

DO | Configurable I/O

PA transmit indicator | | AJ7 | GPIO\_50 | N | BOOT\_CONFIG[1] | PX\_3 | B-PD:nppukp

DI | Configurable I/O

Boot configuration control bit 1 | | AH8 | GPIO\_51 | N | BOOT\_CONFIG[2]

PWM[2] | PX\_3 | B-PD:nppukp

DI

DO | Configurable I/O

Boot configuration control bit 2

PWM output 2 | | AH7 | GPIO\_52 | N | NAV\_GPIO\_2\_MIRA | PX\_3 | B-PD:nppukp

B | Configurable I/O

Generic I/O | | AH6 | GPIO\_53 | N | BOOT\_CONFIG[3] | PX\_3 | B-PD:nppukp

DI | Configurable I/O

Boot configuration control bit 3 | | AG6 | GPIO\_54 | N | – | PX\_3 | B-PD:nppukp | Configurable I/O | | AF6 | GPIO\_55 | N | BOOT\_CONFIG[4] | PX\_3 | B-PD:nppukp

DI | Configurable I/O

Boot configuration control bit 4 | | AE6 | GPIO\_56 | N | – | PX\_3 | B-PD:nppukp | Configurable I/O | | AJ5 | GPIO\_57 | N | BOOT\_CONFIG[5] | PX\_3 | B-PD:nppukp

DI | Configurable I/O

Boot configuration control bit 5 | | AH5 | GPIO\_58 | N | | PX\_3 | B-PD:nppukp | Configurable I/O | | AJ4 | GPIO\_59 | N | SSBI\_WGR\_TX

BOOT\_CONFIG[6] | PX\_3 | B-PD:nppukp

DO

DI | Configurable I/O

Single serial bus interface transmiter

Boot configuration control bit 6 | | AH4 | GPIO\_60 | N | SSBI\_WGR\_RX | PX\_3 | B-PD:nppukp

DI | Configurable I/O

Single serial bus interface receiver | | AH3 | GPIO\_61 | N | BOOT\_CONFIG[7] | PX\_3 | B-PD:nppukp

DI | Configurable I/O

Boot configuration control bit 7 | | AJ2 | GPIO\_62 | Y | – | PX\_3 | B-PD:nppukp | Configurable I/O | | AD1 | GPIO\_63 | Y | – | PX\_3 | B-PD:nppukp | Configurable I/O | | AE4 | GPIO\_64 | Y | – | PX\_3 | B-PD:nppukp | Configurable I/O | | W28 | GPIO\_69 | Y | SPI\_SCLK

UART\_TX

GCC\_GP2\_CLK\_MIRA

QDSS\_GPIO\_TRACEDATA\_LOCB[12] | PX\_3 | B–PU:nppukp

DO

DO

DO

DO | Configurable I/O

QUP 0 SE1, lane 2 :SPI\_SCLK

QUP 0 SE1, lane 2: UART\_TX

Global general purpose clock 2 A

QDSS trace data bit 12 B | | W29 | GPIO\_70 | Y | SPI\_CS\_N

UART\_RX

GCC\_GP3\_CLK\_MIRA

QDSS\_GPIO\_TRACEDATA\_LOCB[13] | PX\_3 | B-PD:nppukp

DO

DI

DO

DO | Configurable I/O

QUP 0 SE1, lane 3 :SPI\_CS\_N

QUP 0 SE1, lane 3: UART\_RX

Global general purpose clock 3 A

QDSS trace data bit 13 B | | AA27 | GPIO\_71 | N | SPI\_SCLK

UART\_TX | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

QUP 0 SE2, lane 2 :SPI\_SCLK

QUP 0 SE 2, lane 2: UART\_TX | | AH18 | GPIO\_72 | Y | QDSS\_CTI\_TRIG1\_IN\_MIRB

PWM[3] | PX\_6 | B-PD:nppukp

DI

DO | Configurable I/O

QDSS trigger input 1 B

PWM output 3 | | AH17 | GPIO\_73 | N | QDSS\_CTI\_TRIG1\_OUT\_MIRB | PX\_6 | B-PD:nppukp

DO | Configurable I/O

QDSS trigger output 1 B | | AJ17 | GPIO\_74 | N | PWM[4] | PX\_6 | B-PD:nppukp

DO | Configurable I/O

PWM output 4 | | AJ16 | GPIO\_75 | Y | PWM[5] | PX\_3 | B-PD:nppukp

DO | Configurable I/O

PWM output 5 | | AH16 | GPIO\_76 | N | – | PX\_5 | B-PD:nppukp | Configurable I/O | | AH15 | GPIO\_77 | N | – | PX\_5 | B-PD:nppukp | Configurable I/O | | AJ14 | GPIO\_78 | N | – | PX\_5 | B-PD:nppukp | Configurable I/O | | AH14 | GPIO\_79 | Y | – | PX\_3 | B-PD:nppukp | Configurable I/O | | AB28 | GPIO\_80 | Y | SPI\_CS\_N

UART\_RX | PX\_3 | B-PD:nppukp

DO

DI | Configurable I/O

QUP 0 SE2, lane 3 :SPI\_CS\_N

QUP 0 SE2, lane 3: UART\_RX | | AG29 | GPIO\_81 | Y | MDP\_VSYNC\_OUT\_0

MDP\_VSYNC\_OUT\_1

MDP\_VSYNC\_P | PX\_3 | B-PD:nppukp

DO

DO

DI | Configurable I/O

MDP vertical sync – output 0

MDP vertical sync – output 1

MDP vertical sync – primary | | V28 | GPIO\_82 | N | SPI\_CS\_N\_1

PWM[6] | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

QUP 0 SE0, lane 4 :SPI\_CS\_N\_1

PWM output 6 | | V30 | GPIO\_86 | Y | SPI\_CS\_N\_2

GCC\_GP1\_CLK\_MIRB | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

QUP 0 SE0, lane 5 :SPI\_CS\_N\_2

Global general purpose clock 1 B | | J1 | GPIO\_87 | Y | QDSS\_GPIO\_TRACEDATA\_LOCA[11] | PX\_3 | B-PD:nppukp

DO | Configurable I/O

QDSS trace data bit 11 A | | AH10 | GPIO\_88 | Y | – | PX\_3 | B-PD:nppukp | Configurable I/O | | AJ29 | GPIO\_89 | Y | USB\_PHY\_PS

PWM[7] | PX\_3 | B-PD:nppukp

DI

DO | Configurable I/O

USB PHY port select

PWM output 7 | | K1 | GPIO\_90 | N | MSS\_LTE\_COXM\_TXD

QDSS\_GPIO\_TRACEDATA\_LOCA[12] | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

UART Tx for LTE coex

QDSS trace data bit 12 A | | K2 | GPIO\_91 | Y | MSS\_LTE\_COXM\_RXD

QDSS\_GPIO\_TRACEDATA\_LOCA[13] | PX\_3 | B-PD:nppukp

DI

DO | Configurable I/O

UART Rx for LTE coex

QDSS trace data bit 13 A | | AC27 | GPIO\_94 | Y | GP\_MN

QDSS\_GPIO\_TRACEDATA\_LOCB[14]

FORCED\_USB\_BOOT\_POL\_SEL | PX\_3 | B-PD:nppukp

DO

DO

DI | Configurable I/O

General-purpose M/N:D counter output

QDSS trace data bit 14 B

Forced USB boot polarity select | | AD27 | GPIO\_95 | Y | NAV\_GPIO\_0\_MIRC

GP\_PDM\_MIRA[0]

QDSS\_GPIO\_TRACEDATA\_LOCB[15]

FORCED\_USB\_BOOT | PX\_3 | B-PD:nppukp

B

DO

DO

DI | Configurable I/O

Generic I/O

General-purpose PDM\_Mirror\_A 0

QDSS trace data bit 15 B

Forced USB boot | | AH30 | GPIO\_96 | Y | SPI\_MISO

UART\_CTS

I2C\_SDA

NAV\_GPIO\_1\_MIRC

MDP\_VSYNC\_E

GP\_PDM\_MIRA[1]

SD\_WRITE\_PROTECT

QDSS\_CTI\_TRIG0\_IN\_MIRA

QDSS\_CTI\_TRIG1\_OUT\_MIRA | PX\_3 | B-PD:nppukp

DI

DI

B

B

DI

DO

DO

DI

DO | Configurable I/O

QUP 0 SE4, lane 0: SPI\_MISO

QUP 0 SE4, lane 0: UART\_CTS

QUP 0 SE4, lane 0: I2C\_SDA

Generic I/O

MDP vertical sync – external

General-purpose PDM\_Mirror\_A 1

SD card write protect

QDSS trigger input 0 A

QDSS trigger output 1 A | | AH29 | GPIO\_97 | Y | SPI\_MOSI

UART\_RFR

I2C\_SCL

NAV\_GPIO\_2\_MIRC

MDP\_VSYNC\_S

GP\_PDM\_MIRA[2]

QDSS\_CTI\_TRIG0\_OUT\_MIRA

QDSS\_CTI\_TRIG1\_IN\_MIRA | PX\_3 | B-PD:nppukp

DO

DO

DO

B

DI

DO

DO

DI | Configurable I/O

QUP 0 SE4, lane 1: SPI\_MOSI

QUP 0 SE4, lane 1: UART\_RFR

QUP 0 SE4, lane1: I2C\_SCL

Generic I/O

MDP vertical sync – secondary

General-purpose PDM\_Mirror\_A 2

QDSS trigger output 0 A

QDSS trigger input 1 A | | AG23 | GPIO\_98 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | N | LPI\_GPIO\_6:LPI\_DMIC1\_CLK

LPI\_GPIO\_6:LPI\_MI2S0\_CLK | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

LPI\_Digital MIC 1 Clock

LPI\_MI2S 0 Clock | | AH23 | GPIO\_99 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | Y | LPI\_GPIO\_7:LPI\_DMIC1\_DATA

LPI\_GPIO\_7:LPI\_MI2S0\_WS | PX\_3 | B-PD:nppukp

DI

DO | Configurable I/O

LPI\_Digital MIC 1 data

LPI\_MI2S 0 Word Select | | AJ23 | GPIO\_100 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | N | LPI\_GPIO\_8:LPI\_DMIC2\_CLK

LPI\_GPIO\_8:LPI\_MI2S0\_DATA0 | PX\_3 | B-PD:nppukp

DO

B | Configurable I/O

LPI\_Digital MIC 2 Clock

LPI\_MI2S 0 Data 0 | | AE22 | GPIO\_101 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | Y | LPI\_GPIO\_9:LPI\_DMIC2\_DATA

LPI\_GPIO\_9:LPI\_MI2S0\_DATA1

LPI\_GPIO\_9:MI2S\_MCLK1\_B | PX\_3 | B-PD:nppukp

DI

B

DO | Configurable I/O

LPI\_Digital MIC 2 Data

LPI\_MI2S 0 Data 1

Master Clock 1 B | | AF22 | GPIO\_102 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | Y | LPI\_GPIO\_10:LPI\_MI2S1\_CLK

LPI\_GPIO\_10:LPI\_DMIC4\_CLK | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

LPI\_MI2S 1 Clock

LPI\_Digital MIC 4 Clock | | AH22 | GPIO\_103 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | Y | LPI\_GPIO\_11:LPI\_MI2S1\_WS

LPI\_GPIO\_11:LPI\_DMIC4\_DATA | PX\_3 | B-PD:nppukp

DO

DI | Configurable I/O

LPI\_MI2S 1 Word Select

LPI\_Digital MIC 4 Data | | AJ22 | GPIO\_104 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | Y | QDSS\_GPIO\_TRACEDATA\_LOCB[1]

LPI\_GPIO\_12:LPI\_DMIC3\_CLK

LPI\_GPIO\_12:LPI\_MI2S1\_DATA0

PWM[8] | PX\_3 | B-PD:nppukp

DO

DO

B

DO | Configurable I/O

QDSS trace data bit 1 B

LPI\_Digital MIC 3 Clock

LPI\_MI2S 1 Data 0

PWM output 8 | | AE21 | GPIO\_105 | Y | QDSS\_GPIO\_TRACECLK\_LOCB

LPI\_GPIO\_13:LPI\_DMIC3\_DATA

LPI\_GPIO\_13:LPI\_MI2S1\_DATA1

LPI\_GPIO\_13:MI2S\_MCLK0\_A | PX\_3 | B-PD:nppukp

DO

DI

B

DO | Configurable I/O

QDSS trace clock B

LPI\_Digital MIC 3 Data

LPI\_MI2S 1 Data 1

MI2S Master Clock 0 A | | AF21 | GPIO\_106 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | Y | NAV\_GPIO\_0\_MIRB

GCC\_GP3\_CLK\_MIRB

QDSS\_GPIO\_TRACECTL\_LOCB

LPI\_GPIO\_16:LPI\_MI2S2\_DATA0 | PX\_3 | B-PD:nppukp

B

DO

DO

B | Configurable I/O

Generic I/O

Global general purpose clock 3 B

QDSS trace control B

LPI\_MI2S 2 Data 0 | | AG21 | GPIO\_107 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | Y | NAV\_GPIO\_1\_MIRB

GCC\_GP2\_CLK\_MIRB

QDSS\_GPIO\_TRACEDATA\_LOCB[0]

LPI\_GPIO\_17:LPI\_MI2S2\_DATA1

LPI\_GPIO\_17:MI2S\_MCLK1\_C | PX\_3 | B-PD:nppukp

B

DO

DO

B

DO | Configurable I/O

Generic I/O

Global general purpose clock 2 B

QDSS trace data bit 0 B

LPI\_MI2S 2 Data 1

MI2S Master Clock 1\_C | | AH21 | GPIO\_108 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | N | NAV\_GPIO\_2\_MIRB

LPI\_GPIO\_18:MI2S\_MCLK1\_A

LPI\_GPIO\_18:SWR\_TX\_DATA2 | PX\_3 | B-PD:nppukp

B

DO

B | Configurable I/O

Generic I/O

MI2S Master Clock 1\_A

SoundWire transmit data 2 | | AJ25 | GPIO\_109 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | Y | QDSS\_GPIO\_TRACEDATA\_LOCB[2]

LPI\_GPIO\_19:I2C\_SDA

LPI\_GPIO\_19:I3C\_SDA | PX\_3 | B-PD:nppukp

DO

B

B | Configurable I/O

QDSS trace data bit 2 B

LPI\_ QUP 0 SE0, lane 0: I2C\_SDA

LPI\_ QUP 0 SE0, lane 0: I3C\_SDA | | AH25 | GPIO\_110 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | N | QDSS\_GPIO\_TRACEDATA\_LOCB[3]

LPI\_GPIO\_20:I2C\_SCL

LPI\_GPIO\_20:I3C\_SCL | PX\_3 | B-PD:nppukp

DO

DO

DO | Configurable I/O

QDSS trace data bit 3 B

LPI\_ QUP 0 SE0, lane 1: I2C\_SCL

LPI\_ QUP 0 SE0, lane 1: I3C\_SCL | | AG25 | GPIO\_111 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | N | LPI\_GPIO\_23:UART\_CTS

LPI\_GPIO\_23:I2C\_SDA

LPI\_GPIO\_23:UART\_TX | PX\_3 | B-PD:nppukp

DI

B

DO | Configurable I/O

LPI\_ QUP 0 SE5, lane 0 :UART\_CTS

LPI\_QUP 0 SE5, lane 0: I2C\_SDA

LPI\_ QUP 0 SE5, lane 2:UART\_TX | | AH24 | GPIO\_112 [^1^](https://docs.qualcomm.com/doc/80-30843-1/topic/Pin_definitions.html#prn1594290580851__fn_mgn_pmc_rkb) | Y | LPI\_GPIO\_24:UART\_RFR

LPI\_GPIO\_24:I2C\_SCL

LPI\_GPIO\_24:UART\_RX | PX\_3 | B-PD:nppukp

DO

DO

DI | Configurable I/O

LPI\_QUP 0 SE5, lane 1 :UART\_RFR

LPI\_ QUP 0 SE5, lane1: I2C\_SCL

LPI\_ QUP 0 SE5, lane 3:UART\_RX | | D30 | GPIO\_113 | N | – | PX\_7 | B-PD:nppukp | Configurable I/O | | E29 | GPIO\_114 | N | – | PX\_7 | B-PD:nppukp | Configurable I/O | | D29 | GPIO\_116 | N | SDC1\_DATA7 | PX\_7 | B-PD:nppukp

B | Configurable I/O

Secure digital controller 1 data bit 7 | | D28 | GPIO\_117 | N | SDC1\_DATA6 | PX\_7 | B-PD:nppukp

B | Configurable I/O

Secure digital controller 1 data bit 6 | | C30 | GPIO\_118 | N | SDC1\_DATA5 | PX\_7 | B-PD:nppukp

B | Configurable I/O

Secure digital controller 1 data bit 5 | | C29 | GPIO\_119 | N | SDC1\_DATA4 | PX\_7 | B-PD:nppukp

B | Configurable I/O

Secure digital controller 1 data bit 4 | | C28 | GPIO\_120 | Y | SDC1\_DATA3 | PX\_7 | B-PD:nppukp

B | Configurable I/O

Secure digital controller 1 data bit 3 | | B30 | GPIO\_121 | N | SDC1\_DATA2 | PX\_7 | B-PD:nppukp

B | Configurable I/O

Secure digital controller 1 data bit 2 | | B29 | GPIO\_122 | Y | SDC1\_DATA1 | PX\_7 | B-PD:nppukp

B | Configurable I/O

Secure digital controller 1 data bit 1 | | B28 | GPIO\_123 | N | SDC1\_DATA0 | PX\_7 | B-PD:nppukp

B | Configurable I/O

Secure digital controller 1 data bit 0 | | A28 | GPIO\_124 | N | SDC1\_RCLK | PX\_7 | B-PD:nppukp

DI | Configurable I/O

Secure digital controller 1 return clock | | C27 | GPIO\_125 | N | SDC1\_CMD | PX\_7 | B-PD:nppukp

B | Configurable I/O

Secure digital controller 1 command | | A29 | GPIO\_126 | N | SDC1\_CLK | PX\_7 | B-PD:nppukp

DO | Configurable I/O

Secure digital controller 1 clock | | AF20 | LPI\_GPIO\_0 | N | SWR\_TX\_CLK

LPI\_MI2S3\_CLK | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

SoundWire transmit clock

LPI\_MI2S 3 clock | | AE20 | LPI\_GPIO\_1 | Y | SWR\_TX\_DATA0

LPI\_MI2S3\_WS | PX\_3 | B-PD:nppukp

B

DO | Configurable I/O

SoundWire transmit data 0

LPI\_MI2S 3 Word Select | | AH20 | LPI\_GPIO\_2 | N | SWR\_TX\_DATA1

LPI\_MI2S3\_DATA0 | PX\_3 | B-PD:nppukp

B

B | Configurable I/O

SoundWire transmit data 1

LPI\_MI2S 3 Data 0 | | AF19 | LPI\_GPIO\_3 | N | SWR\_RX\_CLK

LPI\_MI2S3\_DATA1 | PX\_3 | B-PD:nppukp

DO

B | Configurable I/O

SoundWire receive data 0

LPI\_MI2S 3 Data 1 | | AE19 | LPI\_GPIO\_4 | Y | SWR\_RX\_DATA0

LPI\_MI2S3\_DATA2 | PX\_3 | B-PD:nppukp

B

B | Configurable I/O

SoundWire receive data 0

LPI\_MI2S 3 Data 2 | | AF18 | LPI\_GPIO\_5 | N | SWR\_RX\_DATA1

MI2S\_MCLK0\_B

LPI\_MI2S 3 | PX\_3 | B-PD:nppukp

B

DO

B | Configurable I/O

SoundWire receive data 1

MI2S Master Clock 0 B

LPI\_MI2S 3 Data 3 | | AG19 | LPI\_GPIO\_14 | N | LPI\_MI2S2\_CLK

BTFM\_SLIMBUS\_CLK | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

LPI\_MI2S 2 Clock

Bluetooth/FM SLIMbus clock | | AG18 | LPI\_GPIO\_15 | Y | LPI\_MI2S2\_WS

BTFM\_SLIMBUS\_DATA | PX\_3 | B-PD:nppukp

DO

B | Configurable I/O

LPI\_MI2S 2 Word Select

Bluetooth/FM SLIMbus data | | AE23 | LPI\_GPIO\_21 | Y | SPI\_MISO

UART\_CTS

I2C\_SDA

I3C\_SDA | PX\_3 | B-PD:nppukp

DI

DI

B

B | Configurable I/O

LPI\_QUP 0 SE1, lane 0: SPI\_MISO

LPI\_QUP 0 SE1, lane 0: UART\_CTS

LPI\_QUP 0 SE1, lane 0: I2C\_SDA

LPI\_QUP 0 SE1, lane 0: I3C\_SDA | | AF23 | LPI\_GPIO\_22 | N | SPI\_MOSI

UART\_RFR

I2C\_SCL

I3C\_SCL | PX\_3 | B-PD:nppukp

DO

DO

DO

DO | Configurable I/O

LPI\_QUP 0 SE1, lane 1: SPI\_MOSI

LPI\_QUP 0 SE1, lane 1: UART\_RFR

LPI\_QUP 0 SE1, lane 1: I2C\_SCL

LPI\_QUP 0 SE1, lane 1: I3C\_SDA | | AF24 | LPI\_GPIO\_25 | N | SPI\_SCLK

UART\_TX

UART\_TX | PX\_3 | B-PD:nppukp

DO

DO | Configurable I/O

LPI\_QUP 0 SE1, lane 2: SPI\_SCLK

LPI\_QUP 0 SE1, lane 2: UART\_TX

LPI\_QUP 0 SE6, lane 2: UART\_TX | | AE24 | LPI\_GPIO\_26 | Y | SPI\_CS\_N

UART\_RX

UART\_RX | PX\_3 | B-PD:nppukp

DO

DI

DI | Configurable I/O

LPI\_QUP 0 SE1, lane 3: SPI\_CS\_N

LPI\_QUP 0 SE1, lane 3: UART\_RX

LPI\_QUP 0 SE6, lane 3: UART\_RX | | | | | | | | | ^1^ LPI\_GPIO functions are selected when EGPIO\_ENABLE is low. | Pad number | Pad name | Functional description | Functional description | Functional description | Functional description | | --- | --- | --- | --- | --- | --- | | AD10, AD11, AD13 | VDD\_A2 | Power for analog circuits – high voltage | Power for analog circuits – high voltage | Power for analog circuits – high voltage | Power for analog circuits – high voltage | | AB10, AB11 | VDD\_A1 | Power for analog circuits – low voltage | Power for analog circuits – low voltage | Power for analog circuits – low voltage | Power for analog circuits – low voltage | | U22 | VDD\_A\_APC\_PLL\_0P9 | Power for the APC PLL circuits | Power for the APC PLL circuits | Power for the APC PLL circuits | Power for the APC PLL circuits | | Y16 | VDD\_A\_AUDIO\_PLL\_1P8 | Power for the audio PLL circuits | Power for the audio PLL circuits | Power for the audio PLL circuits | Power for the audio PLL circuits | | P15 | VDD\_A\_CAMSS\_PLL\_1P8 | Power for the camera PLL circuits | Power for the camera PLL circuits | Power for the camera PLL circuits | Power for the camera PLL circuits | | H15 | VDD\_A\_EBI\_CC\_0P9 | Power for the EBI clock circuits | Power for the EBI clock circuits | Power for the EBI clock circuits | Power for the EBI clock circuits | | R7 | VDD\_A\_CSI\_0\_1P2 | Power for the CSI0 1.2 V circuits | Power for the CSI0 1.2 V circuits | Power for the CSI0 1.2 V circuits | Power for the CSI0 1.2 V circuits | | T7 | VDD\_A\_CSI\_1\_1P2 | Power for the CSI1 1.2 V circuits | Power for the CSI1 1.2 V circuits | Power for the CSI1 1.2 V circuits | Power for the CSI1 1.2 V circuits | | P23 | VDD\_A\_DSI\_1P2 | Power for the DSI 1.2 V circuits | Power for the DSI 1.2 V circuits | Power for the DSI 1.2 V circuits | Power for the DSI 1.2 V circuits | | P24 | VDD\_A\_DSI\_0P9 | Power for the DSI 0.9 V circuits | Power for the DSI 0.9 V circuits | Power for the DSI 0.9 V circuits | Power for the DSI 0.9 V circuits | | N24 | VDD\_A\_DSI\_PLL\_1P2 | Power for the DSI PLL circuits | Power for the DSI PLL circuits | Power for the DSI PLL circuits | Power for the DSI PLL circuits | | H9, H11, H13 | VDD\_A\_EBI\_0\_0P9 | Power for EBI0 circuits | Power for EBI0 circuits | Power for EBI0 circuits | Power for EBI0 circuits | | H18, H20, H22 | VDD\_A\_EBI\_1\_0P9 | Power for EBI1 circuits | Power for EBI1 circuits | Power for EBI1 circuits | Power for EBI1 circuits | | G15 | VDD\_A\_EBI\_PLL\_0P9 | Power for EBI PLL circuits | Power for EBI PLL circuits | Power for EBI PLL circuits | Power for EBI PLL circuits | | W14 | VDD\_A\_MODEM\_PLL\_1P8 | Power for modem PLL circuits | Power for modem PLL circuits | Power for modem PLL circuits | Power for modem PLL circuits | | F15 | VDD\_A\_PLL\_HV\_CC\_EBI\_1P2 | Power for EBI PLL high-voltage circuits | Power for EBI PLL high-voltage circuits | Power for EBI PLL high-voltage circuits | Power for EBI PLL high-voltage circuits | | R25 | VDD\_A\_QREFS\_0P9 | Reference voltage for QREF 0.9 V circuits | Reference voltage for QREF 0.9 V circuits | Reference voltage for QREF 0.9 V circuits | Reference voltage for QREF 0.9 V circuits | | M24 | VDD\_A\_USB\_HS\_1P8 | Power for the USB HS 1.8 V circuits | Power for the USB HS 1.8 V circuits | Power for the USB HS 1.8 V circuits | Power for the USB HS 1.8 V circuits | | M23 | VDD\_A\_USB\_HS\_3P1 | Power for the USB HS 3.1 V circuits | Power for the USB HS 3.1 V circuits | Power for the USB HS 3.1 V circuits | Power for the USB HS 3.1 V circuits | | K7 | VDD\_A\_WLAN\_ADCDAC0\_1P3 | Power for the WLAN ADC and DAC 0 | Power for the WLAN ADC and DAC 0 | Power for the WLAN ADC and DAC 0 | Power for the WLAN ADC and DAC 0 | | J7 | VDD\_A\_WLAN\_ADCDAC1\_1P3 | Power for the WLAN ADC and DAC 1 | Power for the WLAN ADC and DAC 1 | Power for the WLAN ADC and DAC 1 | Power for the WLAN ADC and DAC 1 | | K8 | VDD\_A\_WLAN\_PLL\_1P8 | Power for the WLAN PLL circuits | Power for the WLAN PLL circuits | Power for the WLAN PLL circuits | Power for the WLAN PLL circuits | | K24 | VDD\_A\_USB\_SS\_0P9 | Power for USB SS 0.9 V circuits | Power for USB SS 0.9 V circuits | Power for USB SS 0.9 V circuits | Power for USB SS 0.9 V circuits | | K11, K12, K13, K14, K15, K16, K17, K18, K22, M19, N9, N11, N13, N15, N17, R9, R10, R11, R12, R13, R15, R16, R17, T10, T19, Y8, Y9, Y10, Y11, Y12, Y13 | VDD\_CX | Power for the digital core circuits | Power for the digital core circuits | Power for the digital core circuits | Power for the digital core circuits | | F12 | VDD\_IO\_EBI\_0\_CK | Power for the EBI0 I/O clock circuits | Power for the EBI0 I/O clock circuits | Power for the EBI0 I/O clock circuits | Power for the EBI0 I/O clock circuits | | F19 | VDD\_IO\_EBI\_1\_CK | Power for the EBI1 I/O clock circuits | Power for the EBI1 I/O clock circuits | Power for the EBI1 I/O clock circuits | Power for the EBI1 I/O clock circuits | | G9, G10, G13, G14, G17, G18, G21, G22 | VDD\_IO\_EBI | Power for the EBI I/O circuits | Power for the EBI I/O circuits | Power for the EBI I/O circuits | Power for the EBI I/O circuits | | L25 | VDD\_A\_USB\_SS\_1P8 | Power for USB SS 1.8 V circuits | Power for USB SS 1.8 V circuits | Power for USB SS 1.8 V circuits | Power for USB SS 1.8 V circuits | | AB20, AB21, L10, L11, L12, L13, L14, L15, L16, L17, L18, L19, L20, N20, R19, T23, V9, V10, V11, V12, V13, V14 | VDD\_MX | Power for on-chip memory | Power for on-chip memory | Power for on-chip memory | Power for on-chip memory | | Y15 | VDD\_MX\_TXDAC | Power for TXDAC memory circuits | Power for TXDAC memory circuits | Power for TXDAC memory circuits | Power for TXDAC memory circuits | | AC18 | VDD\_PX0 | Power for the pad group 0 | Power for the pad group 0 | Power for the pad group 0 | Power for the pad group 0 | | T25 | VDD\_PX11 | Power for the CXO pads | Power for the CXO pads | Power for the CXO pads | Power for the CXO pads | | F10, F13, F18, F21, F24 | VDD\_PX1 | Power for the EBI I/O circuits | Power for the EBI I/O circuits | Power for the EBI I/O circuits | Power for the EBI I/O circuits | | AE17 | VDD\_PX2 | Power for the pad group 2 – SDC2 pads | Power for the pad group 2 – SDC2 pads | Power for the pad group 2 – SDC2 pads | Power for the pad group 2 – SDC2 pads | | AA7, AC23, AF17, G26, M6, T26, F11, F20, N19 | VDD\_PX3 | Power for the pad group 3 – most I/O pads | Power for the pad group 3 – most I/O pads | Power for the pad group 3 – most I/O pads | Power for the pad group 3 – most I/O pads | | AC17 | VDD\_PX5 | Power for the pad group 5 | Power for the pad group 5 | Power for the pad group 5 | Power for the pad group 5 | | AD18 | VDD\_PX6 | Power for the pad group 6 | Power for the pad group 6 | Power for the pad group 6 | Power for the pad group 6 | | G24 | VDD\_PX7 | Power for the pad group 7 – eMMC pads | Power for the pad group 7 – eMMC pads | Power for the pad group 7 – eMMC pads | Power for the pad group 7 – eMMC pads | | AD17 | VDD\_SDCREF\_1P25 | Reference voltage for SDC | Reference voltage for SDC | Reference voltage for SDC | Reference voltage for SDC | | AD19 | VDD\_REF\_1P25 | Reference voltage | Reference voltage | Reference voltage | Reference voltage | | AA21, AA22, AA23, AA24, AA25, AA26, R20, R22, U19, U20, U21, U23, W18, W19, W20, W21, Y18, Y19, Y20, Y21, Y22, Y23, Y24 | VDD\_APC | Power for the application processor | Power for the application processor | Power for the application processor | Power for the application processor | | W16, W17 | VDD\_CX\_LPI | Power for LPI digital core circuits | Power for LPI digital core circuits | Power for LPI digital core circuits | Power for LPI digital core circuits | | Y17 | VDD\_MX\_LPI | Power for LPI memory circuits | Power for LPI memory circuits | Power for LPI memory circuits | Power for LPI memory circuits | | P19 | VDD\_QFPROM | Power for programming the QFPROM | Power for programming the QFPROM | Power for programming the QFPROM | Power for programming the QFPROM | | M25 | VDD\_USB\_HS\_0P9 | Power for the USB HS 0.9 V circuits | Power for the USB HS 0.9 V circuits | Power for the USB HS 0.9 V circuits | Power for the USB HS 0.9 V circuits | | J9, J10, J11 | VDD\_CX\_WLAN | Power for the WLAN core circuits | Power for the WLAN core circuits | Power for the WLAN core circuits | Power for the WLAN core circuits | | A4, A13, A14, A16, A17, A27, AA6, AA8, AA9, AA11, AA12, AA14, AA16, AA17, AA18,
AA19, AA20, AB3, AB7, AB8, AB9, AB12, AB13, AB14, AB22, AB23, AB24, AB25, AB26, AC6,
AC7, AC9, AC10, AC11, AC13, AC15, AC16, AC20, AC21, AC22, AC24, AC28, AD3, AD6, AD7,
AD9, AD14, AD15, AE7, AE8, AE10, AE12, AE15, AE18, AF7, AF8, AF10, AF12, AF15, AF16,
AG3, AG5, AG7, AG8, AG9, AG10, AG11, AG12, AG13, AG14, AG15, AG16, AG17, AG20, AG22,
AG24, AG26, AG28, B2, B3, B4, B14, B16, B27, C2, C3, C5, C6, C7, C8, C9, C10, C11,
C12, C13, C14, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, D1, D2, D3, D14, D16,
D27, E2, E3, E4, E14, E15, E16, E26, E27, F2, F3, F4, F5, F6, F7, F8, F9, F22, F23,
F25, F26, F27, F29, G5, G6, G8, G11, G12, G19, G20, G23, G28, H2, H5, H6, H7, H24,
H25, H26, H28, J2, J3, J4, J5, J6, J12, J13, J14, J15, J16, J17, J18, J19, J20, J22,
J25, J26, J29, K5, k6, K10, K19, K20, K25, K26, K27, L3, L6, L7, L8, L24, L27, L28,
L29, M7, M8, M10, M11, M13, M15, M16, M17, M18, M22, M26, N5, N7, N8, N21, N25, N26,
P4, P5, P6, P7, P8, P10, P11, P12, P13, P14, P17, P18, P25, P26, P28, R5, R6, R23,
R27, R29, T5, T6, T9, T11, T13, T15, T17, T20, T22, T29, U4, U5, U6, U10, U11, U13,
U15, U17, U26, U28, V5, V6, V7, V8, V15, V16, V17, V18, V19, V21, V23, V24, V26, V29,
W5, W6, W9, W10, W11, W13, W22, W23, W24, W26, W27, Y4, Y5, Y6, Y26, Y27 | GND | Ground | Ground | Ground | Ground | | A1, A30, AJ1, AJ30, AC26, AC25, F17, F28, AB27, L26, W2, Y2, AB1, W3, Y3, AA2, W4, AA1, AA3, W1, C16, B15, C15, D15, A15, G16, F16, G25, J24, U7, AE28, AF28, AH28, AJ28, AE27, AF27, AG27, AE26, AF26 | DNC | Do not connect; connected internally, do not connect externally. | Do not connect; connected internally, do not connect externally. | Do not connect; connected internally, do not connect externally. | Do not connect; connected internally, do not connect externally. | Last Published: Oct 08, 2025 [Previous Topic Introduction](https://docs.qualcomm.com/bundle/publicresource/80-30843-1/topics/Introduction.md) [Next Topic Electrical specifications](https://docs.qualcomm.com/bundle/publicresource/80-30843-1/topics/Electrical_specifications.md)