# DIP switches
Source: [https://docs.qualcomm.com/doc/80-70014-251/topic/rb3_dip_switches.html](https://docs.qualcomm.com/doc/80-70014-251/topic/rb3_dip_switches.html)
This section provides details and shows the location of the DIP switches on the
mainboard, interposer, and vision mezzanine.
DIP switches are on the front, underside of the mainboard and interposer board. They are
near the front, on the top side of the vision mezzanine board. A tool similar to a
dental pick is provided to help access switches that might be difficult to reach. The
following sections provide details on the DIP switches.
## Mainboard DIP switches
DIP\_SW\_0 contains
six switches and is present on the bottom side of the mainboard. DIP\_SW\_1 is
inactive. Use the pick included in the kit to help access switches that might be
difficult to reach. The following table lists the switches and their
functionalities.
Table : DIP switch selection
| DIP\_SW\_0 | Name | Details | Default |
| :---: | :---: | :---: | :---: |
| 1 | Mic switch | ON: on-board DMIC
OFF: off-board DMIC (LS2 connector) | ON |
| 2 | Debug UART | ON: enable serial log (debug UART)
OFF: disable serial log (off-board UART) | ON |
| 3 | N/A | – | – |
| 4 | HDMI switch | ON: HDMI disabled
OFF: HDMI enabled | OFF |
| 5 | Sensor IMU toggle | ON: on-board IMU disabled
OFF: on-board IMU enabled | OFF |
| 6 | IMU external clock | ON: external clock to IMU
OFF: no external clock to IMU | OFF |
The following flowcharts show how the DIP switch settings on the mainboard
control the routing of signals from/to connectors and components. Refer to [Figure : 1. Mainboard and interposer block diagram](https://docs.qualcomm.com/doc/80-70014-251/topic/rb3_hardware_overview.html#hardware_overview__fig_twb_t3t_51c) as
necessary to see the signals, switches, and connectors in context.
Figure : Circuits controlled by DIP switches on the mainboard
## Interposer DIP switches
Figure : DIP switches on the interposer
The interposer board has three boot configuration DIP switches. The following
table lists the interposer DIP switches along with their functionalities:
| DIP\_SW\_2 | Name | Details | Default |
| --- | --- | --- | --- |
| 1 | BOOT\_CONFIG\_1 [GPIO\_120] | Selects external boot devices | OFF |
| 2 | BOOT\_CONFIG\_2 [GPIO\_122] | Selects external boot devices | OFF |
| 3 | BOOT\_CONFIG\_3 [GPIO\_124] | Selects external boot devices | OFF |
| 4 | BOOT\_CONFIG\_0 [GPIO\_118] | ON: disables watchdog
OFF: enables watchdog | OFF |
| | | | |
| | | | |
| DIP\_SW\_3 | Name | Details | Default |
| :---: | :---: | :---: | :---: |
| 1 | DIP\_CSI3\_SW | OFF: CSI3 input from Vision mezzanine CAM3 (IMX577)
ON: CSI3 input from Vision mezzanine CAM5 (GMSL) | OFF |
| 2 | PCIE\_DIP\_SW | ON: QPS 1 Lane PCIe goes to mainboard 500 pin (HS expansion
PCIE2)
OFF: QPS 1 Lane PCIe goes to PCIE2USB (uPD) | OFF |
| DIP\_SW\_4 | Name | Details | Default |
| :---: | :---: | :---: | :---: |
| 1 | CSI1\_DIP\_SW | ON: CSI1 input from interposer CPHY CAM1
OFF: CSI1 input from Vision mezzanine CAM1 | OFF |
| 2 | CSI2\_DIP\_SW | ON: CSI2 input from interposer CPHY CAM2
OFF: CSI2 input from Vision mezzanine CAM2 | OFF |
| 3 | QSPI\_CAN\_DIP\_SW | ON: not supported
OFF: SPI to CAN interface on mainboard | OFF |
| 4 | QSPI\_GPIO\_DIP\_SW | ON: not supported
OFF: SPI to CAN interface on mainboard | OFF |
The following flowcharts show how the DIP switch settings on the interposer
control the routing of signals from/to connectors and components. Refer to the [Figure : 1. Mainboard and interposer block diagram](https://docs.qualcomm.com/doc/80-70014-251/topic/rb3_hardware_overview.html#hardware_overview__fig_twb_t3t_51c) as
necessary to see the signals, switches, and connectors in context.
Figure : Circuits controlled by DIP switches on the interposer
Figure : Vision mezzanine DIP switches
Table : Vision mezzanine DIP switches
| **DIP1** | **Name** | **Details** | **Default** |
| :---: | :---: | :---: | :---: |
| 1 | SENSOR\_SPI\_PASSTHRU | ON: Snapdragon sensor core (SSC) sensor SPI routed to
IMU\_SPI\_SELECT switch
OFF: IMU sensor SPI passthrough | OFF |
| 2 | APPS\_SPI\_PASSTHRU | ON: Application processor SPI routed to IMU\_SPI\_SELECT switch
OFF: passthrough | OFF |
| 3 | CAM2\_APPS\_SPI\_PASSTHRU | ON: SPI to CAM2 connector
OFF: passthrough | OFF |
| 4 | PRESS\_SENS\_DISCONNECT | ON: on-board
OFF: disconnected | ON |
| 5 | MAG\_SENSOR\_DISCONNECT | ON: on-board
OFF: disconnected | ON |
| 6 | UART0\_PASSTHRU | ON: on-board
OFF: passthrough | OFF |
| DIP2 | Name | Details | Default |
| :---: | :---: | :---: | :---: |
| 1 | DIP\_CSI0A\_B\_SWITCH | ON: CSI0 all 4 lanes to CAM0A
OFF: CSI0 2 lanes to CAM0A, 1 lane to CAM0B | OFF |
| 2 | MIC\_DISCONNECT | ON: DMIC 2/3 connects to on-board mics
OFF: DMIC 2/3 passthrough | ON |
| 3 | IMU\_SPI\_SELECT | ON: connects IMU to APPS SPI – only if DIP 1:2 is ON
OFF: connects IMU to SSC SPI – only if DIP 1:1 is ON | OFF |
| 4 | IMU\_INT\_1\_2\_SELECT\_LOGIC1 | ON: IMU INT1 to GYRO\_INT, IMU INT2 to
PMIC clock
OFF: IMU INT1 and 2 connected to IMU sensor switch | OFF |
| 5 | IMU\_INT\_1\_2\_SELECT\_LOGIC2 | ON: IMU INT1 to ACCEL\_INT, IMU INT2 to GYRO\_INT
OFF: IMU INT 1 and 2 disconnected | OFF |
| 6 | PRESSURE\_COMPASS\_SELECT | ON: Pressure/Compass connected to APPS I2C
OFF: Pressure/Compass connected to sensor core I2C | OFF |
The following flowcharts show how the DIP switch settings on the Vision mezzanine
control the routing of signals from/to connectors and components. Refer to the [Figure : 1. Mainboard and interposer block diagram](https://docs.qualcomm.com/doc/80-70014-251/topic/rb3_hardware_overview.html#hardware_overview__fig_twb_t3t_51c) as
necessary to see the signals, switches, and connectors in context.
Figure : Circuits controlled by DIP switches on the Vision mezzanine
**Parent Topic:** [References](https://docs.qualcomm.com/doc/80-70014-251/topic/references.html)
Last Published: Jan 28, 2026
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