# TLMM Source: [https://docs.qualcomm.com/doc/80-70014-4/topic/tlmm-developer-touchpoints.html](https://docs.qualcomm.com/doc/80-70014-4/topic/tlmm-developer-touchpoints.html) The hardware controls the multiplexing of general-purpose input/output (GPIO) and alternate functions through the top-level mode multiplexer (TLMM). You can configure the GPIOs during the boot process using the DT properties for TLMM. You can edit the following file paths to update the properties on the Linux host machine: - /boot\_images/boot/Settings/Soc/<Chipset>/Core/SocInfra/TLMM/<Chipset>-pinctrl.dtsi - /boot\_images/boot/Settings/Soc/<Chipset>/Core/SocInfra/TLMM/tlmm.dtsi The table lists the properties that describe how to configure the default value of a GPIO based on the requirements of the Qualcomm reference device. Table : TLMM DT properties | Property name | Property description | Data type | Possible values/value range | Device behavior | | --- | --- | --- | --- | --- | | QCOM, sleep-config | GPIO configuration settings as defined in
<Chipset>-pinctrl.dtsi. The configurations
are applied on device boot up. | UINT32 | Pin direction:


Pin pull configuration:
Pin output: |






Example:



(GPIO_INPUT | GPIO_PULL_DOWN | GPIO_OUT_LOW | GPIO_PRG_NO) /* PIN 10 */Copy to clipboard | | Compatible | Compatible property contains a read-only string that points to the
compatible chipset. | String | – | Example:

compatible =
"qcom,<chipset>-pinctrl" | | reg | Represents the read only GPIO base address and size. | UINT32 | reg = <0xf100000 0x100000>;Copy to clipboard | In a `reg` property tuple, the first index contains
the base address, and the second index contains the size. Example:
| | ngpios | Number of read only GPIO pins in chipset. | UINT32 | – | Example:



ngpios = <175>;Copy to clipboard | | width | Each GPIO pin has its own set of read only control registers. Width
indicates pin to pin register offset. | – | – | Example:



width = <0x1000>;Copy to clipboard | | id | Hardware instance of read only GPIO pad ID. | UINT32 | – | Example:



id = <0x0>;Copy to clipboard | | version | GPIO read only driver version. Driver 1.0 refers as 0x1. | UINT32 | – | Example:



version = <0x1>;Copy to clipboard | | gpio-controller | Identifier to represent the read only connected device as a GPIO
device. | String | – | – | | phandles for pin configurations | Mux configuration that is used to configure the alternative
functionality of GPIOs. For more information, see [Pin descriptions](https://docs.qualcomm.com/bundle/80-23889-1/resource/80-23889-1_REV_AM_QCS6490_QCS5430_Data_Sheet.pdf). | – | `sdc4_data_1: sdc4_data_1 { mux = <13 3>; };`
| On bootup, the GPIO configures to alternate functionality of
GPIO.
Example:


sdc4_data_1: sdc4_data_1 { mux = <13 3>; };Copy to clipboard


In this example, 13 refers to the GPIO number and 3 indicates the
alternate function selection. | **Parent Topic:** [Interfaces](https://docs.qualcomm.com/doc/80-70014-4/topic/interfaces.html) Last Published: Feb 02, 2026 [Previous Topic PMIC](https://docs.qualcomm.com/bundle/publicresource/80-70014-4/topics/pmic-developer-touchpoints.md) [Next Topic Buses](https://docs.qualcomm.com/bundle/publicresource/80-70014-4/topics/buses.md)