VBackground-1

# Architecture Source: [https://docs.qualcomm.com/doc/80-70015-26/topic/architecture.html](https://docs.qualcomm.com/doc/80-70015-26/topic/architecture.html) The following figure shows the architecture and its components involved in communicating data over Ethernet on RB3 Gen 2 development kit. Figure : Ethernet architecture on RB3 Gen 2 development kit The components of Ethernet architecture are described as follows. | Component | Description | | --- | --- | | Application processor subsystem (APSS) |

Runs on a Linux-based operating system.

| | Ethernet driver |

A software driver in the Linux kernel.

Provides data connectivity over a wired Ethernet interface.

| | PHY driver |

A low-level driver dedicated to manage the Ethernet physical
layer.

Implements a software state machine required to handle the
lifecycle of PHY, from initialization to link
establishment.

Interacts with an underlying management data input/output (MDIO)
to access the PHY register and perform operations such as
detecting alive and/or linked PHYs.

| | Ethernet hardware (RB3 Gen 2 development kit) |

Both QEP and AQR PHYs are validated on RB3 Gen 2 development
kit.
- QEP PHY for 2.5 GbE is available by default on SGMII
  interface. It is enabled and verified on a 1 x QEP8121
  IX connector.
- AQR PHY for 10 GbE is optional and may not be available
  on the development kit. If available, it is verified on
  a 1 x AQR113C IX connector.
- For more information, see RB3 Gen 2 main board
  and interposer block diagram.
Note: The outputs shown in the
subsequent sections are based on the verification of both
QEP8121 and AQR113C PHYs.

To bring up hardware configurations other than the configuration
provided by Qualcomm, see Bring up alternate hardware enablement.

For more information on Universal Serial Bus (USB) Ethernet
connection, see Ethernet.

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