# Bring up Source: [https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html](https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html) ### About this task Note: To bring up hardware configurations other than the configuration provided by Qualcomm, see [Bring up alternate hardware enablement](https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html#attach_other_ethernet_phy_components). Figure : Ethernet bringup workflow VBackground-1 Solid.1000 Page-1 Sheet.4 Assign MAC address Assign MAC address Sheet.7 Sheet.20 Configure MTU size Configure MTU size Sheet.1000 Assign IP address Assign IP address Sheet.1001 The QPS615 MAC driver and kernel configuration are enabled by default in the source code. To bring up Ethernet functionality, do the following: ### Procedure 1. RB3 Gen 2 development kit comes with a [preconfigured MAC address](https://docs.qualcomm.com/doc/80-70015-26/topic/get_started.html#configure_and_store_mac_address). Skip this step if you choose to use the same MAC address. Alternatively, to modify the preconfigured MAC address on the device, perform the following steps: 1. Bring down the interface: ifconfig downCopy to clipboard For example: ifconfig enP1p5s0f0 downCopy to clipboard 2. Assign the MAC address: ifconfig hw ether Copy to clipboard For example: ifconfig enP15sof0 hw ether XX:XX:XX:YY:YY:YYCopy to clipboard 3. Bring up the interface: ifconfig upCopy to clipboard For example: ifconfig enP1p5s0f0 169.254.227.235 upCopy to clipboard A sample output is as follows: ifconfig enP1p5s0f0 Link encap:Ethernet HWaddr XX:XX:XX:YY:YY:YY inet addr:169.254.227.235 Bcast:169.254.255.255 Mask:255.255.0.0 inet6 addr: fe80::533c:8ed6:557:3860/64 Scope:Link UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:19 errors:0 dropped:0 overruns:0 frame:0 TX packets:36 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:3416 (3.3 KiB) TX bytes:5559 (5.4 KiB) Interrupt:249Copy to clipboard Note: This MAC address is valid only for the current boot cycle. On rebooting the device, the MAC address is updated with the address from persistent storage as described in [Verify preconfigured MAC address](https://docs.qualcomm.com/doc/80-70015-26/topic/get_started.html#configure_and_store_mac_address). 2. When the device is connected to a public network, the DHCP server connected to the network assigns the IP address automatically. No specific configuration is required. Alternatively, to assign a static IP address, run the following command: ifconfig Copy to clipboard For example: ifconfig enP1p5s0f0 169.254.227.235Copy to clipboard A sample output is as follows: ifconfig enP1p5s0f0 Link encap:Ethernet HWaddr XX:XX:XX:YY:YY:YY inet addr:169.254.227.235 Bcast:169.254.255.255 Mask:255.255.0.0 inet6 addr: fe80::533c:8ed6:557:3860/64 Scope:Link UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:19 errors:0 dropped:0 overruns:0 frame:0 TX packets:36 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:3416 (3.3 KiB) TX bytes:5559 (5.4 KiB) Interrupt:249 Copy to clipboard Note: This IP address is valid only for the current boot cycle. On rebooting the device, the IP address is not retained. 3. To configure the MTU size for the data packets over the Ethernet interface, run the following command: ifconfig mtu upCopy to clipboard For example: ifconfig enP1p5s0f0 mtu 1500 upCopy to clipboard A sample output is as follows: ifconfig enP1p5s0f0 Link encap:Ethernet HWaddr XX:XX:XX:YY:YY:YY inet addr:169.254.227.235 Bcast:169.254.255.255 Mask:255.255.0.0 inet6 addr: fe80::533c:8ed6:557:3860/64 Scope:Link UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:19 errors:0 dropped:0 overruns:0 frame:0 TX packets:36 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:3416 (3.3 KiB) TX bytes:5559 (5.4 KiB) Interrupt:249 Copy to clipboard ## Bring up alternate hardware enablement Source: [https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html](https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html) You can attach MAC/PHY components other than the hardware configuration provided by Qualcomm and bring them up. Note: You must obtain the MAC/PHY driver and firmware from the respective vendor. Qualcomm is not responsible for these configuration changes. To replace QPS615 with other PCIe based MAC/PHY, see [PCIe software support for QPS615 switch](https://docs.qualcomm.com/bundle/publicresource/topics/80-70015-8/pcie.html#sub$pcie-software-support-feature-for-qps615). ### Retain QPS615 PCIe and replace QEP8121/AQR113C Source: [https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html](https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html) ### About this task To retain QPS615 PCIe and replace QEP8121/AQR113C with other PHY components, do the following: ### Procedure 1. Based on the attached PHY recommendations, update all the parameters in the arch/arm64/boot/dts/qcom/qcs6490-addons-rb3gen2.dtsi file. 2. Compile the software. A sample code for QEP PHY is as follows: qep_vreg: qep_vreg { compatible = "regulator-fixed"; regulator-name = "qep_vreg"; gpio = <&pm7325_gpios 8 0>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; enable-active-high;}; qps615_eth1,qps615_eth1@pcie1_rp { reg = <0x100 0x0 0x0 0x0 0x0>; pinctrl-names = "default"; pinctrl-0 = <&napa_intn_wol_sig>; qcom,phy-rst-gpio = <1>; interrupts-extended = <&tlmm 101 IRQ_TYPE_EDGE_FALLING>; interrupt-names = "wol_irq"; phy-supply = <&qep_vreg>; qcom,phy-rst-delay-us = <20000>; #address-cells = <1>; #size-cells = <1>; Copy to clipboard After flashing the modified software, the QPS615 driver scans the physical devices connected to it and matches the device tree information in the qcs6490-addons-rb3gen2.dtsi file. Warning: A PHY may fail to load due to mismatch between the configuration in the .dtsi file and actual recommendations for the PHY. In such cases, you must update the configuration in the .dtsi file accordingly. ## AQR PHY enablement Source: [https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html](https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html) Though AQR PHY for 10 GbE is optional, it is validated on reference RB3 Gen 2 development kit. You must flash the PHY firmware to the hardware only once; however, you must load and install the PHY driver on every new build. Qualcomm verified the following AQR PHY firmware on RB3 Gen 2 development kit: - Marvell firmware: AQR-G4\_v5.6.1-QR\_Marvell\_NoSwap\_XFI\_ID44874\_VER1836.cld - Marvell proprietary flash burn tool is recommended for flashing Marvell AQR113 PHY. - Contact Marvell Technology, Inc. to obtain the AQR PHY firmware. ### Install AQR PHY driver Source: [https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html](https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html) ### About this task To load and install the PHY driver, do the following: ### Procedure 1. Download the PHY driver source code from [Aquantia GitHub](https://github.com/Aquantia/linux-aqr-phy/tree/aqr_mainline/drivers/net/phy/aquantia). 2. Replace the default upstream driver with the driver downloaded from GitHub in the drivers/net/phy/aquantia directory. 3. To compile Aquantia PHY as kernel module, set `CONFIG_AQUANTIA_PHY=m` in the arch/arm64/configs/qcom\_defconfig file. 4. Verify whether the following object is available in the drivers/net/phy/Makefile file: obj-$(CONFIG_AQUANTIA_PHY) += aquantia/Copy to clipboard Add the object if not available, for example: obj-$(CONFIG_AT803X_PHY) += at803x.o obj-$(CONFIG_AX88796B_PHY) += ax88796b.o obj-$(CONFIG_AQUANTIA_PHY) += aquantia/ obj-$(CONFIG_AT803X_PHY) += at803x.o obj-$(CONFIG_AX88796B_PHY) += ax88796b.oCopy to clipboard 5. Verify whether the following path for source code is available in the drivers/net/phy/Kconfig file: source "drivers/net/phy/aquantia/Kconfig"Copy to clipboard Add the path if not available, for example: config ADIN1100_PHY tristate "Analog Devices Industrial Ethernet T1L PHYs" help Adds support for the Analog Devices Industrial T1L Ethernet PHYs. Currently supports the: - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY source "drivers/net/phy/aquantia/Kconfig" config AX88796B_PHY tristate "Asix PHYs" help Currently supports the Asix Electronics PHY found in the X-Surf 100 AX88796B package.Copy to clipboard 6. Verify whether the following code is available in the drivers/net/phy/aquantia/Kconfig file: # SPDX-License-Identifier: GPL-2.0-only config AQUANTIA_PHY tristate "Aquantia PHYs" select CRC_ITU_T help Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405Copy to clipboard 7. Compile the kernel. The aquantia.ko kernel object is generated. ### Detect the PHY Source: [https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html](https://docs.qualcomm.com/doc/80-70015-26/topic/bring_up.html) ### About this task To detect the PHY, do the following: ### Procedure 1. Update the AQR PHY parameters in the arch/arm64/boot/dts/qcom/qcs6490-addons-rb3gen2.dtsi file. 2. Compile the software. A sample code for AQR PHY is as follows: aqr_vreg: aqr_vreg { compatible = "regulator-fixed"; regulator-name = "aqr_vreg"; gpio = <&pm7250b_gpios 4 0>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; enable-active-high;}; qps615_eth0,qps615_eth0@pcie1_rp { reg = <0x0 0x0 0x0 0x0 0x0>; pinctrl-names = "default"; pinctrl-0 = <&aqr_intn_wol_sig>; qcom,phy-rst-gpio = <0>; interrupts-extended = <&tlmm 141 IRQ_TYPE_EDGE_FALLING>; interrupt-names = "wol_irq"; phy-supply = <&aqr_vreg>; qcom,phy-rst-delay-us = <221000>; #address-cells = <1>; #size-cells = <1>; };Copy to clipboard Last Published: Oct 14, 2024 [Previous Topic Tools](https://docs.qualcomm.com/bundle/publicresource/80-70015-26/topics/tools.md) [Next Topic Configure](https://docs.qualcomm.com/bundle/publicresource/80-70015-26/topics/configure.md)