# Architecture
Source: [https://docs.qualcomm.com/doc/80-70015-30/topic/architecture.html](https://docs.qualcomm.com/doc/80-70015-30/topic/architecture.html)
The CPU subsystem architecture describes the organization of CPU cores and their
power domains. Understanding the architecture helps you to monitor the CPU core usage and
make decisions to balance the power consumption and performance of Qualcomm Linux.
## QCS6490/QCS5430
APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at
a similar frequency. Each CPU core in a cluster has a dedicated L1 and L2 cache.
The CPU subsystem is composed of three clusters and L3 cache as follows:
- Qualcomm^®^ Kryo^™^ CPU Prime cluster, which has a
performance CPU core
- Kryo Gold cluster, which has CPU cores with balanced power and
performance
- Kryo Silver cluster, which has low power CPU cores for light weight
applications
- Common L3 cache
Figure : QCS6490/QCS5430 APSS CPU subsystem architecture
The CPU subsystem operates on two power domains, each supplied by a dedicated
switched mode power supply (SMPS) rail.
The following are the supported power domains:
Table : Power domains and their descriptions
| Power domains | Description |
| --- | --- |
| `VDD_APC0 ` | Power domain for the Silver cluster CPU cores and L3 cache
digital circuit |
| `VDD_APC1` | Power domain for the Gold and Prime clusters CPU
cores |
| `Chip_MX` | Power domain for the L1, L2, and L3 cache memories |
Note: To know more about CPU core arrangement, see [QCS6490 Data Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-23889-1/device-description.html) and [QCS5430 Data Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-23889-1/device-description.html).
## QCS9075
The CPU subsystem is composed of two clusters with a dedicated L3 cache. Each CPU
core in a cluster has a dedicated L1 and L2 cache. All CPU cores in a cluster
operate at a similar frequency.
Figure : QCS9075 APSS CPU subsystem architecture
The CPU subsystem operates on two power domains, each supplied by a dedicated SMPS
rail.
The following are the supported power domains:
Table : Power domains and their descriptions
| Power domains | Description |
| --- | --- |
| `VDD_APC0 ` | Power domain for Cluster0 CPU cores and L3 cache digital
circuit |
| `VDD_APC1` | Power domain for Cluster1 CPU cores and L3 cache digital
circuit |
| `Chip_MX` | Power domain for the L1, L2, and L3 cache memories |
To know more about CPU core arrangement, see [QCS9075 Data Sheet](https://docs.qualcomm.com/bundle/80-73417-1/resource/80-73417-1_REV_AA_QCS9075_Data_Sheet.pdf).
**Parent Topic:** [Power management](https://docs.qualcomm.com/doc/80-70015-30/topic/powermanagement.html)
Last Published: Oct 16, 2024
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