# Overview of peripheral interfaces
Source: [https://docs.qualcomm.com/doc/80-70015-8/topic/overview-of-wired-interfaces.html](https://docs.qualcomm.com/doc/80-70015-8/topic/overview-of-wired-interfaces.html)
The Qualcomm® Linux® interfaces guide describes both the low-speed and high-speed
input/output (I/O) peripheral interface subsystems used in the System-on-Chip
(SoC).
- The low-speed I/O interfaces operate at a lower frequency than the high-speed
interfaces in the SoC. The Qualcomm universal peripheral (QUP) v3 serial engine is a
hardware core that supports the following low-speed peripheral interfaces:
- Universal asynchronous receiver/transmitter ([UART](https://docs.qualcomm.com/doc/80-70015-8/topic/uart.html))
- Serial peripheral interface ([SPI](https://docs.qualcomm.com/doc/80-70015-8/topic/spi.html))
- Interintegrated circuit ([I2C](https://docs.qualcomm.com/doc/80-70015-8/topic/i2c.html))
- Improved interintegrated circuit ([I3C](https://docs.qualcomm.com/doc/80-70015-8/topic/i3c.html))
interfaces
These low-speed interfaces are used to communicate with low-speed
peripherals, such as sensor interface devices, Bluetooth® wireless technology
devices, display or touch interface devices, and other low-speed
devices.
- The high-speed I/O interfaces include the following protocols:
- Peripheral component interconnect express ([PCIe](https://docs.qualcomm.com/doc/80-70015-8/topic/pcie.html))
- Universal serial bus ([USB](https://docs.qualcomm.com/doc/80-70015-8/topic/usb.html))
The high-speed I/O interfaces are used to connect to high-speed devices,
such as solid-state drives, network cards, external graphics cards.
The following figure shows the software stack for peripheral interfaces.
Figure : Peripheral interfaces software stack
Note:Qualcomm uses QUP v3, a highly flexible and programmable
hardware to support a wide range of serial interfaces. For more information on QUP v3,
see the following resources:
- [QUP v3 overview](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html#introduction-to-qup-v3)
- [Supported transfer modes in QUP v3](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html#qup-v3-supported-transfer-modes)
- [QUP v3 access control customization](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html#customize-access-control-of-qup)
- [QUP v3 firmware status verification](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html#verify-qup-firmware-status)
### QCS6490 and QCS5430 interface overview
The following table lists the device interface features for QCS6490 and QCS5430. For
information on GPIO mapping of these chip products, see [QUP v3 mapping to protocols and GPIOs in QCS6490 and QCS5430](https://docs.qualcomm.com/doc/80-70015-8/topic/references.html#qup-v3-mapping-in-qcs6490).
| **2xQUP v3 serial engine** | **2xQUP v3 serial engine** | **2xQUP v3 serial engine** | **2xQUP v3 serial engine** |
| --- | --- | --- | --- |
| Serial engine instances | QUPV3\_0 | QUPV3\_1 | QUPV3\_1 |
| Application processor QUP v3 serial engine | 8 | 8 | 8 |
| LPI QUP v3 serial engine | 5 | – | – |
| **2xUSB controller** | **2xUSB controller** | **2xUSB controller** | **2xUSB controller** |
| Controller address | 0xa600000 | 0x8c00000 | 0x8c00000 |
| Max Speed | USB 3.x SuperSpeed | USB 2.0 high speed | USB 2.0 high speed |
| HS/SS PHY power rails |
|
| Interrupts | MSI and PCI legacy interrupts | MSI and PCI legacy interrupts | MSI and PCI legacy interrupts |
| Power management | ASPM (L1/L1ss, L0s) | ASPM (L1/L1ss, L0s) | ASPM (L1/L1ss, L0s) |
Note:
- The source code for boot and aDSP subsystems is restricted and may not be
accessible to all users.
- See [Hardware SoCs](https://docs.qualcomm.com/bundle/publicresource/topics/80-70015-115/soc.html) that are supported
on Qualcomm Linux.
This guide is your primary resource for information on enabling low and high-speed
I/O interfaces and making configuration changes.
### Conventions
Across this guide, `` refers to QCS6490, QCS5430, or
QCS9075. For example, for
arch/arm64/boot/dts/qcom/<chipset>.dts, the
corresponding device tree source (DTS) file is at [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts) or [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi).
Function declarations, function names, type declarations, attributes, and code
samples appear in a different font, for example, `cp armcc
armcpp`.
Code variables appear in angle brackets, for example
<number>.
Button and key names appear in bold font, for example, click
Save or press Enter.
Last Published: Oct 15, 2024
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