# Overview of peripheral interfaces
Source: [https://docs.qualcomm.com/doc/80-70018-8/topic/overview-of-wired-interfaces.html](https://docs.qualcomm.com/doc/80-70018-8/topic/overview-of-wired-interfaces.html)
The Qualcomm® Linux® interfaces guide describes both the low-speed and high-speed
input/output (I/O) peripheral interface subsystems used in the System-on-Chip
(SoC).
- The low-speed I/O interfaces operate at a lower frequency than the high-speed
interfaces in the SoC. The Qualcomm universal peripheral (QUP) v3 serial engine is a
hardware core that supports the following low-speed peripheral interfaces:
- Universal asynchronous receiver/transmitter ([UART](https://docs.qualcomm.com/doc/80-70018-8/topic/uart.html))
- Serial peripheral interface ([SPI](https://docs.qualcomm.com/doc/80-70018-8/topic/spi.html))
- Interintegrated circuit ([I2C](https://docs.qualcomm.com/doc/80-70018-8/topic/i2c.html))
- Improved interintegrated circuit ([I3C](https://docs.qualcomm.com/doc/80-70018-8/topic/i3c.html))
These low-speed interfaces communicate with low-speed peripherals, such as
sensor interface devices, Bluetooth® wireless technology devices, display or
touch interface devices.
- The high-speed I/O interfaces include the following peripheral interfaces:
- Peripheral component interconnect express ([PCIe](https://docs.qualcomm.com/doc/80-70018-8/topic/pcie.html))
- Universal serial bus ([USB](https://docs.qualcomm.com/doc/80-70018-8/topic/usb.html))
The high-speed I/O interfaces are used to connect to high-speed devices,
such as solid-state drives, network cards, external graphics cards.
The following figure shows the software stack for peripheral interfaces.
Figure : Peripheral interfaces software stack
## QUP v3
Qualcomm uses QUP v3, a highly flexible and programmable hardware to support a wide
range of serial interfaces. For more information about QUP v3, see the following
resources:
- [QUP v3 overview](https://docs.qualcomm.com/doc/80-70018-8/topic/references.html#introduction-to-qup-v3)
- [Supported transfer modes in QUP v3](https://docs.qualcomm.com/doc/80-70018-8/topic/references.html#qup-v3-supported-transfer-modes)
- [QUP v3 access control customization](https://docs.qualcomm.com/doc/80-70018-8/topic/references.html#customize-access-control-of-qup)
- [QUP v3 firmware status verification](https://docs.qualcomm.com/doc/80-70018-8/topic/references.html#verify-qup-firmware-status)
Note:
- The source code for boot and aDSP subsystems is available to licensed
developers with authorized access.
- See [Hardware SoCs](https://docs.qualcomm.com/bundle/publicresource/topics/80-70017-115/soc.html) that are supported
on Qualcomm Linux.
This guide is your primary resource for information about enabling low-speed and
high-speed I/O interfaces and making configuration changes.
Note:
Across this guide, `` refers to QCS6490, QCS5430,
QCS9075, or QCS8275. For example, for
arch/arm64/boot/dts/qcom/<chipset>.dts, the
corresponding device tree source (DTS) file is at [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts) or [https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi](https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/qcom/sa8775p.dtsi).
- **[QCS6490 and QCS5430 interface overview](https://docs.qualcomm.com/doc/80-70018-8/topic/qcs6490-and-qcs5430-interface-overview.html)**
- **[QCS9075 interface overview](https://docs.qualcomm.com/doc/80-70018-8/topic/qcs9075-interface-overview.html)**
- **[QCS8275 interface overview](https://docs.qualcomm.com/doc/80-70018-8/topic/qcs8275-interface-overview.html)**
Last Published: Mar 26, 2025
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