# Performance overview

This guide explains how to measure, fine-tune, and enhance the
performance of Qualcomm^®^ Linux^®^. Additionally, it
discusses:

- Features that impact performance
- Tools to identify and analyze performance issues
- Options to configure and customize the Linux settings for enhanced
performance
- Methods to troubleshoot performance issues
- Procedures to measure performance
- Performance dashboards for QCS6490 and QCS5430

Note

See [Hardware SoCs](https://docs.qualcomm.com/bundle/publicresource/topics/80-70022-115/soc.html)
that are supported on Qualcomm Linux.

The following guides contain supplementary information and are available to licensed users with authorized access:

- [Qualcomm Linux Performance Guide - Addendum for Qualcomm Dragonwing IQ-9075](https://docs.qualcomm.com/bundle/resource/topics/80-70022-10A/overview.html)
- [Qualcomm Linux Performance Guide - Addendum for Qualcomm Dragonwing IQ-8275](https://docs.qualcomm.com/bundle/resource/topics/80-70022-10B/overview.html)
- [Qualcomm Linux Performance Guide - Addendum for Qualcomm Dragonwing IQ-615](https://docs.qualcomm.com/bundle/resource/topics/80-70022-10C/overview.html)

These guides describe device specifications, supported resource opcodes, chipset-specific configuration and customization settings, performance dashboards, and measurement procedures.

## Subsystem dependencies

The performance of the software depends on the CPU, GPU, and DDR
subsystems. Qualcomm Linux uses the Qualcomm^®^ Kryo^™^ CPU, which has the
following clusters:

- Prime cluster for high-performance CPU cores
- Gold cluster for balanced power and performance
- Silver cluster for low-power CPU cores, ideal for light-weight
applications

Cache memory is categorized into three levels: L1, L2, and L3:

- L1 is the smallest and fastest cache level, storing both instructions
(L1 I) and data (L1 D)
- L2 and L3 are larger but slower cache levels, mainly for data storage

The following tables list the specifications for the subsystems on
QCS6490 and QCS5430:

Tab QCS6490
Tab QCS5430

| Specifications | QCS6490 | QCS6490 | QCS6490 | QCS6490 |
| --- | --- | --- | --- | --- |
| Core type | Kryo Prime | Kryo Gold | Kryo Silver | Kryo Silver |
| Number of CPUs | 1 | 3 | 4 | 4 |
| CPU maximum frequency | 2.7 GHz | 2.4 GHz | 1.9 GHz | 1.9 GHz |
| L1 I cache | 32 kB | 32 kB/core | 32 kB/core | 32 kB/core |
| L1 D cache | 32 kB | 32 kB/core | 32 kB/core | 32 kB/core |
| L2 cache | 256 kB | 256 kB/core | 128 kB/core | 128 kB/core |
| L3 cache | 2 MB | 2 MB | 2 MB | 2 MB |
| GPU | Qualcomm^®^ Adreno^™^ 643 GPU | Qualcomm^®^ Adreno^™^ 643 GPU | Qualcomm^®^ Adreno^™^ 643 GPU | Qualcomm^®^ Adreno^™^ 643 GPU |
| GPU maximum frequency | 812 MHz | 812 MHz | 812 MHz | 812 MHz |
| DDRSS | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> |

| Specifications | QCS5430 FP 1 (feature pack 1) | QCS5430 FP 1 (feature pack 1) | QCS5430 FP 2 | QCS5430 FP 2 | QCS5430 FP 2 | QCS5430 FP 2 |
| --- | --- | --- | --- | --- | --- | --- |
| Core type | Kryo Gold | Kryo Silver | Kryo Prime | Kryo Gold | Kryo Silver | Kryo Silver |
| Number of CPUs | 2 | 4 | 1 | 3 | 4 | 4 |
| CPU maximum frequency | 2.1 GHz | 1.8 GHz | 2.2 GHz | 2.1 GHz | 1.8 GHz | 1.8 GHz |
| L1 I cache | 32 kB/core | 32 kB/core | 32 kB | 32 kB/core | 32 kB/core | 32 kB/core |
| L2 cache | 256 kB/core | 128 kB/core | 256 kB | 256 kB/core | 128 kB/core | 128 kB/core |
| L3 cache | 2 MB | 2 MB | 2 MB | 2 MB | 2 MB | 2 MB |
| GPU | Qualcomm^®^ Adreno^™^ 642L GPU | Qualcomm^®^ Adreno^™^ 642L GPU | Qualcomm^®^ Adreno^™^ 642L GPU | Qualcomm^®^ Adreno^™^ 642L GPU | Qualcomm^®^ Adreno^™^ 642L GPU | Qualcomm^®^ Adreno^™^ 642L GPU |
| GPU maximum frequency | 315 MHz | 315 MHz | 315 MHz | 315 MHz | 315 MHz | 315 MHz |
| DDRSS | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> |

| Specifications | QCS5430 FP 2.5 | QCS5430 FP 2.5 | QCS5430 FP 2.5 | QCS5430 FP 3 | QCS5430 FP 3 | QCS5430 FP 3 |
| --- | --- | --- | --- | --- | --- | --- |
| Core type | Kryo Prime | Kryo Gold | Kryo Silver | Kryo Prime | Kryo Gold | Kryo Silver |
| Number of CPUs | 1 | 3 | 4 | 1 | 3 | 4 |
| CPU maximum frequency | 2.38 GHz | 2.4 GHz | 1.8 GHz | 2.38 GHz | 2.4 GHz | 1.8 GHz |
| L1 I cache | 32 kB | 32 kB/core | 32 kB/core | 32 kB | 32 kB/core | 32 kB/core |
| L2 cache | 256 kB | 256 kB/core | 128 kB/core | 256 kB | 256 kB/core | 128 kB/core |
| L3 cache | 2 MB | 2 MB | 2 MB | 2 MB | 2 MB | 2 MB |
| GPU | Qualcomm Adreno 642L GPU | Qualcomm Adreno 642L GPU | Qualcomm Adreno 642L GPU | Qualcomm Adreno 642L GPU | Qualcomm Adreno 642L GPU | Qualcomm Adreno 642L GPU |
| GPU maximum frequency | 550 MHz | 550 MHz | 550 MHz | 550 MHz | 550 MHz | 550 MHz |
| DDRSS | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> | > <br>> <br>> <ul class="simple"><br>> <li><p>Supports dual-channel non-package-on-package high-speed<br>> LPDDR5/LPDDR4 SDRAM.</p></li><br>> <li><p>LPDDR5 SDRAM is designed for a 3200&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> <li><p>LPDDR4 SDRAM is designed for a 2133&nbsp;MHz clock (2 ×<br>> 16‑bit).</p></li><br>> </ul> |

## Next steps

- [Get started with performance tuning and optimization](https://docs.qualcomm.com/doc/80-70022-10/topic/get-started.html#get-started)
- [Prepare performance build](https://docs.qualcomm.com/doc/80-70022-10/topic/get-started.html#performance-build)

Last Published: Oct 10, 2025

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