# Electrical specifications
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
## Absolute maximum ratings
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
The absolute maximum ratings shown in the following table reflect the stress levels that,
if exceeded, may cause permanent damage to the device. No functionality is guaranteed
outside the operating specifications. Functionality and reliability are only guaranteed
within the operating conditions described in [Operating conditions](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_jfw_yyz_mzb).
| Power supply | Description | Min | Max | Unit |
| --- | --- | --- | --- | --- |
| VDD\_APC0 | Power for the cluster 0 of Kryo Gold Prime processors | -0.3 | 1.133 | V |
| VDD\_APC1 | Power for the cluster 1 of Kryo Gold Prime processors | -0.3 | 1.133 | V |
| VDD\_A\_APC\_CS\_1P2 | Power for application processor current sensor 1.2 V
analog circuits | -0.3 | 1.430 | V |
| VDD\_A\_NSP0\_CS\_1P2 | Power for HTP0 current sensor 1.2 V circuits | -0.3 | 1.430 | V |
| VDD\_A\_NSP1\_CS\_1P2 | Power for HTP1 current sensor 1.2 V circuits | -0.3 | 1.430 | V |
| VDD\_PX11 | Power for pad group 11 | -0.3 | 1.430 | V |
| VDD\_RTSS\_PX11 | Power for RTSS pad group 11 | -0.3 | 1.430 | V |
| VDD\_CX | Power for digital core circuits | -0.3 | 1.133 | V |
| VDD\_D\_EBI | Power for EBI digital circuits | -0.3 | 1.133 | V |
| VDD\_RTSS\_CX | Power for RTSS digital core circuits | -0.3 | 1.133 | V |
| VDD\_CX\_LPI | Power for Low-power island digital core circuits | -0.3 | 1.133 | V |
| VDD\_GFX | Power for graphics | -0.3 | 1.133 | V |
| VDD\_MM | Power for multimedia subsystem circuits | -0.3 | 1.133 | V |
| VDD\_MX\_A | Power for always-ON memory circuits | -0.3 | 1.133 | V |
| VDD\_RTSS\_MX | Power for RTSS On-chip memory circuits | -0.3 | 1.133 | V |
| VDD\_MX\_C | Power for collapsible memory circuits | -0.3 | 1.133 | V |
| VDD\_MX\_LPI | Power for Low-power island memory circuit | -0.3 | 1.133 | V |
| VDD\_NSP0 | Power for Hexagon Tensor Processor 0 | -0.3 | 1.300 | V |
| VDD\_NSP1 | Power for Hexagon Tensor Processor 1 | -0.3 | 1.300 | V |
| VDD\_PX0 | Power for pad group 0 | -0.3 | 2.090 | V |
| VDD\_RTSS\_PX0 | Power for RTSS pad group 0 | -0.3 | 2.090 | V |
| VDD\_PX1 | Power for pad group 1 | -0.3 | 1.232 | V |
| VDD\_PX10 | Power for pad group 10 | -0.3 | 1.375 | V |
| VDD\_PX3 | Power for pad group 3 | -0.3 | 2.090 | V |
| VDD\_PX7 | Power for pad group 7 | -0.3 | 2.090 | V |
| VDD\_QFPROM | Power for programming the QFPROM | -0.3 | 2.090 | V |
| VDD\_RTSS\_PX3 | Power for RTSS pad group 3 | -0.3 | 2.090 | V |
| VDD\_QFPROM\_RTSS | Power for programming the QFPROM RTSS | -0.3 | 2.090 | V |
| VDD\_PX9 | Power for pad group 9 | -0.3 | 1.375 | V |
| VDD\_RTSS\_PX8 | Power for RTSS pad group 8 | -0.3 | 2.915 | V |
| VBIAS\_RTSS\_RGMII | Power for RTSS\_RGMII reference circuits; 0.85 V | -0.3 | 0.990 | V |
| VDD\_A\_CSI\_0\_1\_0P9 | Power for MIPI CSI0/CSI1 0.9 V analog circuits | -0.3 | 1.012 | V |
| VDD\_A\_CSI\_2\_3\_0P9 | Power for MIPI CSI2/CSI3 0.9 V analog circuits | -0.3 | 1.012 | V |
| VDD\_A\_DSI\_0\_0P9 | Power for MIPI DSI0 0.9 V analog circuits | -0.3 | 1.012 | V |
| VDD\_A\_DSI\_0\_PLL\_0P9 | Power for MIPI DSI0 PLL 0.9 V | -0.3 | 1.012 | V |
| VDD\_A\_DSI\_1\_0P9 | Power for MIPI DSI1 0.9 V analog circuits | -0.3 | 1.012 | V |
| VDD\_A\_DSI\_1\_PLL\_0P9 | Power for MIPI DSI1 PLL 0.9 V | -0.3 | 1.012 | V |
| VDD\_A\_EDP\_0\_0P9 | Power for EDP 0 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_EDP\_1\_0P9 | Power for EDP 1 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_EDP\_2\_0P9 | Power for EDP 2 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_EDP\_3\_0P9 | Power for EDP 3 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_REFGEN\_0P875 | Power for high-speed interface reference generation
circuits – 0.875 V | -0.3 | 1.012 | V |
| VDD\_A\_SGMII\_0\_0P9 | Power for serial gigabit media-independent interface
0 - 0.9 V | -0.3 | 1.012 | V |
| VDD\_A\_SGMII\_1\_0P9 | Power for serial gigabit media-independent interface
1 - 0.9 V | -0.3 | 1.012 | V |
| VDD\_A\_UFS\_0\_0P9 | Power for the UFS0 0.9 V analog circuits | -0.3 | 1.012 | V |
| VDD\_A\_UFS\_1\_0P9 | Power for the UFS1 0.9 V analog circuits | -0.3 | 1.012 | V |
| VDD\_A\_CSI\_0\_1P2 | Power for MIPI CSI0 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_CSI\_1\_1P2 | Power for MIPI CSI1 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_CSI\_2\_1P2 | Power for MIPI CSI2 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_CSI\_3\_1P2 | Power for MIPI CSI3 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_DSI\_0\_1\_1P2 | Power for MIPI DSI0/DSI1 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_EDP\_0\_1P2 | Power for EDP 0 1.2 V circuits | -0.3 | 1.375 | V |
| VDD\_A\_EDP\_1\_1P2 | Power for EDP 1 1.2 V circuits | -0.3 | 1.375 | V |
| VDD\_A\_EDP\_2\_1P2 | Power for EDP 2 1.2 V circuits | -0.3 | 1.375 | V |
| VDD\_A\_EDP\_3\_1P2 | Power for EDP 3 1.2 V circuits | -0.3 | 1.375 | V |
| VDD\_A\_PCIE\_0\_PLL\_1P2 | Power for PCIe 0 PLL 1.2 V circuits | -0.3 | 1.375 | V |
| VDD\_A\_PCIE\_1\_PLL\_1P2 | Power for PCIe 1 PLL 1.2 V circuits | -0.3 | 1.375 | V |
| VDD\_A\_REFGEN\_1P2 | Power for high-speed interface reference generation
circuits – 1.2 V | -0.3 | 1.375 | V |
| VDD\_A\_SGMII\_0\_1P2 | Power for serial gigabit media-independent interface
0 - 1.2 V | -0.3 | 1.375 | V |
| VDD\_A\_SGMII\_1\_1P2 | Power for serial gigabit media-independent interface
1 - 1.2 V | -0.3 | 1.375 | V |
| VDD\_A\_UFS\_0\_1P2 | Power for the UFS0 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_UFS\_1\_1P2 | Power for the UFS1 1.2 V analog circuits | -0.3 | 1.375 | V |
| VDD\_A\_USBSS\_0\_1P2 | Power for USB super-speed 0 1.2 V circuits | -0.3 | 1.375 | V |
| VDD\_A\_USBSS\_1\_1P2 | Power for USB super-speed 1 1.2 V circuits | -0.3 | 1.375 | V |
| VDD\_A\_USBHS\_0\_0P9 | Power for USB high-speed 0 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_USBHS\_1\_0P9 | Power for USB high-speed 1 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_USBHS\_2\_0P9 | Power for USB high-speed 2 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_USBSS\_0\_0P9 | Power for USB super-speed 0 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_USBSS\_1\_0P9 | Power for USB super-speed 1 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_USBHS\_0\_3P1 | Power for USB high-speed 0 3.1 V circuits | -0.3 | 3.520 | V |
| VDD\_A\_USBHS\_1\_3P1 | Power for USB high-speed 1 3.1 V circuits | -0.3 | 3.520 | V |
| VDD\_A\_USBHS\_2\_3P1 | Power for USB high-speed 2 3.1 V circuits | -0.3 | 3.520 | V |
| VDD\_A\_USBHS\_0\_1P8 | Power for USB high-speed 0 1.8 V circuits | -0.3 | 2.145 | V |
| VDD\_A\_USBHS\_1\_1P8 | Power for USB high-speed 1 1.8 V circuits | -0.3 | 2.145 | V |
| VDD\_A\_USBHS\_2\_1P8 | Power for USB high-speed 2 1.8 V circuits | -0.3 | 2.145 | V |
| VDD\_A\_PCIE\_0\_0P9 | Power for PCIe 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_PCIE\_1\_0P9 | Power for PCIe 0.9 V circuits | -0.3 | 1.012 | V |
| VDD\_A\_EBI\_01\_0P9 | Power for EBI0/EBI1 circuits | -0.3 | 1.133 | V |
| VDD\_A\_EBI\_PLL | Power for EBI PHY PLL circuits | -0.3 | 1.133 | V |
| VDD\_A\_EBI\_23\_45\_0P9 | Power for EBI2/EBI3/EBI4/EBI5 PHY 0.9 V circuits | -0.3 | 1.133 | V |
| VDD\_IO\_EBI\_01 | Power for EBI0/EBI1 I/O circuits | -0.3 | 0.627 | V |
| VDD\_IO\_EBI\_23\_45 | Power for EBI2/EBI3/EBI4/EBI5 I/O circuits | -0.3 | 0.627 | V |
| Ts | Storage temperature[^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_1_absolute-maximum-ratings)^,^ [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_2_absolute-maximum-ratings) | -55 | 150 | °C |
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[^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_1_absolute-maximum-ratings) The storage temperature range applies when the
device is in the OFF state (the device is not assembled in any
platform and is not electrically connected to any voltage or I/O
signals). Damage may occur when the device is subjected to this
temperature for any length of time.
[^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_2_absolute-maximum-ratings) For devices shipped
in tape and reel, the storage temperature range is [+15°C~35°C] and
<-90% relative humidity (RH). QTI recommends allowing the device
to return to ambient room temperature before usage.
## Operating conditions
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
The QCS9075 meets all performance specifications, when used within
the operating conditions, unless otherwise noted in those sections (provided the
absolute maximum ratings have never been exceeded).
| Parameter | Parameter | Min | Max | Unit |
| --- | --- | --- | --- | --- |
| **Power supply voltages** | **Power supply voltages** | **Power supply voltages** | **Power supply voltages** | **Power supply voltages** |
| VDD\_APC0 | Power for the cluster 0 of Kryo Gold Prime
processors | | | |
| | Active | 0.576 | 1.030 | V |
| VDD\_APC1 | Power for the cluster 1 of Kryo Gold Prime processors | | | |
| | Active | 0.576 | 1.030 | V |
| VDD\_CX | Power for digital core circuits | | | |
| VDD\_D\_EBI | Power for EBI digital circuits | | | |
| VDD\_RTSS\_CX | Power for RTSS digital core circuits | | | |
| | Active | 0.560 | 1.030 | V |
| | Retention [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_jfw_yyz_mzb__fn_hnf_rxg_kbc_radhikav_05-15-24-1029-58-310) | 0.352 | 0.480 | V |
| VDD\_CX\_LPI | Power for Low-power island digital core circuits | | | |
| | Active | 0.560 | 1.030 | V |
| | Retention [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_jfw_yyz_mzb__fn_hnf_rxg_kbc_radhikav_05-15-24-1029-58-310) | 0.352 | 0.480 | V |
| VDD\_GFX | Power for graphics | | | |
| | Active | 0.560 | 1.030 | V |
| VDD\_MM | Power for multimedia subsystem circuits | | | |
| | Active | 0.560 | 1.030 | V |
| VDD\_MX\_A | Power for always-ON memory circuits | | | |
| VDD\_RTSS\_MX | Power for RTSS On-chip memory circuits | | | |
| | Active | 0.716 | 1.030 | V |
| | Retention [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_jfw_yyz_mzb__fn_hnf_rxg_kbc_radhikav_05-15-24-1029-58-310) | 0.504 | 0.680 | V |
| VDD\_MX\_C | Power for collapsible memory circuits | | | |
| | Active | 0.716 | 1.030 | V |
| VDD\_MX\_LPI | Power for Low-power island memory circuit | | | |
| | Active | 0.695 | 1.030 | V |
| | Retention [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_jfw_yyz_mzb__fn_hnf_rxg_kbc_radhikav_05-15-24-1029-58-310) | 0.504 | 0.680 | V |
| VDD\_NSP0 | Power for Hexagon Tensor Processor 0 | | | |
| | Active | 0.560 | 1.030 | V |
| VDD\_NSP1 | Power for Hexagon Tensor Processor 1 | | | |
| | Active | 0.560 | 1.030 | V |
| VDD\_A\_EBI\_0P9 | Power for EBI PHY 0.9 V circuits | | | |
| VDD\_A\_EBI\_PLL | Power for EBI PHY PLL circuits | | | |
| VDD\_A\_EBI\_23\_45\_0P9 | Power for EBI2/EBI3/EBI4/EBI5 I/O circuits | | | |
| | Active | 0.835 | 1.030 | V |
| | Retention [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_jfw_yyz_mzb__fn_hnf_rxg_kbc_radhikav_05-15-24-1029-58-310) | 0.352 | 0.480 | V |
^1^ The
retention voltage is the PMIC output setting and it is static. There
is no scaling.
| Parameter[^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_2_operating-conditions) | Parameter[^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_2_operating-conditions) | Min | Typ[^3^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_3_operating-conditions) | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| Power supply
voltages | Power supply
voltages | Power supply
voltages | Power supply
voltages | Power supply
voltages | Power supply
voltages |
| VDD\_A\_APC\_CS\_1P2 | Power for application processor current sensor 1.2 V
analog circuits | 1.100 | 1.200 | 1.300 | V |
| VDD\_A\_NSP0\_CS\_1P2 | Power for HTP0 current sensor 1.2 V circuits | 1.100 | 1.200 | 1.300 | V |
| VDD\_A\_NSP1\_CS\_1P2 | Power for HTP1 current sensor 1.2 V circuits | 1.100 | 1.200 | 1.300 | V |
| VDD\_PX11 | Power for pad group 11 | 1.100 | 1.200 | 1.300 | V |
| VDD\_RTSS\_PX11 | Power for RTSS pad group 11 | 1.100 | 1.200 | 1.300 | V |
| VDD\_PX0 | Power for pad group 0 | 1.700 | 1.800 | 1.900 | V |
| VDD\_RTSS\_PX0 | Power for RTSS pad group 0 | 1.700 | 1.800 | 1.900 | V |
| VDD\_PX1 | Power for pad group 1 | 1.010 | 1.100 | 1.120 | V |
| VDD\_PX10 | Power for pad group 10 | 1.100 | 1.200 | 1.250 | V |
| VDD\_PX3 | Power for pad group 3 | 1.700 | 1.800 | 1.900 | V |
| VDD\_PX7 | Power for pad group 7 | 1.700 | 1.800 | 1.900 | V |
| VDD\_QFPROM | Power for programming the QFPROM | 1.700 | 1.800 | 1.900 | V |
| VDD\_RTSS\_PX3 | Power for RTSS pad group 3 | 1.700 | 1.800 | 1.900 | V |
| VDD\_QFPROM\_RTSS | Power for programming the QFPROM RTSS | 1.700 | 1.800 | 1.900 | V |
| VDD\_PX9 | Power for pad group 9 | 1.100 | 1.200 | 1.250 | V |
| VDD\_RTSS\_PX8 | Power for RTSS pad group 8 | 1.700 | 1.800 | 1.900 | V |
| VBIAS\_RTSS\_RGMII | Power for RTSS\_RGMII reference circuits; 0.85 V | 0.800 | 0.850 | 0.900 | V |
| VDD\_A\_CSI\_0\_1\_0P9 | Power for MIPI CSI0/CSI1 0.9 V analog circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_CSI\_2\_3\_0P9 | Power for MIPI CSI2/CSI3 0.9 V analog circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_DSI\_0\_0P9 | Power for MIPI DSI0 0.9 V analog circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_DSI\_0\_PLL\_0P9 | Power for MIPI DSI0 PLL 0.9 V | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_DSI\_1\_0P9 | Power for MIPI DSI1 0.9 V analog circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_DSI\_1\_PLL\_0P9 | Power for MIPI DSI1 PLL 0.9 V | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_EDP\_0\_0P9 | Power for EDP 0 0.9 V circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_EDP\_1\_0P9 | Power for EDP 1 0.9 V circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_EDP\_2\_0P9 | Power for EDP 2 0.9 V circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_EDP\_3\_0P9 | Power for EDP 3 0.9 V circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_REFGEN\_0P875 | Power for high-speed interface reference generation
circuits – 0.875 V | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_SGMII\_0\_0P9 | Power for serial giga bit media-independent interface 0 -
0.9 V | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_SGMII\_1\_0P9 | Power for serial giga bit media-independent interface 1 -
0.9 V | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_UFS\_0\_0P9 | Power for the UFS0 0.9 V analog circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_UFS\_1\_0P9 | Power for the UFS1 0.9 V analog circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_CSI\_0\_1P2 | Power for MIPI CSI0 1.2 V analog circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_CSI\_1\_1P2 | Power for MIPI CSI1 1.2 V analog circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_CSI\_2\_1P2 | Power for MIPI CSI2 1.2 V analog circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_CSI\_3\_1P2 | Power for MIPI CSI3 1.2 V analog circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_DSI\_0\_1\_1P2 | Power for MIPI DSI0/DSI1 1.2 V analog circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_EDP\_0\_1P2 | Power for EDP 0 1.2 V circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_EDP\_1\_1P2 | Power for EDP 1 1.2 V circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_EDP\_2\_1P2 | Power for EDP 2 1.2 V circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_EDP\_3\_1P2 | Power for EDP 3 1.2 V circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_PCIE\_0\_PLL\_1P2 | Power for PCIe 0 PLL 1.2 V circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_PCIE\_1\_PLL\_1P2 | Power for PCIe 1 PLL 1.2 V circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_REFGEN\_1P2 | Power for high-speed interface reference generation
circuits – 1.2 V | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_SGMII\_0\_1P2 | Power for serial giga bit media-independent interface 0 -
1.2 V | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_SGMII\_1\_1P2 | Power for serial giga bit media-independent interface 1 -
1.2 V | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_UFS\_0\_1P2 | Power for the UFS0 1.2 V analog circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_UFS\_1\_1P2 | Power for the UFS1 1.2 V analog circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_USBSS\_0\_1P2 | Power for USB super-speed 0 1.2 V circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_USBSS\_1\_1P2 | Power for USB super-speed 1 1.2 V circuits | 1.150 | 1.200 | 1.250 | V |
| VDD\_A\_USBHS\_0\_0P9 | Power for USB high-speed 0 0.9 V circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_USBHS\_1\_0P9 | Power for USB high-speed 1 0.9 V circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_USBHS\_2\_0P9 | Power for USB high-speed 2 0.9 V circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_USBSS\_0\_0P9 | Power for USB super-speed 0 0.9 V circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_USBSS\_1\_0P9 | Power for USB super-speed 1 0.9 V circuits | 0.830 | 0.880 | 0.920 | V |
| VDD\_A\_USBHS\_0\_3P1 | Power for USB high-speed 0 3.1 V circuits | 2.970 | 3.072 | 3.200 | V |
| VDD\_A\_USBHS\_1\_3P1 | Power for USB high-speed 1 3.1 V circuits | 2.970 | 3.072 | 3.200 | V |
| VDD\_A\_USBHS\_2\_3P1 | Power for USB high-speed 2 3.1 V circuits | 2.970 | 3.072 | 3.200 | V |
| VDD\_A\_USBHS\_0\_1P8 | Power for USB high-speed 0 1.8 V circuits | 1.650 | 1.800 | 1.950 | V |
| VDD\_A\_USBHS\_1\_1P8 | Power for USB high-speed 1 1.8 V circuits | 1.650 | 1.800 | 1.950 | V |
| VDD\_A\_USBHS\_2\_1P8 | Power for USB high-speed 2 1.8 V circuits | 1.650 | 1.800 | 1.950 | V |
| VDD\_A\_PCIE\_0\_0P9 | Power for PCIe 0.9 V circuits | 0.880 | 0.912 | 0.960 | V |
| VDD\_A\_PCIE\_1\_0P9 | Power for PCIe 0.9 V circuits | 0.880 | 0.912 | 0.960 | V |
| VDD\_IO\_EBI | Power for EBI I/O circuits | 0.470 | 0.500 | 0.570 | V |
| VDD\_IO\_EBI\_23\_45 | Power for EBI2/EBI3/EBI4/EBI5 I/O circuits | 0.470 | 0.500 | 0.570 | V |
| **Thermal Conditions** | **Thermal Conditions** | **Thermal Conditions** | **Thermal Conditions** | **Thermal Conditions** | **Thermal Conditions** |
| TA | Ambient operating temperature | -40 | – | 85 [^4^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_4_operating-conditions) | °C |
| TJ | Junction operating temperature | – | – | 115 | °C |
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[^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_2_operating-conditions) Parts with voltages
outside of the specified ranges are not guaranteed to operate
properly.
[^3^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_3_operating-conditions) Typical voltages represent the recommended output settings of
the companion PMIC device.
[^4^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_4_operating-conditions) The TJ max specification must be met.
## Average operating current
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
This information will be included in future version of this document.
## Power-on circuits and power sequence
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Dedicated circuits continuously monitor several events that might trigger a power-on
sequence. If any of these events occur, the PMIC circuits are powered on, the system’s
available power sources are determined, the correct source is enabled, and the SoC is
taken out of reset.
Figure : QCS9075 and PMIC power-on sequence
## Digital logic characteristics
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
A digital I/O’s performance specification depends on its pad type, its usage, and/or its
supply voltage.
- Some are dedicated for interconnections between the QCS9075
device and other ICs within the QTI chipset; therefore, specifications are not
required.
- Some are defined by existing standards, such as I²C and SPI. QTI devices comply with
those standards; therefore, additional specifications are not required.
- All other digital I/Os require performance specifications.
- Back powering protection is not supported in digital pads unless otherwise specified
in the following table. All non-bpp digital pads must be kept at less than 50 mV and
with a maximum of 1 µA current being injected into the pad to avoid potential
back-power scenarios.
Note: Unless otherwise specified, all device characterizations are
carried out across the specified operating temperature and voltage ranges.
Table : Digital I/Os specified in this section
| Pad voltage | Usage | Table |
| --- | --- | --- |
| 1.8 V | VDD\_PX0, VDD\_RTSS\_PX0, VDD\_PX3, VDD\_RTSS\_PX3 | [Table : DC specification of 1.8 V I/Os](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__table_ymd_mfb_nzb_radhikav_11-21-23-1100-3-596) |
| 1.8 V | VDD\_RTSS\_PX8 | [Table : DC specifications for RGMII 1.8 V mode (VDD_RTSS_PX8)](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__table_wgf_hmb_nzb_radhikav_11-21-23-1151-55-742) |
| 1.2 V | VDD\_PX9/VDD\_PX10 | [Table : Digital I/O characteristics for UFS_RESET and UFS_REF_CLK
(VDD_PX9/VDD_PX10)](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__table_d2p_hmb_nzb_radhikav_11-21-23-1152-2-431) |
Table : DC specification of 1.8 V I/Os
| Parameter | Description | Min | Max | Unit |
| :---: | --- | :---: | :---: | :---: |
| VIH | High-level input voltage, CMOS/Schmitt (HIHYS\_EN = low) | 0.65 × VDD\_PXx | VDD\_PXx [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_ahl_dfb_nzb_radhikav_11-21-23-1057-30-666) +
0.3 | V |
| VIL | Low-level input voltage, CMOS/Schmitt (HIHYS\_EN = low) | -0.3 | 0.35 × VDD\_PXx [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_ahl_dfb_nzb_radhikav_11-21-23-1057-30-666) | V |
| VIH | High-level input voltage, CMOS/Schmitt (HIHYS\_EN = high) | 0.7 × VDD\_PXx | VDD\_PXx [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_ahl_dfb_nzb_radhikav_11-21-23-1057-30-666) +0.3 | V |
| VIL | Low-level input voltage, CMOS/Schmitt (HIHYS\_EN = high) | -0.3 | 0.3 × VDD\_PXx [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_ahl_dfb_nzb_radhikav_11-21-23-1057-30-666) | V |
| VSHYS | Schmitt hysteresis voltage (HIHYS\_EN= low) | 100 | – | mV |
| VSHYS | Schmitt hysteresis voltage (HIHYS\_EN = high) | 300 | – | mV |
| IIH | Input high leakage current | – | 3 | µA |
| IIL | Input low leakage current | -1 | – | µA |
| RPD | Pull-down resistance | 20k | 60k | Ω |
| RPU | Pull-up resistance | 20k | 60k | Ω |
| RKP | Bus keeper resistor | 20k | 60k | Ω |
| VOH | High-level output voltage, CMOS [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_i5h_xls_fgc) | VDD\_PXx [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_ahl_dfb_nzb_radhikav_11-21-23-1057-30-666) -0.45 | VDD\_PXx [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_ahl_dfb_nzb_radhikav_11-21-23-1057-30-666) | V |
| VOL | Low-level output voltage, CMOS [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_i5h_xls_fgc) | 0.0 | 0.45 | V |
^1^ VDD\_PXx
can be VDD\_PX0, VDD\_RTSS\_PX0, VDD\_PX3, VDD\_RTSS\_PX3 depending on the
pad group.
^2^ VOL and VOH are measured at
IOL and IOH respectively, with 16 mA
current across min and max voltages and operating temperatures. For
more information regarding possible drive strength settings, see
[Table : Possible drive strength settings](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__table_j5b_vjs_fgc).
Table : Possible drive strength settings
| BIT configuration | Drive strength (mA) |
| --- | --- |
| 000 | 2 |
| 001 | 4 |
| 010 | 6 |
| 011 | 8 |
| 100 | 10 |
| 101 | 12 |
| 110 | 14 |
| 111 | 16 |
Table : DC specifications for RGMII 1.8 V mode (VDD_RTSS_PX8)
| Parameter | Description | Min | Max | Unit |
| :---: | --- | :---: | :---: | :---: |
| VOL | Low-level output voltage [^3^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_bk5_mps_fgc) | – | 0.45 | V |
| VOH | High-level output voltage [^3^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_bk5_mps_fgc) | VDD\_PXx - 0.45 | – | V |
| VIL | Low-level input voltage | -0.3 | 0.35× VDD\_PXx | V |
| VIH | High-level input voltage | 0.65× VDD\_PXx | VDD\_PXx+ 0.3 | V |
| VHYS | Input Hysteresis | 100 | – | mV |
| RPULL-UP | Pull-up resistance | 20 | 50 | kΩ |
| RPULL-DOWN | Pull-down resistance | 20 | 50 | kΩ |
| RKEEPERUP | Keeper-up resistance | 20 | 50 | kΩ |
| RKEEPERDOWN | Keeper-down resistance | 20 | 50 | kΩ |
| IIL | Input low leakage current | – | 5 | μA |
| IIH | Input high leakage current | -5 | – | μA |
^3^ VOL and
VOH are measured at IOL and IOH
respectively, with 12 mA current across min and max voltages and
operating temperatures. For more information regarding possible
drive strength settings, see [Table : Possible drive strength](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__table_zjw_4ms_fgc)
Table : Possible drive strength
| Drive strength | IOL (mA) | IOH (mA) |
| --- | --- | --- |
| 000 | 1.5 | 1.5 |
| 001 | 3.0 | 3.0 |
| 010 | 4.5 | 4.5 |
| 011 | 6.0 | 6.0 |
| 100 | 7.5 | 7.5 |
| 101 | 9.0 | 9.0 |
| 110 | 10.5 | 10.5 |
| 111 | 12.0 | 12.0 |
Note: There is no industry-standard specification for a 1.8 V RGMII interface. Thus, the
above specifications are taken from *JESD8-7A, “1.8 V ± 0.15 V (Normal range) and 1.2 V – 1.95 V (Wide range) Power Supply Voltage and Interface Standard for Non terminated Digital Integrated Circuits”*.
Table : Digital I/O characteristics for UFS_RESET and UFS_REF_CLK
(VDD_PX9/VDD_PX10)
| Parameter | Description | Min | Max | Unit |
| :---: | --- | :---: | :---: | :---: |
| VOL | Low-level output voltage [^4^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_lvf_zms_fgc) | 0 | 0.25 × VDD\_PXx | V |
| VOH | High-level output voltage [^4^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_lvf_zms_fgc) | VDD\_PXx × 0.75 | VDD\_PXx | V |
| RPULL-UP | Pull-up resistance | 20 | 60 | kΩ |
| RPULL-DOWN | Pull-down resistance | 20 | 60 | kΩ |
| ILEAK | Standby leakage | -10 | 10 | µA |
^4^ VOL and
VOH are measured at IOL and IOH
respectively, with 4.8 mA current across min and max voltages and
operating temperatures.
Note: VDD\_PXx can be either VDD\_PX9 or VDD\_PX10.
Table : DC specifications for SPMI (VDD_PX0)
| Parameter | Description | Min | Max | Unit |
| :---: | --- | :---: | :---: | :---: |
| VIH | High-level input voltage | 0.65 × VDD\_PXx | VDD\_PXx + 0.3 | V |
| VIL | Low-level input voltage | -0.3 | 0.35 × VDD\_PXx | V |
| VSHYS | Schmitt hysteresis voltage | 100 | – | mV |
| IIH | Input high leakage current | – | 30 | μA |
| IIL | Input low leakage current | -10 | – | μA |
| Rpullup | Pull-up resistance | 7.5 K | 20 K | Ω |
| Rpulldown | Pull-down resistance | 10 K | 50 K | Ω |
| Rkeeperup | Keeper-up resistance | 7.5 K | 20 K | Ω |
| Rkeeperdown | Keeper-down resistance | 10 K | 50 K | Ω |
| VOH | High-level output voltage, CMOS [^5^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_edx_kns_fgc) | VDD\_PXx - 0.45 | VDD\_PXx | V |
| VOL | Low-level output voltage, CMOS [^5^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_edx_kns_fgc) | 0 | 0.45 | V |
^5^ VOL and VOH are measured at
IOL and IOH respectively, with 12 mA
current across min and max voltages and operating
temperatures.
Table : DC specifications for PS_HOLD and MD_PS_HOLD (VDD_PX3)
| Parameter | Description | Min | Max | Unit |
| :---: | --- | :---: | :---: | :---: |
| VIH | High-level input voltage, (hihys\_en = LOW) | 0.65 × VDD\_PXx | VDD\_PXx + 0.3 V | V |
| VIL | Low-level input voltage, (hihys\_en = LOW) | -0.3 | 0.35 × VDD\_PXx | V |
| VIH | High-level input voltage, (hihys\_en = HIGH) | 0.7 × VDD\_PXx | VDD\_PXx + 0.3 V | V |
| VIL | Low-level input voltage, (hihys\_en = HIGH) | -0.3 | 0.3 × VDD\_PXx | V |
| VSHYS | Schmitt hysteresis, (hihys\_en = LOW) | 100 | – | mV |
| VSHYS | Schmitt hysteresis, (hihys\_en = HIGH) | 300 | – | mV |
| IIH | Input high leakage current | – | 20 | μA |
| IL | Input low leakage current | -1 | – | μA |
| RPD | Pull-down resistance | 10 K | 50 K | Ω |
| RPU | Pull-up resistance | 3 K | 20 K | Ω |
| RKP | Bus keeper resistor | 3 K | 50 K | Ω |
| VOH | High-level output voltage [^6^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_mzp_vns_fgc) | VDD\_PXx - 0.45 | VDD\_PXx | V |
| VOL | Low-level output voltage [^6^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__fn_mzp_vns_fgc) | 0 | 0.45 | V |
^6^ VOL and
VOH are measured at IOL and IOH
respectively, with 12 mA current across min and max voltages and
operating temperatures.
## Timing characteristics
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Specifications for the device timing characteristics are included (where appropriate)
under each function’s section, along with all its other performance specifications. Some
general comments about timing characteristics and pertinent pin design methodologies are
included here.
Note: All QCS9075 devices are characterized with actively terminated
loads; therefore, all baseband timing parameters in this document assume no bus loading.
For more details, see [Rise and fall time specifications](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_yvr_rjw_dbc).
### Timing diagram conventions
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
The conventions used within timing diagrams throughout this document are shown in the
following figure.
Figure : Timing diagram conventions
For each signal in the diagram:
- One clock period (T) extends from one rising clock edge to the next rising clock
edge.
- The high level represents 1, the low level represents 0, and the middle level
represents the floating (high-impedance) state.
- When both the high and low levels are shown over the same time interval, the
meaning depends on the signal type:
- For a bus type signal (multiple bits), the processor or external
interface is driving a value, but that value may or may not be
valid.
- For a single signal, this indicates don’t care.
### Rise and fall time specifications
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
The testers that characterize QCS9075 devices have actively
terminated loads, making the rise and fall times quicker (mimicking a no-load
condition). The impact that different external load conditions have on rise and fall
times is shown in the following diagram.
Figure : Rise and fall times under different load conditions
To account for external load conditions, rise or fall times must be added to the
parameters that start timing at the QCS9075 device and terminate at
an external device (or vice versa). Adding these rise and fall times is equivalent to
applying capacitive load derating factors.
## Memory support
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
QCS9075 supports six channel up to 36 GB LPDDR5 memory (JESD209-5C)
with maximum speed at 3200 MHz.
## Multimedia
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Multimedia parameters requiring performance specifications are addressed in this
section.
### Camera interfaces
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
The QCS9075 device supports up to four D-PHY or C-PHY camera
interfaces.
Table : Supported MIPI-CSI standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| *MIPI Alliance Specification for CSI-2 v3.0* | RAW7 is not supported; DPCM predictor 2 is not supported. |
| *MIPI Alliance Specification for D-PHY v1.2* | Efficient Packet Delimiter (EPD) for D-PHY is not
supported. |
| *MIPI Alliance Specification for C-PHY v1.2* | None |
The following tables summarize the electrical and timing characteristics for CSI C‑PHY
and D‑PHY interfaces at the SoC pin level.
Table : CSI C‑PHY electrical characteristics
| Parameter | Condition | Min | Typ | Max | Unit |
| --- | :---: | :---: | :---: | :---: | :---: |
| Symbol rate per trio | – | – | 4.5 | – | Gsps/trio |
| Equivalent data rate | Per trio | – | 10.26 | – | Gb/s |
| Supported trios | – | 1 | – | 3 | trios |
| Single-ended signal swing | HS mode | TBD | 450 | 535 | mVpp |
| Common-mode voltage | HS mode | 95 | 225 | 390 | mV |
| Intra-trio skew | HS mode | – | – | 5 | ps |
| Inter-trio skew | HS mode | – | – | 30 | ps |
| HS jitter (total) | At max rate | – | – | 0.55 | UI |
| LP input low (VIL) | LP mode | – | – | 550 | mV |
| LP input high (VIH) | LP mode | 740 | – | – | mV |
Table : CSI D‑PHY electrical characteristics
| Parameter | Condition | Min | Typ | Max | Unit |
| --- | :---: | :---: | :---: | :---: | :---: |
| Data rate per lane | HS mode | – | 2.5 | – | Gb/s |
| Supported data lanes | – | 1 | – | 4 | lanes |
| HS differential swing | HS mode | 140 | 200 | 270 | mVpp |
| HS common-mode voltage | HS mode | 70 | – | 330 | mV |
| Receiver sensitivity | HS mode | 40 | – | – | mVpp |
| Intra-pair skew (P–N) | HS mode | – | – | 5 | ps |
| Lane-to-lane skew | HS mode | – | – | 15 | ps |
| HS clock frequency | Dedicated lane | – | 1.25 | – | GHz |
| HS clock jitter (total) | At max rate | – | – | 0.5 | UI |
| HS eye height | HS mode | 140 | – | – | mV |
| LP input high (VIH) | LP mode | – | – | 740 | mV |
| LP input low (VIL) | LP mode | 550 | – | – | mV |
| Hold time | – | 0.3 | – | 0.5 | UI |
| Setup time | – | –0.5 | – | –0.3 | UI |
### Audio support
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
The audio-related interfaces supported with QCS9075 include:
- [I2S interfaces](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#topic.dita_3de50955-32a3-4168-a48e-1a6c300bf0c9)
- [PCM/TDM interfaces](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_knr_3qc_nzb)
### Display support
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
The QCS9075 device supports one D-PHY or C-PHY display.
Table : Supported MIPI-DSI standards and exceptions
| Applicable standard | Feature exceptions |
| --- | :---: |
| *MIPI Alliance Specification for Display Serial Interface 2, v2.1* | None |
| *MIPI Alliance Specification for D-PHY v1.2* | None |
| *MIPI Alliance Specification for C-PHY v1.1* | None |
The following tables summarize the electrical and timing characteristics for DSI C‑PHY
and D‑PHY interfaces at the SoC pin level.
Table : DSI C‑PHY electrical characteristics
| Parameter | Condition | Min | Typ | Max | Unit |
| --- | :---: | :---: | :---: | :---: | :---: |
| Symbol rate per trio | – | – | 2.5 | – | Gsym/s per trio |
| Equivalent data rate | Per trio | – | 5.7 | – | Gb/s |
| Supported trios | – | 1 | – | 3 | trios |
| Static common point voltage | HS mode | 175 | – | 310 | mV |
| Intra-trio skew [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_g4z_cpb_nzb__fn_aqj_jc1_4jc) | HS mode | – | – | 5 | ps |
| Inter-trio skew [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_g4z_cpb_nzb__fn_aqj_jc1_4jc) | HS mode | – | – | 30 | ps |
| HS jitter (total) [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_g4z_cpb_nzb__fn_aqj_jc1_4jc) | at max rate | – | – | 0.3 | UI |
| HS eye height [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_g4z_cpb_nzb__fn_aqj_jc1_4jc) | HS mode | 80 | – | – | mV |
| HS eye width [^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_g4z_cpb_nzb__fn_aqj_jc1_4jc) | HS mode | 0.5 | – | – | UI |
| LP output high (VOH) | LP mode | 0.95 | – | – | V |
| LP output low (VOL) | LP mode | -0.05 | – | 0.05 | V |
^1^ Not characterized; guaranteed
by design
| Parameter | Condition | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| Supported data rates | 2.5, 2.1, 1.312 | 2.5, 2.1, 1.312 | 2.5, 2.1, 1.312 | 2.5, 2.1, 1.312 | Gb/s per lane |
| Data rate per lane | HS mode | – | – | 2.5 | Gb/s |
| Supported data lanes | – | 1 | – | 4 | lanes |
| HS differential swing | HS mode | 140 | 200 | 270 | mVpp |
| HS common-mode voltage | HS mode | 0.15 | 0.2 | 0.25 | V |
| Intra-pair skew (P–N) [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_g4z_cpb_nzb__fn_p1f_dc1_4jc) | HS mode | – | – | 5 | ps |
| Lane-to-lane skew [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_g4z_cpb_nzb__fn_p1f_dc1_4jc) | HS mode | – | – | 15 | ps |
| HS jitter (total) [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_g4z_cpb_nzb__fn_p1f_dc1_4jc) | at max rate | – | – | 0.3 | UI |
| HS eye height [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_g4z_cpb_nzb__fn_p1f_dc1_4jc) | HS mode | 80 | – | – | mV |
| HS data rise time | HS mode | – | – | 160 | ps |
| HS data fall time | HS mode | – | – | 160 | ps |
| HS clock rise time | HS mode | – | – | 160 | ps |
| HS clock fall time | HS mode | – | – | 160 | ps |
| LP output high (VOH) | LP mode | 0.95 | – | 1.3 | V |
| LP output low (VOL) | LP mode | -0.05 | – | 0.05 | V |
| LP input high (VIH) | LP mode | 740 | – | – | mV |
| LP input low (VIL) | LP mode | – | – | 550 | mV |
| LP Tx rise time | LP mode | – | – | 25 | ns |
| LP Tx fall time | LP mode | – | – | 25 | ns |
^2^ Not characterized;
guaranteed by design
### DisplayPort
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Table : Supported DisplayPort standards and exceptions
| Applicable standard | Feature exceptions |
| --- | :---: |
| *VESA DisplayPort v1.4* | None |
The following table summarizes the key electrical and link characteristics for the
DisplayPort and embedded DisplayPort (eDP) interface.
Table : DP/eDP electrical and link characteristics
| Parameter | Min | Typ | Max | Unit |
| --- | :---: | :---: | :---: | :---: |
| Main link lane count | 1 | 2 | 4 | lanes |
| Main link per-lane rate (DP 1.4) | 1.612 | – | 8.1 | Gbps/lane |
| Encoding/clocking | – | 8b/10b | – | – |
| Total raw bandwidth (4 lanes) | – | – | 32.4 | Gbps |
| AUX channel data rate | – | 1 | – | Mbps |
| AUX differential peak-to-peak voltage (DP) | 0.29 | – | 1.38 | Vpp (diff) |
| AUX differential peak-to-peak voltage (eDP) | 0.14 | – | 1.36 | Vpp (diff) |
| AUX AC-coupling capacitance | 75 | 100 | 200 | nF |
## Connectivity
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
The connectivity functions supported by the QCS9075 that require
electrical specifications include:
- USB host/slave support with built-in physical layer (PHY)
- Peripheral component interconnect express (PCIe) interfaces
- Universal flash storage (UFS)
- NOR flash storages (OSPI/QSPI)
- Reduced gigabit media independent interface (RGMII)
- High-speed serial gigabit media-independent interface (HSGMII)
- Inter-IC sound (I^2^S) interfaces
- Pulse-coded modulation (PCM) interfaces
- Time-division multiplexing (TDM) interfaces
- Through proper configuration of 21main domain (MD) GPIO-based QUP SEs and
5 RTSS domain RTSS\_IO- based QUP SEs:
- Universal asynchronous receiver/transmitter (UART) ports
- Inter-integrated circuit (I^2^C) interfaces
- Serial peripheral interface (SPI) ports
- Dedicated I^2^C interfaces for camera (CCI I^2^C)
Pertinent specifications for these functions are detailed in the following
subsections.
Note: In addition to the following hardware specifications, see the
latest software release notes for software- based performance features or
limitations.
### USB interfaces
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Table : Supported USB standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| *Universal Serial Bus Specification, Revision 3.1 (August11, 2014 or later)* | None |
| *UTMI specification version 1.05, released on 3/29/2001* | None |
| *On-The-Go and Embedded Host Supplement to the USB 3.0 Specification (May 10, 2012, Revision 1.1 or later)* | Attach detection protocol (ADP), role swap protocol (RSP), session
request protocol (SRP), and host negotiation protocol (HNP) |
| *USB Serial Bus Specification, Revision 2.0 (April 27, 2000 or later)* | None |
The following table summarizes the SuperSpeed USB electrical and timing characteristics
for Gen1 and Gen2 operation at the SoC pin level.
Table : USB SuperSpeed electrical characteristics
| Parameter | Min | Typ | Max | Unit |
| --- | :---: | :---: | :---: | :---: |
| Supported generation | – | Gen1, Gen2 | – | – |
| Signaling rate (Gen1) | – | 5 | – | Gb/s |
| Signaling rate (Gen2) | – | 10 | – | Gb/s |
| Unit interval (Gen1) | 199.94 | 200 | 200.065 | ps |
| Unit interval (Gen2) | 99.97 | 100 | 100.0325 | ps |
| Differential output voltage | 800 | 900 | 1200 | mVpp-diff |
| Tx rise / fall time (Gen1) | 20 | – | 80 | ps |
| Tx rise / fall time (Gen2) | 10 | – | 50 | ps |
| Differential output impedance | 70 | 90 | 110 | Ω |
| Intra-pair skew (P–N) | – | – | 5 | ps |
| Lane-to-lane skew | – | – | 70 | ps |
| Tx total jitter (Gen1) | – | – | 132 | ps |
| Tx total jitter (Gen2) | – | – | 67 | ps |
| Rx eye height (Gen2) | 0.07 | – | – | mV |
| Rx eye height (Gen1) | 0.1 | – | – | mV |
Note:
- Compliant with USB‑IF USB 3.1/USB 3.2 specifications for SuperSpeed
operation.
- Table applies to SuperSpeed differential pairs (Tx/Rx); USB 2.0 D+/D− signaling
is specified separately.
- SuperSpeed signaling uses embedded clocking; an external reference clock is
required only for PHY PLL operation.
- Differential routing requirement: 90 Ω ± 10% impedance, with strict control of
intra‑pair and inter‑pair skew.
- AC coupling capacitors are required on Tx SuperSpeed lanes and should be placed
near SoC pins.
- Supports LFPS‑based power management including U1, U2, and U3 states.
- All parameters apply across recommended voltage and temperature range unless
otherwise stated.
The following table summarizes the high-speed USB electrical and timing characteristics
at the SoC pin level.
Table : USB high-speed electrical characteristics
| Parameter | Condition | Min | Typ | Max | Unit |
| --- | --- | :---: | :---: | :---: | :---: |
| Signaling rate | High-speed mode | 479.76 | 480 | 480.24 | Mb/s |
| Unit interval (UI) | at 480 Mb/s | – | 2.083 | – | ns |
| Differential output voltage (high) | HS driver | 360 | 400 | 440 | mVpp |
| Differential output voltage (low) | HS driver | – | – | 10 | mVpp |
| Differential interface impedance | Link (cable + termination) | 76.5 | 90 | 103.5 | Ω |
| Termination resistance (per line) | HS mode | 40.5 | 45 | 49.5 | Ω |
| Differential receiver sensitivity | Receiver | 200 | – | – | mV |
| Differential common-mode range | HS signaling | 0.8 | – | 2.5 | V |
| Rise time (10–90%) | Signal edge | 0.5 | – | – | ns |
| Fall time (10–90%) | Signal edge | 0.5 | – | – | ns |
| Chirp K/J width | HS detection | 40 | – | 60 | µs |
| Chirp J level (differential) | HS driver | 700 | – | 1100 | mV |
| Chirp K level (differential) | HS driver | –900 | – | –500 | mV |
| Bus pull-up (upstream port) | – | 1.425 | – | 1.575 | kΩ |
| Bus pull-down (downstream port) | – | 14.25 | – | 15.75 | kΩ |
Note:
- Compliant with the USB 2.0 high-speed specification (480 Mb/s); values reflect
SoC pin-level electrical and timing characteristics
- High-speed signaling uses bit-stuffed NRZI encoding with differential D+ and D-
signaling
- High-speed operation requires chirp signaling during reset for speed negotiation
with downstream devices
- No external reference clock is required; clock is recovered from the data
stream
- Differential impedance target is 90 Ω ± 10%; tight control of D+ and D– skew is
recommended for margin
- On-die series termination is assumed unless otherwise specified in the hardware
design guide
- All specifications apply across recommended operating voltage and temperature
unless otherwise noted
### PCIe interface
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
| Applicable standard | Feature exceptions |
| --- | --- |
| *PCI Express Base Specification Revision 4.0* | Link configure capability |
| *PCI Express Base Specification Revision 4.0* | Lane margining at receiver |
| *PCI Express Base Specification Revision 4.0* | L0s link state |
| | |
| | |
The following table summarizes the electrical and timing characteristics for the
high-speed serial interface operating at Gen4 and Gen3 data rates. The parameters
represent SoC pin-level requirements across supported operating conditions.
| Parameter | Gen4 | Gen4 | Gen4 | Gen3 | Gen3 | Gen3 | Unit |
| --- | --- | --- | --- | --- | --- | --- | --- |
| Parameter | Min | Typ | Max | Min | Typ | Max | Unit |
| Signaling rate | – | – | 16 | – | – | 8 | GT/s |
| Unit interval (UI) | 62.48 | 62.5 | 62.64 | 124.96 | 125 | 125.28 | ps |
| Differential voltage (Tx) | 600 | – | 1200 | 800 | – | 1200 | mVpp-diff |
| Single-ended swing (Tx) | 300 | – | 600 | 400 | – | 600 | mVpp |
| Tx common-mode voltage | 0.7 | – | 0.9 | 0.7 | – | 0.9 | V |
| Differential output impedance | 80 | – | 120 | 80 | – | 120 | Ω |
| Receiver input sensitivity | 30 | – | – | 85 | – | – | mV |
| AC coupling capacitance | 75 | 100 | 200 | 75 | 100 | 200 | nF |
| Intra-pair skew (P–N) | – | – | 5 | – | – | 20 | ps |
| Lane-to-lane skew | – | – | 20 | – | – | 50 | ps |
| Tx total jitter (TJ) | – | – | 15.85 | – | – | 33.83 | ps |
| REFCLK frequency | 99.8 | 100 | 100.2 | 99.8 | 100 | 100.2 | MHz |
| REFCLK duty cycle | 45 | 50 | 55 | 45 | 50 | 55 | % |
| REFCLK RMS jitter (no SSC) | – | – | 1 | – | – | 1 | ps |
| REFCLK peak-to-peak jitter | – | – | 10 | – | – | 10 | ps |
| Spread spectrum clocking (down spread) | -0.5 | -0.3 | 0 | -0.5 | -0.3 | 0 | % |
| PERST# assertion width | 100 | – | – | 100 | – | – | ms |
| PERST# deassertion to LTSSM | 2 | – | – | 2 | – | – | ms |
| Receiver detect voltage | 200 | – | 600 | 200 | – | 600 | mV |
| Receiver detect resistance | 40 | – | 60 | 40 | – | 60 | Ω |
| | | | | | | | |
### UFS interface
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Table : Supported UFS standards and exceptions
| Applicable standard | Feature exceptions |
| --- | :---: |
| *Universal Flash Storage (UFS), Version 3.1* | None |
### HSGMII interface
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Table : Supported HSGMII standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| *IEEE 802.3 section 47* | None |
The following tables summarize the SoC pin-level electrical and timing characteristics
for SGMII operation at *3.125 Gbps* and *1.25 Gbps*.
Table : SGMII characteristics at 3.125 Gbps
| Parameter | Min | Typ | Max | Unit |
| --- | :---: | :---: | :---: | :---: |
| Supported link speed | – | – | 2500 | Mb/s |
| Line coding | – | 8b/10b | – | – |
| Serial line rate | – | 3.125 | – | Gb/s |
| Unit interval (UI) | – | 320 | – | ps |
| Tx rise/fall time | 60 | – | 130 | ps |
| Intra-pair skew (P–N) | – | – | 15 | ps |
| Lane-to-lane skew | – | – | 100 | ps |
| Tx total jitter (TJ) | – | – | 0.35 | UI |
| Tx random jitter (RJ, RMS) | – | – | 0.18 | UI |
| Tx deterministic jitter | – | – | 0.17 | UI |
| Tx duty cycle distortion (DCD) | – | – | 2 | % |
| Rx eye height | 200 | – | – | mV |
| Rx eye width | 0.35 | – | – | UI |
Table : SGMII characteristics at 1.25 Gbps
| Parameter | Min | Typ | Max | Unit |
| --- | :---: | :---: | :---: | :---: |
| Supported link speed | – | – | 1000 | Mb/s |
| Line coding | – | 8b/10b | – | – |
| Serial line rate | – | 1.25 | – | Gb/s |
| Unit interval (UI) | – | 800 | – | ps |
| Tx rise/fall time | 100 | – | 200 | ps |
| Intra-pair skew (P–N) | – | – | 20 | ps |
| Lane-to-lane skew | – | – | 100 | ps |
| Tx total jitter (TJ) | – | – | 0.30 | UI |
| Tx random jitter (RJ, RMS) | – | – | 0.20 | UI |
| Tx deterministic jitter | – | – | 0.10 | UI |
| Rx eye height | 100 | – | – | mV |
| Rx eye width | 0.35 | – | – | UI |
Note:
- Compliant with SGMII specification and IEEE 802.3 (1000BASE-X PCS/PMA)
- Uses 8b/10b encoding with a fixed 1.25 Gb/s serial line rate, independent of
negotiated link speed
- Clock is embedded in the serial data stream; an optional 25 MHz reference clock
may be used for PLL operation, depending on the SoC implementation
- Differential routing requires controlled impedance of 100 Ω ± 10% with tight
control of intra-pair skew
- Auto-negotiation supports 10/100/1000 Mb/s operation over a single differential
pair
- AC coupling is required on Tx differential signals unless otherwise specified in
the platform design
- Specifications apply across recommended operating voltage and temperature unless
otherwise noted
### Secured digital interfaces
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
The supported secure digital (SD) interface standards and their exceptions are listed
here.
Table : Supported SD standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *MultiMediaCard Host Specification version 5.1* | None |
| *Secure Digital: Physical Layer Specification version 3.0* | None |
| *SDIO Card Specification version 3.0* | None |
| Function | Bits | I/O voltage | Vector name | Frequency |
| --- | --- | --- | --- | --- |
| eMMC | 8 | 1.8 V | HS400 | 192 MHz |
| eMMC | 8 | 1.8 V | HS200 | 192 MHz |
| eMMC | 8 | 1.8 V | HSSDR (SDR25) | 52 MHz |
| eMMC | 8 | 1.8 V | HSDDR (DDR50) | 52 MHz |
| SD | 4 | 1.8 V | SDR50 | 100 MHz |
| | | | | |
| | | | | |
| | | | | |
Figure : Single data rate – SDR mode
Figure : Double data rate – DDR mode
Figure : HS400 mode input timing
Figure : HS400 mode output timing
| SDCC modes | Frequency | Parameter | Description | Minimum (ns) | Maximum (ns) |
| --- | --- | --- | --- | --- | --- |
| HS400
(DDR 200 MHz) | 192 MHz | Tclhigh | Clock high time | 2.3437 | 2.8646 |
| HS400
(DDR 200 MHz) | 192 MHz | tRQ | DQS to DQ valid setup | 0.4 | – |
| HS400
(DDR 200 MHz) | 192 MHz | tRQH | DQS to DQ valid hold | 0.4 | – |
| HS400
(DDR 200 MHz) | 192 MHz | tCIDV | Command input valid window | 2.4 | – |
| HS400
(DDR 200 MHz) | 192 MHz | tCODLY | Command output delay | -1.45 | 0.85 |
| HS400
(DDR 200 MHz) | 192 MHz | tIDV | Data input valid window | 1.7 | – |
| HS400
(DDR 200 MHz) | 192 MHz | tODLY | Data output delay | 0.4 | 1.85 |
| HS200
(SDR 200 MHz) | 192 MHz | Tclhigh | Clock high time | 2.3437 | 2.8646 |
| HS200
(SDR 200 MHz) | 192 MHz | tCIDV | Command input valid window | 2.4 | – |
| HS200
(SDR 200 MHz) | 192 MHz | tCODLY | Command output delay | -1.45 | 0.85 |
| HS200
(SDR 200 MHz) | 192 MHz | tIDV | Data input valid window | 1.7 | – |
| HS200
(SDR 200 MHz) | 192 MHz | tODLY | Data output delay | -1.45 | 0.85 |
| HSDDR
(DDR 50) | 52 MHz | Tclhigh | Clock high time | 9 | 11 |
| HSDDR
(DDR 50) | 52 MHz | tCIS | Command input setup | 6.3 | – |
| HSDDR
(DDR 50) | 52 MHz | tCIH | Command input hold | 1.5 | – |
| HSDDR
(DDR 50) | 52 MHz | tCODLY | Command output delay | -8.2 | 3 |
| HSDDR
(DDR 50) | 52 MHz | tIS | Data input setup | 2 | – |
| HSDDR
(DDR 50) | 52 MHz | tIH | Data input hold | 1.5 | – |
| HSDDR
(DDR 50) | 52 MHz | tODLY | Data output delay | 0.8 | 6 |
| HSSDR
(SDR25) | 52 MHz | Tclhigh | Clock high time | 9 | 11 |
| HSSDR
(SDR25) | 52 MHz | tCIS | Command input setup | 6.3 | – |
| HSSDR
(SDR25) | 52 MHz | tCIH | Command input hold | 1.5 | – |
| HSSDR
(SDR25) | 52 MHz | tCODLY | Command output delay | -8.2 | 3 |
| HSSDR
(SDR25) | 52 MHz | tIS | Data input setup | 2 | – |
| HSSDR
(SDR25) | 52 MHz | tIH | Data input hold | 1.5 | – |
| HSSDR
(SDR25) | 52 MHz | tODLY | Data output delay | -3.7 | 1.5 |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| SDCC modes | Frequency | Parameter | Description | Minimum (ns) | Maximum (ns) |
| --- | --- | --- | --- | --- | --- |
| SDR 50 | 100 MHz | Tclhigh | Clock high time | T\*0.45 | T\*0.45 |
| SDR 50 | 100 MHz | tCIS | Command input setup | 2.5 | – |
| SDR 50 | 100 MHz | tCIH | Command input hold | 1.5 | – |
| SDR 50 | 100 MHz | tCODLY | Command output delay | -3.7 | 1.5 |
| SDR 50 | 100 MHz | tIS | Data input setup | 2.5 | – |
| SDR 50 | 100 MHz | tIH | Data input hold | 1.5 | – |
| SDR 50 | 100 MHz | tODLY | Data output delay | -3.7 | 1.5 |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
### Octa-SPI/Quad-SPI interface
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Figure : Octa-SPI/Quad-SPI SDR timing diagram
Table : Octa-SPI/Quad-SPI interface SDR timing
| Parameter | Comments | Min. | Max. | Unit |
| --- | --- | :---: | :---: | :---: |
| 1/T | OSPI/QSPI clock frequency | – | 90 | MHz |
| t(mis) | Master input setup time | 1.7 | – | ns |
| t(mih) | Master input hold time | 1.3 | – | ns |
| t(mod) | Master output delay | -2.00 | 2.00 | ns |
Figure : Octa-SPI DDR timing diagram
Table : Octa-SPI interface DDR timing
| Parameter | Comments | Min. | Max. | Unit |
| :---: | --- | --- | --- | --- |
| 1/T | OSPI clock frequency | – | 166 | MHz |
| t(skew) | DQ to DQS skew | – | 530 | ps |
| t(mod) | Master output delay | -2.00 | 2.00 | ns |
Note: DDR is not supported on Quad-SPI operation.
### RGMII interface
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Table : Supported RGMII standards and exceptions
| Applicable standard | Feature exceptions |
| --- | :---: |
| *Reduced Gigabit Media Independent Interface (RGMII) v1.3 and v2.0* | None |
| Parameter | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- |
| Supported speeds | 10/100/1000 | 10/100/1000 | 10/100/1000 | Mb/s |
| Reference clock (TXC/RXC) | 2.5/25/125 | 2.5/25/125 | 2.5/25/125 | MHz |
| Data transfer | DDR at 1000 Mbps only | DDR at 1000 Mbps only | DDR at 1000 Mbps only | DDR at 1000 Mbps only |
| **Signal electrical levels (CMOS)** | **Signal electrical levels (CMOS)** | **Signal electrical levels (CMOS)** | **Signal electrical levels (CMOS)** | **Signal electrical levels (CMOS)** |
| I/O supply voltage (VDDIO) | 1.7 | 1.8 | 1.9 | V |
| Input high voltage (VIH) | 0.65 × VDD\_PXx | — | VDD\_PXx + 0.3 | V |
| Input low voltage (VIL) | -0.3 | — | 0.35 × VDD\_PXx | V |
| Output high voltage (VOH) | VDD\_PXx - 0.45 | — | — | V |
| Output low voltage (VOL) | — | — | 0.45 | V |
| **Timing (1000BASE‑T)** | **Timing (1000BASE‑T)** | **Timing (1000BASE‑T)** | **Timing (1000BASE‑T)** | **Timing (1000BASE‑T)** |
| TXD setup time | 1.2 | — | — | ns |
| TXD hold time | 1.2 | — | — | ns |
| RXD setup time | 1 | — | — | ns |
| RXD hold time | 1 | — | — | ns |
| Clock duty cycle | 45 | 50 | 55 | % |
| **Management interface (MDIO/MDC)** | **Management interface (MDIO/MDC)** | **Management interface (MDIO/MDC)** | **Management interface (MDIO/MDC)** | **Management interface (MDIO/MDC)** |
| MDC clock frequency | — | 2.5 | | MHz |
| Input high voltage (VIH) | 0.65 × VDD\_PXx | — | VDD\_PXx + 0.3 | |
| Input low voltage (VIL) | -0.3 | — | 0.35 × VDD\_PXx | |
| Output high voltage (VOH) | VDD\_PXx - 0.45 | — | — | V |
| Output low voltage (VOL) | — | — | 0.45 | V |
Figure : MDIO sourced by PHY
When the MDIO signal is sourced by the PHY, it is sampled by the SoC synchronous to the
rising edge of MDC. The clock-to-output delay from the PHY shall be a minimum of 0 ns
and a maximum of 300 ns.
Figure : MDIO sourced by SoC
When the SoC sources the MDIO signal, it shall provide a minimum setup time of 10 ns and
a minimum hold time of 10 ns, referenced to the rising edge of MDC.
Figure : RGMII Tx and Rx timing
### I^2^S interfaces
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Table : Supported I2S standards and exceptions
| Applicable standards | Feature exceptions |
| --- | :---: |
| *Philips I*^*2*^*S Bus Specifications*
revised June 5, 1996 | None |
Figure : I^2^S timing diagram
| Parameter | Parameter | Comments[^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_1_i2s-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** |
| Frequency | Frequency | | – | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(sr) | SD and WS input setup time | | 8.14 | – | – | ns |
| t(hr) | SD and WS input hold time | | 1.5 | – | – | ns |
| t(dtr) | SD and WS output delay | | – | – | 8.14 | ns |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** |
| Frequency | Frequency | | – | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(sr) | SD and WS input setup time | | 8.14 | – | – | ns |
| t(hr) | SD and WS input hold time | | 1.5 | – | – | ns |
| t(dtr) | SD and WS output delay | | – | – | 8.14 | ns |
[^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_1_i2s-interfaces) Load capacitance is between 10 pF and
40 pF.
| Parameter | Parameter | Comments[^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_2_i2s-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** |
| | Frequency | | | – | 73.728 | MHz |
| T | Clock period | | 13.56 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(sr) | SD and WS input setup time | | 2.71 | – | – | ns |
| t(hr) | SD and WS input hold time | | 1.5 | – | – | ns |
[^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_2_i2s-interfaces) Load capacitance is between 10 pF and
40 pF.
| Parameter | Parameter | Comments[^3^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_3_i2s-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** |
| | Frequency | | | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(dtr) | SD and WS output delay | | – | – | 8.14 | ns |
[^3^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_3_i2s-interfaces) Load capacitance is between 10 pF and 40 pF.
### PCM/TDM interfaces
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Figure : PCM/TDM audio format with different sync modes
Figure : PCM/TDM timing diagram
| Parameter | Parameter | Comments | Min | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** |
| Frequency | Frequency | | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | ns |
| t(HC) | Clock high | | 0.45× T | 0.55× T | ns |
| t(LC) | Clock low | | 0.45× T | 0.55× T | ns |
| t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | | 8.14 | – | ns |
| t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | | 1.5 | – | ns |
| t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC output delay | | – | 8.14 | ns |
| ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** |
| Frequency | Frequency | | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | ns |
| t(HC) | Clock high | | 0.45× T | 0.55× T | ns |
| t(LC) | Clock low | | 0.45× T | 0.55× T | ns |
| t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | | 8.14 | – | ns |
| t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | | 1.5 | – | ns |
| t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC output delay | | – | 8.14 | ns |
^1^ Load
capacitance is between 10 pF to 40 pF.
| Parameter | Parameter | Comments[^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_2_pcm-tdm-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** |
| | Frequency | | | – | 73.728 | MHz |
| T | Clock period | | 13.56 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | | 2.71 | – | – | ns |
| t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | | 1.5 | – | – | ns |
[^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_2_pcm-tdm-interfaces) Load capacitance is between 10 pF and
40 pF.
| Parameter | Parameter | Comments[^3^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_3_pcm-tdm-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** |
| | Frequency | | | – | 24.576 | MHz |
| T | Clock period | | 40.69 | – | – | ns |
| t(HC) | Clock high | | 0.45 × T | – | 0.55 × T | ns |
| t(LC) | Clock low | | 0.45 × T | – | 0.55 × T | ns |
| t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC delay | | – | – | 8.14 | ns |
[^3^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_3_pcm-tdm-interfaces) Load capacitance is between 10 pF and
40 pF.
### I^2^C interface
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Table : Supported I2C standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| *I^2^C Specification, version 3.0* | HS mode, slave mode, multi-master mode, and 10‑bit addressing are not
supported. |
### Serial peripheral interface
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
The QCS9075 supports SPI as a master on 25 QUP ports. SPI slave mode
is supported on the eight QUP ports. See [QCS9075 Pin Assignment and
GPIO Configuration Spreadsheet (80-73417-1A)](https://docs.qualcomm.com/bundle/80-73417-1A/resource/80-73417-1A.xlsm) for more details.
Figure : SPI master timing diagram
Note: Depending on the mode configuration (Clock PHA and POL settings), Tx and Rx
sampling edge could differ. The timing diagram above is using mode 1 as an
example
Table : SPI master timing characteristics
| Parameter | Comments | Min | Typ | Max | Unit |
| --- | --- | :---: | :---: | :---: | :---: |
| T(SPI clock period)[^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fntarg_1_serial-peripheral-interface) | 50 MHz maximum | 20 | – | – | ns |
| t(ch) | Clock high | 8 | – | – | ns |
| t(cl) | Clock low | 8 | – | – | ns |
| t(mov) | Master output valid | -5 | – | 5 | ns |
| t(mis) | Master input setup | 5 | – | – | ns |
| t(mih) | Master input hold | 1 | – | – | ns |
[^1^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#fnsrc_1_serial-peripheral-interface) The minimum clock period includes 1%
jitter of maximum frequency.
Table : SPI slave timing characteristics
| Parameter | Comments | Min | Max | Unit |
| --- | --- | :---: | :---: | :---: |
| T (SPI clock period) [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_gcp_tsc_nzb__fn_zpt_xtc_nzb_radhikav_11-21-23-1608-6-867) | 50 MHz maximum | 20.0 | – | ns |
| t(ch) | Clock high | 9 | – | ns |
| t(cl) | Clock low | 9 | – | ns |
| t(sov) | Slave output valid | 2 | 13 | ns |
| t(mis) | Slave input setup | 3 | – | ns |
| t(mih) | Slave input hold | 3 | – | ns |
| S\_TRI\_STATE\_EN [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_gcp_tsc_nzb__fn_zpt_xtc_nzb_radhikav_11-21-23-1608-6-867) | Slave tri-state enable | – | 14 | ns |
| S\_TRI\_STATE\_DIS [^2^](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_gcp_tsc_nzb__fn_zpt_xtc_nzb_radhikav_11-21-23-1608-6-867) | Slave tri-state disable | – | 14 | ns |
^2^ The total
capacitive load must not exceed 30 pF for a single slave system.
For each additional slave, 10 pF should be added to the clock
and data lines (not needed for chip select since it is
one-to-one). For example, 40 pF for two slaves, although most
systems have only a single slave. Care must be taken to verify
that every slave can drive the data line fast enough to meet the
timing requirement or the system must use a reduced
frequency.
Note: Only SPI slave mode 1 (PHA = 1 and POL = 0) is supported.
### CAN-FD-interface
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
QCS9075 supports up to eight CAN-FD interfaces multiplexed through RTSS\_IOs in the RTSS
domain.
For voltage characteristics, see [Table : DC specification of 1.8 V I/Os](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb__table_ymd_mfb_nzb_radhikav_11-21-23-1100-3-596). CAN-FD supports data rates up to 10 Mbps. For information on
supported lower data rates, contact QTI.
Table : Supported CAN-FD standards and exceptions
| Applicable standard | Feature exception |
| --- | :---: |
| *ISO 11898-1: 2015, Road vehicles, Controller area network (CAN)* | None |
| *ISO 11898-4, Road vehicles, Controller area network (CAN)* | None |
## Internal functions
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Some internal functions require external interfaces to enable their operation. These
include modes and resets, and JTAG functions.
### Modes and resets
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Mode and reset functions are basic digital I/Os that meet the performance specifications
presented in [Digital logic characteristics](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html#concept_hmf_cdb_nzb).
### JTAG
Source: [https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73417-1/topic/electrical-specifications.html)
Figure : JTAG interface timing diagram
| Parameter | Parameter | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| t(tckcy) | TCK period | 50 | – | – | ns |
| t(tckh) | TCK pulse width high | 20 | – | – | ns |
| t(tckl) | TCK pulse width low | 20 | – | – | ns |
| t(sutms) | TMS input setup time | 5 | – | – | ns |
| t(htms) | TMS input hold time | 20 | – | – | ns |
| t(sutdi) | TDI input setup time | 5 | – | – | ns |
| t(htdi) | TDI input hold time | 20 | – | – | ns |
| t(do) | TDO data output delay | – | – | 15 | ns |
| t(tckcy) | TCK period | 50 | – | – | ns |
Last Published: Jun 30, 2026
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