# Carrier, storage, and handling information
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html)
This topic discusses shipping, storage, and handling of this chipset.
## Tape and reel information
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html)
All QTI tape carrier systems conform to EIA-481 standards.
The following figure shows the simplified sketch of the QCS615
chipsets tape carrier including the part orientation, maximum number of devices per reel, and
key dimensions.
Figure : Carrier tape drawing with part orientation
The following figure shows the tape-handling recommendation.
Figure : Tape handling
## Matrix tray information
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html)
All matrix tray media is available for sampling only. All QTI matrix tray carriers conform to
JEDEC standards.
The device pin 1 is oriented to the chamfered corner of the matrix tray. Each tray of the
QCS615 contains up to 60 devices. Production orders of the QCS615 that are shipped in matrix
tray carriers will be in 5 + 1 tray stacks of 300 units. The stacking configuration and
quantity for sample orders will vary.
The following table lists the key dimensions:
Table : Matrix tray key dimensions
| Array | Key dimensions |
| :---: | :---: |
| M | 16.95 |
| M1 | 17.25 |
| M2 | 25.50 |
| M3 | 25.50 |
The following figure shows the matrix tray orientation.
Figure : Matrix tray orientation
## Device moisture sensitivity level
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html)
Plastic-encapsulated surface-mount packages are susceptible to damage induced by absorbed moisture and high temperature. A moisture sensitivity level (MSL) indicates the ability for a package to withstand exposure after it is removed from its shipment bag before PCB installation. A low MSL rating is better than a high rating; a low MSL device is exposed longer than a high MSL device. The following table summarizes all pertinent MSL ratings:
Table : MSL ratings summary
| MSL | Out-of-bag floor life | Comments |
| :---: | --- | --- |
| 1 | Unlimited | ≤ 30°C/85% RH |
| 2 | 1 year | ≤ 30°C/60% RH |
| 2a | 4 weeks | ≤ 30°C/60% RH |
| 3 | 168 hours | ≤ 30°C/60% RH;
**QCS615 rating** |
| 4 | 72 hours | ≤ 30°C/60% RH |
| 5 | 48 hours | ≤ 30°C/60% RH |
| 5a | 24 hours | ≤ 30°C/60% RH |
| 6 | Mandatory bake before use. After baking, it must be reflowed within the time limit specified on the label. | ≤ 30°C/60% RH |
QTI follows the latest IPC/JEDEC J-STD-020 standard revision for moisture-sensitivity qualification. ***The QCS615 devices are classified as MSL3; the qualification temperature was 255ºC.*** Do not confuse this qualification temperature (255°C) with the peak temperature within the recommended solder reflow profile.
## Bagged storage conditions
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html)
QCS615 devices delivered in tape and reel carriers must be stored
in sealed, moisture barrier, antistatic bags. For the expected shelf life, see [IC Products Packing Method (80-VK055-1)](https://docs.qualcomm.com/bundle/80-VK055-1/resource/80-VK055-1.pdf).
## Out-of-bag duration
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html)
The out-of-bag duration is the time that a device can be exposed before being installed onto
a PCB.
## Handling
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html)
Tape handling is described in [Tape and reel information](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html#flb1612799320214). For other (IC-specific) handling guidelines, see the following topics.
### Baking
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html)
It is not necessary to bake the QCS615 chipsets if the conditions
specified in [Bagged storage conditions](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html#tjl1612799429370) and
[Out-of-bag duration](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html#lhf1612799619746) have not **been exceeded**.
It is necessary to bake the QCS615 chipsets if any condition
specified in [Bagged storage conditions](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html#tjl1612799429370) or [Out-of-bag duration](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html#lhf1612799619746) has **been exceeded**. The
baking conditions are specified on the moisture-sensitive caution label attached to each bag.
For more details, see [IC Products Packing Method (80-VK055-1)](https://docs.qualcomm.com/bundle/80-VK055-1/resource/80-VK055-1.pdf).
**CAUTION**: If baking is required, the devices must be transferred into trays that can be
baked to at least 125°C. Do not bake devices in tape and reel carriers at any temperature.
### Electrostatic discharge
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html)
Electrostatic discharge (ESD) occurs naturally in laboratory and factory environments. An established high-voltage potential is always at risk of discharging to a lower potential. If this discharge path is through a semiconductor device, destructive damage may result.
ESD counter measures and handling methods must be developed and used to control the factory environment at each manufacturing site.
QTI products must be handled according to the ESD Association standard: ANSI/ESD S20.20-1999, Protection of Electrical and Electronic Parts, Assemblies, and Equipment.
## Bar code label and packing for shipment
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html](https://docs.qualcomm.com/doc/80-73480-1/topic/carrier-storage-and-handling-information.html)
For all packing-related information, including bar code label details, see [IC Products Packing Method (80-VK055-1)](https://docs.qualcomm.com/bundle/80-VK055-1/resource/80-VK055-1.pdf).
Last Published: Mar 09, 2026
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