# Electrical specifications
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
This topic defines the device electrical performance specifications, including absolute
maximum ratings, operating conditions, and subsystem (such as memory and connectivity)
parameters, which are useful in deploying the device with optimal processing capabilities and
high efficiency.
## Absolute maximum ratings
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
Do not exceed the absolute maximum ratings mentioned in [Table : Absolute maximum ratings](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#jbz1612763758912__table_u21_rls_qpb).
**WARNING:** If ratings are exceeded, this may cause permanent damage to the device.
Functionality and reliability are guaranteed only within the conditions described in [Operating conditions](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#rkh1612768256411).
| Power supply | Description | Min | Max | Unit |
| --- | --- | --- | --- | --- |
| VDD\_APC0 | Kryo Silver application processor | -0.3 | 1.17 | V |
| VDD\_APC1 | Kryo Gold application processor | -0.3 | 1.17 | V |
| VDDCX | Digital core circuits | -0.3 | 1.17 | V |
| VDDA\_CSI0\_1P2 | MIPI CSI0 1.2 V circuits | -0.3 | 1.39 | V |
| VDDA\_CSI1\_1P2 | MIPI CSI1 1.2 V circuits | -0.3 | 1.39 | V |
| VDDA\_CSI2\_1P2 | MIPI CSI2 1.2 V circuits | -0.3 | 1.39 | V |
| VDDA\_DSI0\_1P2 | MIPI DSI0 1.2 V circuits | -0.3 | 1.39 | V |
| VDDA\_DSI0\_PLL | MIPI DSI0 PLL 1.2 V circuits | -0.3 | 1.39 | V |
| VDDA\_PLL\_HV\_CC\_EBI | EBI high-voltage circuits | -0.3 | 1.39 | V |
| VDDA\_DSI0\_0P9 | MIPI DSI0 0.9 V circuits | -0.3 | 1.07 | V |
| VDDA\_USB0\_HS\_0P9 | USB0 high-speed (HS) 0.9 V circuits | -0.3 | 1.07 | V |
| VDDA\_USB1\_HS\_0P9 | USB1 high-speed (HS) 0.9 V circuits | -0.3 | 1.07 | V |
| VDDA\_USB\_SS\_DP\_CORE | USB1 SS and DisplayPort core circuits | -0.3 | 1.07 | V |
| VDDA\_UFS\_CORE | UFS core circuits | -0.3 | 1.07 | V |
| VDDA\_EBI\_PLL | EBI0/EBI1 PLL circuits | -0.3 | 1.07 | V |
| VDDA\_PCIE\_CORE | PCIe core circuits | -0.3 | 1.07 | V |
| VDDA\_QREFS\_1P25 | QREFS 1.25 V circuits | -0.3 | 1.41 | V |
| VDDPX\_VBIAS\_SDC | Reference voltage for SDC | -0.3 | 1.41 | V |
| VDDA\_APC\_CS\_1P8 | Application processor current sensor 1.8 V circuits | -0.3 | 2.09 | V |
| VDD\_QFPROM | Programming the QFPROM | -0.3 | 2.09 | V |
| VDDA\_UFS\_1P8 | UFS 1.8 V circuits | -0.3 | 2.09 | V |
| VDDA\_USB\_HS\_1P8 | USB0/1 high-speed (HS) 1.8 V circuits | -0.3 | 2.09 | V |
| VDDA\_USB\_SS\_1P8 | Power for USB SuperSpeed (SS) 1.8 V circuits | -0.3 | 2.09 | V |
| VDDA\_LPAAUDIO\_PLL | LPA AUDIO PLL circuits | -0.3 | 2.09 | V |
| VDDA\_CAMSS\_PLL | CAMSS PLL circuits | -0.3 | 2.09 | V |
| VDDA\_PCIE\_1P8 | PCIe 1.8 V circuits | -0.3 | 2.09 | V |
| VDDPX\_0 | Digital pad circuits – control signals | -0.3 | 2.09 | V |
| VDDPX\_1 | Digital pad circuits - EBI and DDR I/O | -0.3 | 1.29 | V |
| VDDPX\_2 | Digital pad circuits – SDC2 dual-voltage | – | – | – |
| VDDPX\_2 | Low voltage | -0.3 | 2.11 | – |
| VDDPX\_2 | High voltage | -0.3 | 3.36 | V |
| VDDPX\_3 | Digital pad circuits – most I/Os | -0.3 | 2.11 | V |
| VDDPX\_5 | Digital pad circuits | -0.3 | 2.11 | V |
| VDDPX\_6 | Digital pad circuits | -0.3 | 2.11 | V |
| VDDPX\_7 | Digita l pad circuits – SDC1 | -0.3 | 2.11 | V |
| VDDPX\_10 | Digital pad circuits – UFS clock | -0.3 | 1.40 | V |
| VDDPX\_11 | Digital pad circuits – CXO | -0.3 | 2.11 | V |
| VDDIO\_EBI | EBI0/1 I/O memory circuits | -0.3 | 0.75 | V |
| VDDIO\_CK\_EBI0 | EBI0 I/O clock circuits | -0.3 | 0.75 | V |
| VDDIO\_CK\_EBI1 | EBI1 I/O clock circuits | -0.3 | 0.75 | V |
| VDDA\_EBI | EBI0/EBI1 PHYcircuits | -0.3 | 1.17 | V |
| VDDA\_CC\_EBI | EBI0/EBI1 clock circuits | -0.3 | 1.17 | V |
| VDDA\_USB\_HS\_3P1 | USB0/1 HS 3.1 V circuits | -0.3 | 3.52 | V |
| VDD\_WCSS | WCSS circuits | -0.3 | 1.07 | V |
| VDDA\_WCSS\_PLL | WCSS PLL circuits | -0.3 | 2.09 | V |
| VDDA\_WCSS\_ADCDAC | WCSS ADC and DAC | -0.3 | 1.46 | V |
| Ts | Storage temperature[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_1_absolute-maximum-ratings),[^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_2_absolute-maximum-ratings) | -55 | 150 | °C |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_1_absolute-maximum-ratings) The storage temperature range applies when the device is
in the OFF state (the device is not assembled in any platform and is not
electrically connected to any voltage or I/O signals). Damage may occur when the
device is subjected to this temperature for any length of time.
[^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_2_absolute-maximum-ratings) For devices
shipped in tape and reel, the storage temperature range is [+15°C~+35°C] and <
90% relative humidity (RH). QTI recommends allowing the device to return to ambient
room temperature before usage.
## Operating conditions
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
Operating conditions include parameters such as power supply voltage, power distribution
impedances, and thermal conditions. The QCS615 chipsets meet all
performance specifications listed in the following table when used within the operating
conditions.
Note: Keep the thermal mitigation algorithm enabled with default limits to ensure
that the operating temperature range is kept within the specification.
| Parameter[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_1_operating-conditions) | Parameter[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_1_operating-conditions) | Min | Max | Unit |
| --- | --- | --- | --- | --- |
| ***Power supply voltages*** | ***Power supply voltages*** | ***Power supply voltages*** | ***Power supply voltages*** | ***Power supply voltages*** |
| VDD\_APC0 | ***Kryo Silver application processor*** | ***Kryo Silver application processor*** | ***Kryo Silver application processor*** | ***Kryo Silver application processor*** |
| VDD\_APC0 | Turbo | 0.73 | 1.067 | V |
| VDD\_APC0 | Nominal-L1 | 0.69 | 1 | V |
| VDD\_APC0 | Nominal | 0.655 | 0.939 | V |
| VDD\_APC0 | SVSL1 | 0.6 | 0.86 | V |
| VDD\_APC0 | SVS | 0.55 | 0.781 | V |
| VDD\_APC0 | LowSVS | 0.49 | 0.688 | V |
| VDD\_APC1 | ***Kryo Gold application processor*** | ***Kryo Gold application processor*** | ***Kryo Gold application processor*** | ***Kryo Gold application processor*** |
| VDD\_APC1 | Turbo | 0.73 | 1.067 | V |
| VDD\_APC1 | Nominal-L1 | 0.69 | 1 | V |
| VDD\_APC1 | Nominal | 0.655 | 0.939 | V |
| VDD\_APC1 | SVSL1 | 0.6 | 0.86 | V |
| VDD\_APC1 | SVS | 0.55 | 0.781 | V |
| VDDCX | Digital core circuits | – | – | – |
| VDDCX | Turbo | 0.785 | 1.067 | V |
| VDDCX | Nominal-L1 | 0.785 | 1 | V |
| VDDA\_EBI VDDA\_CC\_EBI | EBI0/EBI1 clock and PHY circuits | – | – | – |
| | Turbo | 0.785 | 1.067 | V |
| | Nominal-L1 | 0.785 | 1 | V |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_1_operating-conditions) Parts with voltages outside of the
specified ranges are not guaranteed to operate properly.
| Parameter[^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_2_operating-conditions) | Parameter[^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_2_operating-conditions) | Minimum | Typical[^3^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_3_operating-conditions) | Maximum | Unit |
| --- | --- | --- | --- | --- | --- |
| ***Power supply voltages*** | ***Power supply voltages*** | ***Power supply voltages*** | ***Power supply voltages*** | ***Power supply voltages*** | ***Power supply voltages*** |
| VDDA\_CSI0\_1P2 | MIPI CSI0 1.2 V circuits | 1.15 | 1.2 | 1.26 | V |
| VDDA\_CSI1\_1P2 | MIPI CSI1 1.2 V circuits | 1.15 | 1.2 | 1.26 | V |
| VDDA\_CSI2\_1P2 | MIPI CSI2 1.2 V circuits | 1.15 | 1.2 | 1.26 | V |
| VDDA\_DSI0\_1P2 | MIPI DSI0 1.2 V circuits | 1.15 | 1.2 | 1.26 | V |
| VDDA\_DSI0\_PLL | MIPI DSI0 PLL 1.2 V circuits | 1.15 | 1.2 | 1.26 | V |
| VDDA\_PLL\_HV\_CC\_EBI | EBI high-voltage circuits | 1.15 | 1.2 | 1.26 | V |
| VDDA\_DSI0\_0P9 | MIPI DSI0 0.9 V circuits | 0.873 | 0.925 | 0.975 | V |
| VDDA\_USB0\_HS\_0P9 | USB0 high-speed (HS) 0.9 V circuits | 0.873 | 0.925 | 0.975 | V |
| VDDA\_USB1\_HS\_0P9 | USB1 high-speed (HS) 0.9 V circuits | 0.873 | 0.925 | 0.975 | V |
| VDDA\_USB\_SS\_DP\_ CORE | USB1SS and DisplayPort core circuits | 0.873 | 0.925 | 0.975 | V |
| VDDA\_UFS\_CORE | UFS core circuits | 0.873 | 0.925 | 0.975 | V |
| VDDA\_EBI\_PLL | EBI0/EBI1 PLL circuits | 0.873 | 0.925 | 0.975 | V |
| VDDA\_PCIE\_CORE | PCIe core circuits | 0.873 | 0.925 | 0.975 | V |
| VDDA\_QREFS\_1P25 | QREFS 1.25 V circuits | 1.21 | 1.25 | 1.28 | V |
| VDDPX\_VBIAS\_SDC | Reference voltage for SDC | 1.21 | 1.25 | 1.28 | V |
| VDDA\_APC\_CS\_1P8 | Application processor current sensor 1.8 V circuits | 1.71 | 1.8 | 1.9 | V |
| VDD\_QFPROM | Programming the QFPROM | 1.71 | 1.8 | 1.9 | V |
| VDDA\_UFS\_1P8 | UFS 1.8 V circuits | 1.71 | 1.8 | 1.9 | V |
| VDDA\_USB\_HS\_1P8 | USB0/1high-speed (HS) 1.8 V circuits | 1.71 | 1.8 | 1.9 | V |
| VDDA\_USB\_SS\_1P8 | Power for USB SuperSpeed (SS) 1.8 V circuits | 1.71 | 1.8 | 1.9 | V |
| VDDA\_LPAAUDIO\_PLL | LPA AUDIO PLL circuits | 1.71 | 1.8 | 1.9 | V |
| VDDA\_CAMSS\_PLL | CAMSS PLL circuits | 1.71 | 1.8 | 1.9 | V |
| VDDA\_PCIE\_1P8 | PCIe1.8 V circuits | 1.71 | 1.8 | 1.9 | V |
| VDDPX\_0 | Digital pad circuits – control signals | 1.71 | 1.8 | 1.9 | V |
| VDDPX\_1 | Digital pad circuits - EBI and DDR I/O | 1.07 | 1.1 | 1.17 | V |
| VDDPX\_2 | Digital pad circuits – SDC2 dual voltage | – | – | – | – |
| VDDPX\_2 | Low voltage | 1.7 | 1.8 | 1.92 | V |
| VDDPX\_2 | High voltage | 2.7 | 2.95 | 3.05 | V |
| VDDPX\_3 | Digital pad circuits – most I/Os | 1.7 | 1.8 | 1.92 | V |
| VDDPX\_5 | Digital pad circuits | 1.7 | 1.8 | 1.92 | V |
| VDDPX\_6 | Digital pad circuits | 1.7 | 1.8 | 1.92 | V |
| VDDPX\_7 | Digital pad circuits – SDC1 | 1.7 | 1.8 | 1.92 | V |
| VDDPX\_10 | Digital pad circuits – UFS clock | 1.15 | 1.2 | 1.27 | V |
| VDDPX\_11 | Digital pad circuits – CXO | 1.7 | 1.8 | 1.92 | V |
| VDDIO\_EBI | EBI0/1I/O memory circuits | 0.57 | 0.6 | 0.6485 | V |
| VDDIO\_CK\_EBI0 | EBI0I/O clock circuits | 0.57 | 0.6 | 0.6485 | V |
| VDDIO\_CK\_EBI1 | EBI1I/O clock circuits | 0.57 | 0.6 | 0.6485 | V |
| VDDA\_USB\_HS\_3P1 | USB0/1HS 3.1 V circuits | 2.98 | 3.1 | 3.2 | V |
| VDD\_WCSS | WCSS circuits | 0.823 | 0.848 | 0.97 | V |
| VDDA\_WCSS\_PLL | WCSS PLL circuits | 1.7 | 1.8 | 1.9 | V |
| VDDA\_WCSS\_ADCDAC | WCSS ADC and DAC | 1.26 | 1.3 | 1.33 | V |
| ***Thermal conditions*** [^4^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_4_operating-conditions) | ***Thermal conditions*** [^4^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_4_operating-conditions) | ***Thermal conditions*** [^4^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_4_operating-conditions) | ***Thermal conditions*** [^4^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_4_operating-conditions) | ***Thermal conditions*** [^4^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_4_operating-conditions) | ***Thermal conditions*** [^4^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_4_operating-conditions) |
| Ta | Ambient operating temperature | -40 | – | +85 [^5^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_5_operating-conditions) | °C |
| Tj | Junction operating temperature | – | – | +105 | °C |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
[^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_2_operating-conditions) Parts with voltages outside of the
specified ranges are not guaranteed to operate properly.
[^3^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_3_operating-conditions) Typical voltages represent the recommended output settings of the
companion PMIC device.
[^4^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_4_operating-conditions) To maximize the
device performance and useful life, follow the thermal guidelines for the system –
document to be shared later.
[^5^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_5_operating-conditions) The Tj max specification must be
met.
Note: Unless otherwise specified, the specifications apply across the
device's operating temperature range.
## Power delivery network specification
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
This section outlines the power delivery network (PDN) requirements for designing with
QTI processors that operate at higher frequencies. A detailed power delivery network
specification is available in the QCS615 Chipset Power Delivery Network
Specification (80-73480-1P) document.
## Digital-logic characteristics
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The digital I/O performance specification depends on pad type, usage, supply voltage, or a
combination of pad type, usage, and supply voltage.
- Some of the I/Os are dedicated for interconnections between the SoC device and other ICs
within the QTI chipset; therefore, specifications are not required.
- Some of the I/Os conform to existing standards, such as I²C and SPI. QTI devices comply
with those standards; therefore, additional specifications are not required.
- All other digital I/Os require performance specifications.
Note: Unless otherwise specified, all device characterizations are carried
out across the specified operating temperature and voltage ranges.
Table : DC specification of 1.8 V GPIOs and WCSS WSI I/Os
| Parameter | Description | Min | Max | Unit |
| :---: | --- | :---: | :---: | :---: |
| VIH | High-level input voltage, CMOS/Schmitt (HIHYS\_EN = low) | 0.65 × VDD\_PX3 | VDD\_PX3 + 0.3 V | V |
| VIL | Low-level input voltage, CMOS/Schmitt (HIHYS\_EN = low) | -0.3 V | 0.35 × VDD\_PX3 | V |
| VIH | High-level input voltage, CMOS/Schmitt (HIHYS\_EN = high) | 0.7 × VDD\_PX3 | VDD\_PX3 + 0.3 V | V |
| VIL | Low-level input voltage, CMOS/Schmitt (HIHYS\_EN = high) | -0.3 V | 0.3 × VDD\_PX3 | V |
| VHYS | Schmitt hysteresis voltage (HIHYS\_EN= low) | 100 | – | mV |
| VHYS | Schmitt hysteresis voltage (HIHYS\_EN = high) | 300 | – | mV |
| IIH | Input high leakage current [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_uhf_ssw_1dc) | – | 1.0 | µA |
| IIL | Input low leakage current [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_uhf_ssw_1dc) | -1.0 | – | µA |
| IIHPD | Input high leakage current with pull-down | 27.5
(60) | 97.5
(20) | µA
(kΩ) |
| IILPU | Input low leakage current with pull-up | -97.5 (20) | -27.5
(60) | µA
(kΩ) |
| VOH | High-level output voltage, CMOS [^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_cwh_scq_hgc) | VDD\_PX3 - 0.45 | VDD\_PX3 | V |
| VOL | Low-level output voltage, CMOS [^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_cwh_scq_hgc) | 0.0 | 0.45 | V |
^1^ IIH and IIL values are based on nominal
PVT (TT/25°C).
^2^ VOL and
VOH are measured at IOL and IOH respectively,
with 16 mA current across minimum and maximum voltages and operating temperatures.
For more information regarding possible drive strength settings, see [Table : Possible drive strength](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__table_asf_xzn_hgc).
Table : Possible drive strength
| Bit configuration | Drive strength (mA) |
| :---: | :---: |
| 000 | 2 |
| 001 | 4 |
| 010 | 6 |
| 011 | 8 |
| 100 | 10 |
| 101 | 12 |
| 110 | 14 |
| 111 | 16 |
| Parameter | Parameter | Comments | Minimum | Maximum | Unit |
| --- | --- | --- | --- | --- | --- |
| ***Common to all 1.8 /2.95 V dual-voltage pads*** | ***Common to all 1.8 /2.95 V dual-voltage pads*** | ***Common to all 1.8 /2.95 V dual-voltage pads*** | ***Common to all 1.8 /2.95 V dual-voltage pads*** | ***Common to all 1.8 /2.95 V dual-voltage pads*** | ***Common to all 1.8 /2.95 V dual-voltage pads*** |
| RP | Pull resistance [^3^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_utj_kmh_wcc) | pull-up and pull-down | 10 | 100 | kΩ |
| RK | Keeper resistance [^3^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_utj_kmh_wcc) | – | 10 | 100 | kΩ |
| VSHYS | Schmitt hysteresis voltage | – | 100 | – | mV |
| ***SDC2 pads at 2.95 V*** | ***SDC2 pads at 2.95 V*** | ***SDC2 pads at 2.95 V*** | ***SDC2 pads at 2.95 V*** | ***SDC2 pads at 2.95 V*** | ***SDC2 pads at 2.95 V*** |
| IIH | Input high leakage current | No pull-down | -20 | 20 | µA |
| IIL | Input low leakage current | No pull-up | – | 1000 | µA |
| VIH | High-level input voltage | CMOS/Schmitt | 0.625 × VDDPX | VDDPX + 0.3 | V |
| VIL | Low-level input voltage | CMOS/Schmitt | -0.3 | 0.25 × VDDPX | V |
| VOH | High-level output voltage | CMOS, at rated drive strength | 0.75 × VDDPX | VDDPX | V |
| VOL | Low-level output voltage | CMOS, at rated drive strength | 0.0 | 0.125 × VDDPX | V |
| ***SDC2 pads at 1.8 V*** | ***SDC2 pads at 1.8 V*** | ***SDC2 pads at 1.8 V*** | ***SDC2 pads at 1.8 V*** | ***SDC2 pads at 1.8 V*** | ***SDC2 pads at 1.8 V*** |
| IIH | Input high leakage current | No pull-down | – | 5 | µA |
| IIL | Input low leakage current | No pull-up | -5 | – | µA |
| VIH | High-level input voltage | CMOS/Schmitt | 1.27 | 2 | V |
| VIL | Low-level input voltage | CMOS/Schmitt | -0.3 | 0.58 | V |
| VOH | High-level output voltage [^4^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_xll_rcq_hgc) | CMOS, at rated drive strength | 1.4 | – | V |
| VOL | Low-level output voltage [^4^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_xll_rcq_hgc) | CMOS, at rated drive strength | – | 0.45 | V |
^3^ See [Table : 2. Pin descriptions – general pins](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#kxg1605206453609__table_bkv_zjf_rnb) for pull-up,
pull-down, and keeper options for each pad (where appropriate).
^4^ VOL and
VOH are measured at IOL and IOH respectively,
with 16 mA current across minimum and maximum voltages and operating temperatures.
For more information regarding possible drive strength settings, see [Table : Possible drive strength](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__table_c55_rb4_hgc).
Table : Possible drive strength
| Bit configuration | Drive strength (mA) |
| :---: | :---: |
| 000 | 2 |
| 001 | 4 |
| 010 | 6 |
| 011 | 8 |
| 100 | 10 |
| 101 | 12 |
| 110 | 14 |
| 111 | 16 |
| Parameter | Parameter | Comments | Minimum | Maximum | Unit |
| --- | --- | --- | --- | --- | --- |
| RP | Pull resistance [^5^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_emr_l5h_wcc) | Pull-up and pull-down | 10 | 100 | kΩ |
| RK | Keeper resistance [^5^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_emr_l5h_wcc) | – | 10 | 100 | kΩ |
| VSHYS | Schmitt hysteresis voltage | – | 100 | – | mV |
| VIH | High-level input voltage | CMOS/Schmitt | 0.7 × VDDPX | VDDPX + 0.3 | V |
| VIL | Low-level input voltage | CMOS/Schmitt | -0.3 | 0.2 × VDDPX | V |
| VOH | High-level output voltage [^6^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_kdc_wy4_hgc) | CMOS, at rated drive strength(2) | 0.8 × VDDPX | VDDPX | V |
| VOL | Low-level output voltage [^6^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__fn_kdc_wy4_hgc) | CMOS, at rated drive strength(2) | 0.0 | 0.4 | V |
| IIH | Input high leakage current | No pull-down | – | 5 | µA |
| IIL | Input low leakage current | No pull-up | -5 | – | µA |
^5^ See [Table : 3. Pin descriptions–general-purpose input/output ports](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#kxg1605206453609__table_u1k_vdn_tnb) for pull-up,
pull-down, and keeper options for each pad (where appropriate).
^6^ VOL and
VOH are measured at IOL and IOH respectively,
with 16 mA current across minimum and maximum voltages and operating temperatures.
For more information regarding possible drive strength settings, see [Table : Possible drive strength](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__table_tdv_dc4_hgc).
Table : Possible drive strength
| Bit configuration | Drive strength (mA) |
| :---: | :---: |
| 000 | 2 |
| 001 | 4 |
| 010 | 6 |
| 011 | 8 |
| 100 | 10 |
| 101 | 12 |
| 110 | 14 |
| 111 | 16 |
## Timing characteristics
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
Specifications for the device timing characteristics are included (where appropriate) under
each function along with all its other performance specifications. Some general comments about
timing characteristics and pertinent pad design methodologies are included here.
Note:
QCS615 devices are characterized with actively terminated loads,
so all baseband timing parameters assume no bus loading. For more information, see [Rise and fall time specifications](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#kfb1612783228904).
### Timing diagram conventions
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The following figure shows the conventions used within timing diagrams throughout this
document.
Figure : Timing diagram conventions
For each signal in the diagram:
- One clock period (T) extends from one rising clock edge to the next rising clock edge.
- The high level represents 1, the low level represents 0, and the middle level represents
the floating (high impedance) state.
- When both the high and low levels are shown over the same time interval, the meaning depends on the signal type:
- For a bus type signal (multiple bits), the processor or external interface is driving a value, but that value may or may not be valid.
- For a single signal, it indicates *don't care*.
### Rise and fall time specifications
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
QCS615 chipsets characterization testing uses actively terminated
loads, making the rise and fall times quicker (mimicking a no-load condition). The impact of
different external load conditions on rise and fall times is shown in the following
figure.
Figure : Rise and fall times under different load conditions
To account for external load conditions, add the rise or fall times to the parameters that
start timing at the QCS615 chipsets and terminate at an external
device (or vice versa). Adding these rise and fall times is equivalent to applying capacitive
load derating factors.
### Pad design methodology
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The QCS615 chipsets use a generic CMOS pad driver design. The pad
design creates a pin response and behavior that is symmetric, regarding the associated
VDD_PXDD_PX/2% or 50% of Vsupply. The input switchpoint for pure
input-only pads is a VDD_PX supply. The documented switchpoints (guaranteed over
worst-case combinations of process, voltage, and temperature by both design and
characterization) are 35% of VDD_PX for VIL and 65% of VDD_PX
for VIH.
Figure : Digital input-signal switchpoints
Outputs (such as addresses, chip selects, and clocks) are designed and characterized to
source or sink a large DC output current (several mA) at the documented VOH (min)
and VOL(max) levels over worst-case process/voltage/temperature. The pad output
structures are essentially CMOS drivers. They may have a small amount of IR loss (estimated at
<50 mV under worst-case conditions), the expected zero DC load outputs are estimated to
be:
- VOH~ VDDPX - 50 mV or more
- VOL~ 50 mV or less
Figure : Output pad equivalent circuit
The output pads are essentially CMOS outputs with a corresponding FET-type output voltage/current transfer function. When an output pad is shorted to the opposite power rail, the pad is capable of sourcing or sinking ISC (SC = short-circuit) of current, where the magnitude of ISC is larger than the current capability at the intended output logic levels.
The DC output drive strength can be approximated by linear interpolations between
VOH (min) and VDDPX - 50 mV, and between VOL (max) and
50 mV. For example, an output pad driving low that guarantees 4.5 mA at VOL (max)
provides approximately 3.0 mA or more at 2/3 × [VOL (max) - 50 mV], and 1.5 mA or
more at 1/3 × [VOL (max) - 50 mV]. Likewise, an output pad driving high that
guarantees 2.5 mA at VOH (min) provides approximately 1.25 mA or more at ½ ×
[VDDPX - 50 mV + VOH (min)].
The target application includes a radio, output pads are designed to minimize output slew
rates. Decreased slew rates limit high-frequency spectral components that tend to desensitize
the companion radio.
## Memory support
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
All timing parameters in this document assume no bus loading. Rise/fall time numbers must
factor into the numbers in this document. For example, setup time numbers get worse, and hold
time numbers may improve.
### EBI memory support
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
EBI is dedicated to the off-chip LPDDR4X SDRAM memory. It supports LPDDR4X SDRAM memory parts
that are compliant with the JEDEC Standard for Low-Power Double Data Rate 4 SDRAM
(JESD209-4-1).
### eMMC on SDC1
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
eMMC NAND flash supports the SDC1 port. For more information, see [Secured digital interfaces](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430).
## Multimedia
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
This topic addresses the performance specification of multimedia parameters.
### Camera interfaces
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The QCS615 chipsets support three 4-lane MIPI CSI: CSI0, CSI1, and
CSI2.
Table : Supported MIPI CSI standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *MIPI Alliance Specification for D-PHY v1.2* | Supports only unidirectional data receiving |
| *MIPI Alliance Specification for C-PHY v1.0* | None |
### Display support
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The QCS615 chipset supports 4-lane MIPI DSI port.
Table : Supported MIPI-DSI standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *MIPI Alliance Specification v1.01 for Display Serial Interface* | Virtual channel not supported |
| *MIPI D-PHY Specification v1.2* | None |
### Audio support
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
QCS615 chipset supports the following audio-related interfaces:
- SLIMbus: [SLIMbus interface](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fhj1612792152597)
- I²S: [I²S interfaces](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#qnl1612792195661)
- PCM/TDM: [PCM/TDM interfaces](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#concept_oqm_3db_ycc)
## Connectivity
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The connectivity functions that require electrical specifications for this chipset are as
follows:
- SD, including SD cards and multimedia cards (MMC)
- High-speed USB/on-the-go (USB-OTG, host mode only) with a built-in physical layer
(PHY)
- DisplayPort interface
- Peripheral Component Interconnect Express (PCIe) interfaces
- Universal Flash Storage (UFS)
- Reduced Gigabit Media Independent Interface (RGMII)
- Reduced Media Independent Interface (RMII)
- Serial low-power inter-chip media bus (SLIMbus) interface
- Inter-IC sound (I²S) interfaces
- Pulse-coded modulation (PCM) interfaces
- Time-division multiplexing (TDM) interfaces
- Touchscreen connections
- Dedicated I²C interfaces for camera (CCI I²C)
- Through a proper configuration of the 14 QUP ports:
- Universal asynchronous receiver/transmitter (UART) ports
- Inter-integrated circuit (I²C) interfaces
- Serial peripheral interface (SPI) ports
The pertinent specifications for these functions are detailed in the following topics.
Note: In addition to the following hardware specifications, see the latest software release notes for software-based performance features or limitations.
### Secured digital interfaces
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The supported secure digital (SD) interface standards and their exceptions are listed
here.
Table : Supported SD standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *MultiMediaCard Host Specification version 5.1* | None |
| *Secure Digital: Physical Layer Specification version 3.0* | None |
| *SDIO Card Specification version 3.0* | None |
In the following figure,
- VIH denotes VIH(min) and VIL denotes
VIL(max). For more information on high-level input voltage and on low-level
input voltage, see [Table : P2 (1.8 V/2.95 V) digital I/O characteristics](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603__table_qdt_wkh_wcc).
- VT = 0.975 V clock threshold and VDDP7 = 1.8 V indicates clock reference point for
timing measurements.
Figure : Secured digital interface timing
| SDCC modes | Frequency | Parameter | Description | Minimum (ns) | Maximum (ns) |
| --- | --- | --- | --- | --- | --- |
| HS200 (SDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 200 MHz | TclkH | Clock high time | 2.25 | 2.75 |
| HS200 (SDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 200 MHz | Tcidv | Command input valid window | – | 2.4 |
| HS200 (SDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 200 MHz | Tcodly | Command output delay | -1.45 | 0.85 |
| HS200 (SDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 200 MHz | Tidv | Data input valid window | – | 2.4 |
| HS200 (SDR 200 MHz) [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 200 MHz | Tdodly | Data output delay | -1.45 | 0.85 |
| DDR52 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 52 MHz | TclkH | Clock high time | 8.65 | 10.57 |
| DDR52 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 52 MHz | Tcisu | Command input setup | – | 5.53 |
| DDR52 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 52 MHz | Tcih | Command input hold | – | 1.50 |
| DDR52 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 52 MHz | Tcodly | Command output delay | -7.85 | 2.65 |
| DDR52 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 52 MHz | Tisu | Data input setup | – | 1.65 |
| DDR52 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 52 MHz | Tih | Data input hold | – | 1.50 |
| DDR52 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 52 MHz | Tdodly | Data output delay | 2.50 | 6.15 |
| SDR104 | 208 MHz | TclkH | Clock high time | 2.16 | 2.64 |
| SDR104 | 208 MHz | Tcidv | Command input valid window | – | 2.4 |
| SDR104 | 208 MHz | Tcodly | Command output delay | -1.36 | 0.76 |
| SDR104 | 208 MHz | Tidv | Data input valid window | – | 2.4 |
| SDR104 | 208 MHz | Tdodly | Data output delay | -1.36 | 0.76 |
| DDR50 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 50 MHz | TclkH | Clock high time | 9 | 11 |
| DDR50 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 50 MHz | Tcisu | Command input setup | – | 6.3 |
| DDR50 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 50 MHz | Tcih | Command input hold | – | 1.5 |
| DDR50 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 50 MHz | Tcodly | Command output delay | -8.2 | 3 |
| DDR50 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 50 MHz | Tisu | Data input setup | – | 2 |
| DDR50 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 50 MHz | Tih | Data input hold | – | 1.5 |
| DDR50 [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#won1612791672430__fn_e1j_3qp_hgc) | 50 MHz | Tdodly | Data output delay | 0.8 | 6 |
| SDR50 | 100 MHz | TclkH | Clock high time | 4.5 | 5.5 |
| SDR50 | 100 MHz | Tcisu | Command input setup | – | 2.5 |
| SDR50 | 100 MHz | Tcih | Command input hold | – | 1.5 |
| SDR50 | 100 MHz | Tcodly | Command output delay | -3.7 | 1.5 |
| SDR50 | 100 MHz | Tisu | Data input setup | – | 2.5 |
| SDR50 | 100 MHz | Tih | Data input hold | – | 1.5 |
| SDR50 | 100 MHz | Tdodly | Data output delay | -3.7 | 1.5 |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
^1^ For
DDR200, DDR52 and SD DDR50, command input/output is only in single data rate (with
respect to controller CLK falling edge). Only data input/ output is running at
DDR.
### USB interfaces
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The supported USB standards and their exceptions are listed here.
Table : Supported USB standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *Universal Serial Bus Specification, Revision 3.1* (August 11, 2014 or later) | SS Gen 2 |
| *Universal Serial Bus Specification*, Revision 2.0 (April 27, 2000 or later) | Low speed is not supported in device mode |
| *On-The-Go Supplement to the USB 2.0 Specification* (June 24, 2003, Revision 1.0 A or later) | Supports the host mode aspect of OTG only |
### DisplayPort
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
DisplayPort++ is not supported. The supported DisplayPort standards and their exceptions are
listed here.
Table : Supported DisplayPort standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *VESA DisplayPort V1.4* | None |
### PCIe interface
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
QCS615 supports both root complex (RC) mode and endpoint (EP) mode on PCIe port. The supported PCIe standards and their exceptions are listed here.
Table : Supported PCIe standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *PCI Express Specification, Revision 2.1* (March 4, 2009 or later) | None |
### UFS interface
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The supported UFS standards and their exceptions are listed here.
Table : Supported UFS standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *Universal Flash Storage (UFS), Version 2.1* | None |
### RGMII interface
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
RGMII interface supports 1.8 V mode only and is compliant with JESD8-7.
Table : Supported RGMII standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| *Reduced Gigabit Media Independent Interface (RGMII) v1.3 and v2.0* | None |
### RMII interface
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
RMII interface supports 1.8 V mode only and is compliant with JESD8-7.
Table : Supported RMII standards and exceptions
| Applicable standard | Feature exceptions |
| --- | --- |
| *Reduced Media Independent Interface (RMII) v1.2* | None |
### SLIMbus interface
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The supported SLIMbus standards and their exceptions are listed here.
Table : Supported SLIMbus standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *MIPI Alliance Specification for Serial Low-power Interchip Media Bus, Version 1.01.01* |
No support of the CHANGE_CONTENT() message by any of the devices in the component. Only the manager is given the ability to manage data channels in the system
No support for the elemental access mode for information and value elements
No support for the following transport protocols
Asynchronous half-duplex
Extended asynchronous half-duplex
No support for the locked transport protocol
No support of partial mask in CHANGE_VALUE message
|
### I²S interfaces
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
There are two supported I²S interface types:
- Legacy I²S interfaces for primary and secondary microphones and speakers
- The multiple I²S (MI²S) interface for microphone and speaker functions
The following information applies to both interface types. The supported I²S standards and
their exceptions are listed here.
Table : Supported I²S standards and exceptions
| Applicable standards | Feature exceptions |
| :---: | :---: |
| *Philips I²S Bus Specifications revised June 5, 1996* | None |
Figure : I²S timing diagram
The supported I²S interface timings are listed here.
| Parameter | Parameter | Min | Typ | Max | Unit | Comments |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | ***Using internal SCK*** | X% ofT |
| Frequency | Frequency | – | – | 24.576 | MHz | – |
| T | Clock period | 40.69 | – | – | ns | – |
| **t**(HC) | Clock high | 0.45 × T | – | 0.55 × T | ns | – |
| **t**(LC) | Clock low | 0.45 × T | – | 0.55 × T | ns | – |
| **t**(sr) | SD and WS input setup time | 8.14 | – | – | ns | 20 |
| **t**(hr) | SD and WS input hold time | 0 | – | – | ns | – |
| **t**(dtr) | SD and WS output delay | – | – | 6.10 | ns | 15 |
| **t**(htr) | SD and WS output hold time | 0 | – | – | ns | – |
| ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | ***Using external SCK*** | – |
| Frequency | Frequency | - | – | 24.576 | MHz | X% ofT |
| T | Clock period | 40.69 | – | – | ns | – |
| **t**(HC) | Clock high | 0.45 × T | – | 0.55 × T | ns | – |
| **t**(LC) | Clock low | 0.45 × T | – | 0.55 × T | ns | – |
| **t**(sr) | SD and WS input setup time | 8.14 | – | – | ns | 20 |
| **t**(hr) | SD and WS input hold time | 0 | – | – | ns | – |
| **t**(dtr) | SD and WS output delay | – | – | 6.10 | ns | 15 |
| **t**(htr) | SD and WS output hold time | – | – | – | ns | – |
| Parameter | Parameter | Comments[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_1_I2S-interfaces) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| ***Using External SCK*** | ***Using External SCK*** | ***Using External SCK*** | ***Using External SCK*** | ***Using External SCK*** | ***Using External SCK*** | ***Using External SCK*** |
| Frequency | Frequency | – | – | – | 65.536 | MHz |
| T | Clock period | – | 15.38 | – | – | ns |
| t(HC) | Clock high | – | 0.40 × T | – | 0.60 × T | ns |
| t(LC) | Clock low | – | 0.40 × T | – | 0.60 × T | ns |
| t(sr) | SD and WS input setup time | – | 2.71 | – | – | ns |
| t(hr) | SD and WS input hold time | – | 1.5 | – | – | ns |
[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_1_I2S-interfaces) Load capacitance is between 10 pF and 40 pF.
Note:
- Both HS-I²S are slaves only (HS I²S cannot drive clock and WS lines; should be driven by
master).
- HS-I²S can only receive data (cannot send data to master).
- HS-I²S does not have access to LPM (LPASS local memory). All received data will be
routed to DDR.
### PCM/TDM interfaces
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
Figure : PCM/TDM audio format with different sync modes
| Parameter[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_1_pcm-tdm-interfaces) | Parameter[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_1_pcm-tdm-interfaces) | Comments | Min | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** | ***Master mode*** |
| Frequency | Frequency | – | – | 24.576 | MHz |
| T | Clock period | – | 40.69 | – | ns |
| t(HC) | Clock high | – | 0.45 × T | 0.55 × T | ns |
| t(LC) | Clock low | – | 0.45 × T | 0.55 × T | ns |
| t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | – | 8.14 | – | ns |
| t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | – | 0 | – | ns |
| t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC output delay | – | – | 6.10 | ns |
| ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** | ***Slave mode*** |
| Frequency | Frequency | – | – | 24.576 | MHz |
| T | Clock period | – | 40.69 | – | ns |
| t(HC) | Clock high | – | 0.45 × T | 0.55 × T | ns |
| t(LC) | Clock low | – | 0.45 × T | 0.55 × T | ns |
| t(sr) | PCM/TDM\_DIN and PCM/TDM\_SYNC setup time | – | 8.14 | – | ns |
| t(hr) | PCM/TDM\_DIN and PCM/TDM\_SYNC hold time | – | 0 | – | ns |
| t(dtr) | PCM/TDM\_DOUT and PCM/TDM\_SYNC output delay | – | – | 6.10 | ns |
[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_1_pcm-tdm-interfaces) Load capacitance is between
10 pF to 40 pF.
### Touchscreen connections
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
Touchscreen panels are supported using I²C buses ([I²C interface](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#arb1612792921091)) and GPIOs configured as discrete digital inputs ([Digital-logic characteristics](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603)).
### I²C interface
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The supported I²C standards and their exceptions are listed here.
Table : Supported I²C standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *I²C Specification, version 3.0* | HS mode, slave mode, multi-master mode, and 10‑bit addressing are not supported. |
### Serial peripheral interface
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The QCS615 chipsets support SPI as a master on QUP2/QUP4/QUP6/QUP7
ports and the additional Quad-SPI interface. SPI slave mode is supported on QUP2/QUP6 ports as
listed in [Physical interfaces](https://docs.qualcomm.com/doc/80-73480-1/topic/Introduction.html#qyn1605199756466__section_dfc_3xy_p1c).
The Tx and Rx sampling edge will differ depending on the mode configuration (Clock PHA and
POL settings). Mode 1 is used as an example in the following timing diagram.
Figure : SPI master timing diagram
The supported SPI master timing characteristics are listed here.
Table : SPI master timing characteristics
| Parameter | Comments | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| T (SPI clock period) [^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_1_serial-peripheral-interface) | 50 MHz maximum | 20 | – | – | ns |
| t(ch) | Clock high | 9 | – | – | ns |
| t(cl) | Clock low | 9 | – | – | ns |
| t(mov) | Master output valid | -5 | – | 5 | ns |
| t(mis) | Master input setup | 5 | – | – | ns |
| t(mih) | Master input hold | 1 | – | – | ns |
[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_1_serial-peripheral-interface) The minimum clock period includes 1% jitter of maximum
frequency.
Table : SPI slave timing characteristics for QUP_2/QUP_6
| Parameter | Comments | Min | Max | Unit |
| --- | --- | --- | --- | --- |
| T(SPI slave clock period)[^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_2_serial-peripheral-interface) | 50 MHz maximum | 20.0 | – | ns |
| t(ch) | Clock high | 9 | – | ns |
| t(cl) | Clock low | 9 | – | ns |
| t(sov) [^3^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#pzl1612792942013__fn_eqq_ckb_bdc) | Slave output valid | 2 | 13 | ns |
| t(sis) | Slave input setup time | 3 | – | ns |
| t(sih) | Slave input hold time | 3 | – | ns |
| S\_TRI\_STATE\_EN [^3^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#pzl1612792942013__fn_eqq_ckb_bdc) | Slave tri-state enable | – | 14 | ns |
| S\_TRI\_STATE\_DIS [^3^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#pzl1612792942013__fn_eqq_ckb_bdc) | Slave tri-state disable | – | 14 | ns |
[^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_2_serial-peripheral-interface) The minimum clock period includes 1% jitter of
maximum frequency.
^3^ The total capacitive load must not exceed 30 pF for a single
slave system. For each additional slave, 10 pF should be added to the clock and data
lines (not needed for chip-select since it is one-to-one). For example, 40 pF for
two slaves, although most systems have only a single slave. Care must be taken to
verify that every slave can drive the data line fast enough to meet the timing
requirement or the system must use a reduced frequency.
Note: Only SPI slave mode 1 (PHA = 1 and POL = 0) is supported.
### Quad serial peripheral interface (QSPI)
QSPI core implements the serial peripheral interface protocol to be used for different
purposes in the chip-level. The QSPI purpose is to read/write from/to a flash device through
an SPI slave by transmitting the physical layer of the SPI protocol according to
configurations loaded by software. QSPI core supports single, dual, and quad data bit serial
transfers.
QSPI core supports SDR, mode 0 (CPOL = 0, CPHA = 0), SPI clock = 60 MHz clocking modes and
frequencies:
Table : QSPI external interface to NOR-flash device
| Signal | In/out | Description |
| --- | --- | --- |
| QSPI\_CLK | Out | QSPI clock goes to the NOR-flash device |
| QSPI\_CS\_N | Out | Chip-select |
| QSPI\_MOSI | Out | Serial data output from the QSPI core to the NOR-flash device |
| QSPI\_MOSI\_OE | Out | Data output enable |
| QSPI\_MISO | In | Serial data input from the QSPI core to the NOR-flash device |
| QSPI\_FB\_CLK | In | Delayed version of QSPI\_CLK, routed back from the I/O pad. |
### QSPI timing specifications
Figure : SDR output timing diagram
Figure : SDR input timing diagram
Table : SDRAC parameters
| Parameter | Comments | Min | Max | Unit |
| --- | --- | --- | --- | --- |
| 1/T | QSPI clock frequency | – | 60 | MHz |
| t(mov) | Master output valid | -3.93 | 4.93 | ns |
| t(mis) | Master input setup time | 1.93 | – | ns |
| t(mih) | Master input hold time | 9.47 | – | ns |
## Internal functions
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
Some internal functions require external interfaces to enable their operation. These include clock generation, modes and resets, and JTAG functions.
### Clocks
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
Clocks that are specific to particular functions are addressed in the corresponding topics of
this document. Others are specified here.
### 19.2 MHz CXO input
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The following figure shows the XO timing parameters.
Figure : XO timing parameters
The supported XO timing parameters are listed here.
| Parameter | Parameter | Comments[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fntarg_1_19-2-MHz-CXO-input) | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| t(xoh) | XO logic high | – | 22.6 | – | 29.5 | ns |
| t(xol) | XO logic low | – | 22.6 | – | 29.5 | ns |
| T | XO clock period | – | – | 52.083 | – | ns |
| 1/T | Frequency | 19.2 MHz must be used | – | 19.2 | – | MHz |
[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#fnsrc_1_19-2-MHz-CXO-input) For more information, see [GPS Quality, 19.2 MHz 2520 Package Size,
Crystal and TH+Xtal Mini-Specification (80-V9690-24).](https://docs.qualcomm.com/bundle/80-V9690-24/resource/80-V9690-24.pdf)
### Sleep clock
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The following figure shows the sleep-clock timing parameters.
Figure : Sleep-clock timing parameters
The supported sleep-clock timing parameters are listed here.
| Parameter | Parameter | Comments | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| t(xoh) | Sleep-clock logic high | – | 4.58 | – | 25.94 | µs |
| t(xol) | Sleep-clock logic low | – | 4.58 | – | 25.94 | µs |
| T | Sleep-clock period | – | – | 30.518 | – | µs |
| F | Sleep-clock frequency | F = 1/T | – | 32.768 | – | kHz |
| Vpp | Peak-to-peak voltage | – | – | 1.8 | – | V |
### Modes and resets
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
Mode and reset functions are basic digital I/Os that meet the performance specifications in [Digital-logic characteristics](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html#nmg1612775927603).
### JTAG
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The following figure shows the JTAG interface timing diagram.
Figure : JTAG interface timing diagram
The supported JTAG interface timing characteristics are listed here.
| Parameter | Parameter | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- |
| t(tckcy) | TCK period | 50 | – | – | ns |
| t(tckh) | TCK pulse width high | 20 | – | – | ns |
| t(tckl) | TCK pulse width low | 20 | – | – | ns |
| t(sutms) | TMS input setup time | 5 | – | – | ns |
| t(htms) | TMS input hold time | 20 | – | – | ns |
| t(sutdi) | TDI input setup time | 5 | – | – | ns |
| t(htdi) | TDI input hold time | 20 | – | – | ns |
| t(do) | TDO data output delay | – | – | 15 | ns |
## System power management interface (SPMI)
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html](https://docs.qualcomm.com/doc/80-73480-1/topic/electrical-specifications.html)
The supported SPMI standards and their exceptions are listed here.
Table : Supported SPMI standards and exceptions
| Applicable standard | Feature exceptions |
| :---: | :---: |
| *MIPI Alliance Specification for System Power Management Interface (SPMI) version 1.0* | None |
Last Published: Mar 09, 2026
[Previous Topic
Pin definitions](https://docs.qualcomm.com/bundle/publicresource/80-73480-1/topics/pin-definitions.md) [Next Topic
Mechanical information](https://docs.qualcomm.com/bundle/publicresource/80-73480-1/topics/mechanical-information.md)