# Pin definitions Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html) This topic explains the pin assignments of the QCS615 chipsets. The figure and table within this topic provide details on pinouts, pad attributes, and their corresponding definitions. ## I/O parameter definitions Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html) The following table lists pad attributes and their descriptions, pad pull details, and the pad voltage groupings used throughout this topic. | Symbol | Description | | --- | --- | | ***Pad attribute*** | ***Pad attribute*** | | AI | Analog input (does not include pad circuitry) | | AO | Analog output (does not include pad circuitry) | | B | Bidirectional digital with CMOS input | | DI | Digital input (CMOS) | | DO | Digital output (CMOS) | | H | High-voltage tolerant | | S | Schmitt trigger input | | Z | High impedance (Hi-Z) output | | ***Pad pull details for digital I/Os*** | ***Pad pull details for digital I/Os*** | | nppdpukp | Programmable pull resistor. The default pull direction is indicated using capital letters and is a prefix to other programmable options:


NP: pdpukp = default no-pull with programmable options following the colon (:)


PD: nppukp = default pull-down with programmable options following the colon (:)


PU: nppdkp = default pull-up with programmable options following the colon (:)


KP: nppdpu = default keeper with programmable options following the colon (:) | | KP | Internal weak keeper device (keepers cannot drive external buses) | | NP | Internal pull | | PU | Internal pull-up device | | PD | Internal pull-down device | | ***Pad voltage groupings for baseband circuits*** | ***Pad voltage groupings for baseband circuits*** | | EBI | Pad group for EBI pads | | PX0 | Power for pad group 0 | | PX1 | Power for pad group 1 | | PX2 | Pad group 2 (SDC2); 1.8 V or 2.95 V | | PX3 | Pad group 3 (most peripherals); 1.8 V | | PX5 | Pad group 5 (GPIO); 1.8 V | | PX6 | Pad group 6 (GPIO); 1.8 V | | PX7 | Pad group 7 (SDC1); 1.8 V | | PX10 | Pad group 10 (UFS\_REF\_CLK and UFS\_RESET); 1.2 V | | PX11 | Pad group 11 (CXO); 1.8 V | | CSI | Supply voltage for MIPI-CSI circuits and I/Os; tied to VDD\_A\_CSI\_X\_1P2 (1.2 V) | | DSI | Supply voltage for MIPI-DSI circuits and I/Os; tied to VDD\_A\_DSI\_1P2 (1.2 V) | ## Pin map Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html) The QCS615 chipsets are available in the pico scale package (FCBGA761+HS). The following figure shows a high-level view of the pin assignments. For more information on package details and to create printed circuit board (PCB) footprint, see [Mechanical information](https://docs.qualcomm.com/doc/80-73480-1/topic/mechanical-information.html). [QCS615 Pin Assignment and GPIO Configuration Spreadsheet (80-73480-1A)](https://docs.qualcomm.com/bundle/80-73480-1A/resource/80-73480-1A.xlsm) lists all QCS615 pad numbers (in alphanumeric order), pad names, pad voltages, pad types, and functional descriptions. Figure : QCS615 pin assignments Page-1 Sheet.2 Sheet.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A NC1 GND EBI0_DMI _0 EBI0_DQ_ 5 EBI0_DQ_ 3 EBI0_DQ_ 8 EBI0_DMI _1 EBI0_DQ_ 10 EBI0_DQ_ 13 DDR_RES ET_N GND EBI1_DQ_1 3 EBI1_DQ_1 0 EBI1_DMI _1 EBI1_DQ_ 8 EBI1_DQ_ 3 EBI1_DQ_ 5 EBI1_DMI _0 GND NC2 A B EBI0_DQ_ 0 EBI0_DQ_ 6 EBI0_DQS _C_0 GND EBI0_DQ_ 15 GND EBI0_DQS _T_1 GND EBI0_DQ_ 12 RESOUT_ N EBI1_DQ_1 2 GND EBI1_DQS _T_1 GND EBI1_DQ_1 5 GND EBI1_DQS _C_0 EBI1_DQ_ 6 EBI1_DQ_1 B C GND EBI0_DQ_ 7 EBI0_DQS _T_0 EBI0_DQ_ 4 EBI0_DQ_ 2 EBI0_DQ_ 14 EBI0_DQ_ 9 EBI0_DQS _C_1 EBI0_DQ_ 11 GND GND EBI1_DQ_1 1 EBI1_DQS _C_1 EBI1_DQ_ 9 EBI1_DQ_1 4 EBI1_DQ_ 2 EBI1_DQ_ 4 EBI1_DQS _T_0 EBI1_DQ_ 7 GND C D WLAN_P WR_EN GND EBI0_DQ_ 1 EBI0_CAL GND GND GND GND GND GND GND GND GND GND GND DNC TDI TCK EBI1_DQ_ 0 D E WLAN1_A DC_I_P WLAN1_A DC_I_N GPIO_10 GPIO_13 EBI0_CA_ CA_4 EBI0_CA_ CA_3 EBI0_CA_ CK_C EBI0_CA_ CKE_1 EBI0_CA_ CS_0 EBI0_CA_ CA_0 EBI1_CA_ CA_1 EBI1_CA_ CS_1 EBI1_CA_ CKE_0 EBI1_CA_ CK_T EBI1_CA_ CA_2 EBI1_CA_ CA_5 SRST_N TRST_N TDO TMS E Legend F WLAN1_A DC_Q_P WLAN1_A DC_Q_N GPIO_11 WCSS_CX M_RFA_C MD_DAT A EBI0_CA_ CA_5 EBI0_CA_ CA_2 EBI0_CA_ CK_T EBI0_CA_ CKE_0 EBI0_CA_ CS_1 EBI0_CA_ CA_1 EBI1_CA_ CA_0 EBI1_CA_ CS_0 EBI1_CA_ CKE_1 EBI1_CA_ CK_C EBI1_CA_ CA_3 EBI1_CA_ CA_4 GND GPIO_16 GPIO_17 F Color Net group G WLAN1_D AC_REXT GND GPIO_12 GND WCSS_CX M_RFA_C MD_CLK UFS_REX T GND GND GND GND GND GND GND GND GND GND VDDPX_7 GPIO_88 DSI0_REX T_PLL DSI0_LN3 _N G EBI1* H WLAN1_D AC_I_N GND GND RF_XO_C LK GND UFS_L0_T XP UFS_REF _CLK VDDA_UF S_1P8 UFS_L0_R XP VDDA_UF S_CORE SDC1_CLK SDC1_DA TA_6 SDC1_DA TA_4 SDC1_RCL K SDC1_DA TA_1 VDDA_DS I0_1P2 GND DSI1_CLK_ N DSI0_LN3 _P H PCI* J WLAN1_D AC_Q_N WLAN1_D AC_I_P GPIO_106 VDDA_W CSS_PLL GND UFS_L0_T XM UFS_RES ET GND UFS_L0_R XM VDDA_UF S_CORE SDC1_CM D SDC1_DA TA_7 SDC1_DA TA_5 SDC1_DA TA_3 SDC1_DA TA_2 SDC1_DA TA_0 GPIO_91 DSI1_CLK_ P GND DSI0_LN2 _N J USB* K WLAN1_D AC_Q_P GND WCSS1_B BD_RFA_ CMD_DA TA VDDA_W CSS_ADC DAC WCSS1_B BD_RFA_ CMD_CLK VDDA_EB I VDDA_EB I VDDA_EB I VDDIO_E BI VDDA_EB I_PLL VDDPX_1 VDDA_CC _EBI VDDPX_1 0 VDDA_PL L_HV_CC _EBI VDDIO_C K_EBI1 VDDPX_3 GPIO_114 DSI0_CLK _N DSI0_LN2 _P K WLAN* L GND GPIO_107 CSI0_A1_L N1_P CSI0_NC_ CLK_P VDDA_W CSS_ADC DAC VDDA_EB I VDDA_EB I VDDIO_E BI VDDIO_E BI GND VDDA_CA MSS_PLL VDDIO_E BI VDDIO_E BI VDDIO_E BI VDDIO_E BI VDDA_DS I0_0P9 GPIO_113 DSI0_CLK _P GND DSI0_LN1_ N L *GPIO/ SSC* M GND CSI0_B1_L N1_N CSI0_A0_ CLK_N VDDPX_3 GND GND GND GND VDDIO_C K_EBI0 GND GND GND GND GND VDDA_DS I0_PLL GPIO_112 GPIO_98 GPIO_89 DSI0_LN1_ P M VDD* N CSI1_NC_ CLK_P GND CSI0_C1_L N2_P CSI0_B0_ LN0_P GND VDD_WC SS VDD_WC SS VDDCX VDDCX VDDCX VDDCX GND GND GND GND GND GPIO_102 GPIO_92 GND DSI0_LN0 _N N GND* P CSI1_A0_ CLK_N CSI0_A2_ LN2_N CSI0_C0_ LN0_N VDDA_CS I0_1P2 VDD_WC SS VDD_WC SS VDDCX VDDCX VDDCX VDDCX VDDCX VDDCX VDDCX VDDCX GND GPIO_103 GPIO_93 GND DSI0_LN0 _P P *CLK* R CSI1_B0_L N0_P GND CSI0_B2_ LN3_P GND GND VDD_APC 0 GND GND GND GND GND GND GND GND GND VDDPX_3 GPIO_81 GPIO_94 GND PCIE_RX_ M R EBI2* T CSI1_C0_L N0_N CSI0_C2_ LN3_N GND VDDA_CS I1_1P2 VDD_APC 0 VDD_APC 0 VDD_APC 0 VDDCX VDDCX VDDCX VDDCX VDDCX VDDCX VDDCX GND GPIO_82 GPIO_95 GPIO_96 PCIE_RX_ P T EBI3* U CSI1_A1_L N1_P GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDDA_PC IE_1P8 GPIO_83 GPIO_97 GND PCIE_REX T U EBI0* V CSI1_B1_L N1_N CSI2_A1_L N1_P CSI2_NC_ CLK_P VDDPX_2 VDD_APC 0 VDD_APC 0 VDD_APC 0 VDD_APC 0 VDD_APC 0 VDD_APC 0 VDDCX VDDCX VDDCX VDDCX GND GPIO_100 CXO PCIE_REF CLK_M PCIE_TX_ M V CSI* W CSI1_C1_L N2_P GND CSI2_B1_L N1_N CSI2_A0_ CLK_N GND GND GND GND GND GND GND GND GND GND GND VDDA_PC IE_CORE GPIO_101 GND PCIE_REF CLK_P PCIE_TX_ P W UFS* Y CSI1_A2_L N2_N CSI2_C1_L N2_P CSI2_B0_ LN0_P VDDA_CS I2_1P2 VDD_APC 0 VDD_APC 0 VDD_APC 0 VDD_APC 0 VDD_APC 0 VDD_APC 0 VDDCX VDDCX VDDCX VDDCX VDDA_US B1_HS_0P 9 VDDPX_11 GPIO_90 GND QREFS_C XO_REXT Y Display Port AA CSI1_B2_L N3_P GND CSI2_A2_ LN2_N CSI2_C0_ LN0_N GND GND GND VDD_APC 0 GND GND VDDCX GND GND GND GND VDDPX_0 GND DP_LANE 2_P DP_REXT DP_LANE 0_P AA AB CSI1_C2_L N3_N CSI2_B2_ LN3_P GND VDDPX_V BIAS_SDC VDDA_AP C_CS_1P8 VDD_APC 0 VDD_APC 0 VDD_APC 0 VDDCX VDDCX VDDCX VDDCX VDDCX VDDCX GND VDDA_US B_HS_1P8 DP_AUX_ P DP_LANE 2_M DP_LANE 0_M AB AC GND GPIO_28 CSI2_C2_ LN3_N GPIO_44 GND GND GND GND GND GND GND GND GND GND VDD_Inter nal1_0P9 VDDA_US B_SS_DP _1P8 DP_AUX_ N DP_LANE 3_P GND DP_LANE1 _P AC AD GPIO_40 GPIO_29 GPIO_45 VDDPX_3 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_Inter nal1_0P9 VDD_Inter nal1_0P9 GND GND USB1_HS_ DP DP_LANE 3_M DP_LANE1 _M AD AE GPIO_41 GPIO_31 GPIO_30 GPIO_46 GND GND GND GND GND GND GND GND GND GND VDD_Inter nal1_0P9 VDD_QFP ROM USB1_HS_ DM USB1_SS_ TPA USB1_HS_ REXT USB0_SS _REXT AE AF GPIO_42 GPIO_20 GPIO_47 VDDPX_3 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_Inter nal1_0P9 VDD_Inter nal1_0P9 GND VDDA_US B0_HS_0P 9 VDDA_US B_SS_DP _CORE USB0_SS _TX0_P USB0_SS _RX0_P AF AG GPIO_43 GPIO_23 GPIO_21 GPIO_48 VDD_APC 1 GND GND GND GND GND GND GND GND GND VDD_Inter nal1_0P9 VDDA_US B_SS_DP _CORE USB0_HS _DP USB0_SS _TX0_M GND USB0_SS _RX0_M AG AH GPIO_22 GPIO_33 GPIO_49 GND VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_Inter nal1_0P9 GND VDDA_US B_HS_3P1 USB0_HS _DM USB0_SS _TX1_P USB0_SS _RX1_P AH AJ GPIO_14 GPIO_32 GPIO_35 GPIO_50 GND GND GND GND GND GND GND GND GND GND GND VDDA_QR EFS_1P25 DNC USB0_SS _TX1_M GND USB0_SS _RX1_M AJ AK GPIO_15 GPIO_34 GND VDDPX_6 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_APC 1 VDD_Inter nal1_0P9 VDD_Inter nal1_0P9 GND VDDPX_3 DNC GND USB0_HS _REXT AK AL GPIO_77 GND GPIO_9 GPIO_87 GND VDD_APC 1 GND GND VDD_APC 1 GND VDD_APC 1 VDD_APC 1 VDDA_LP AAUDIO_ PLL GND VDD_Inter nal2_0P9 GPIO_55 USB0_SS _TPA GND GPIO_104 GPIO_105 AL AM GPIO_80 GPIO_8 GND VDDPX_5 VDDPX_V BIAS_Inter nal GND VDDPX_3 GND GND VDDPX_3 GND VDDPX_0 GND VDD_Inter nal2_0P9 VDDPX_3 GPIO_56 GPIO_18 GPIO_19 GPIO_0 AM AN GPIO_78 GPIO_79 GPIO_7 GPIO_86 GND GND VDDPX_3 SSC_28 SSC_29 SSC_13 SSC_8 SSC_7 GPIO_61 GPIO_72 GPIO_70 GPIO_57 GPIO_53 GND GPIO_4 GPIO_1 AN AP GPIO_73 GPIO_6 GPIO_85 GPIO_38 GPIO_37 GPIO_121 GND SSC_31 SSC_12 SSC_9 SSC_6 SSC_0 GPIO_62 GPIO_71 GPIO_69 GPIO_58 GPIO_54 GPIO_5 GPIO_2 AP AR GPIO_74 GPIO_76 GPIO_26 GPIO_84 GPIO_36 GPIO_109 GPIO_122 SSC_25 SSC_30 SSC_11 GND SSC_1 GPIO_63 GPIO_67 GPIO_66 DNC GPIO_59 DNC MODE_0 GPIO_3 AR AT GPIO_75 GPIO_27 GPIO_25 GPIO_39 GPIO_108 GND SSC_26 SSC_27 SSC_18 SSC_10 SSC_2 SSC_16 GPIO_64 GPIO_68 GPIO_65 GPIO_51 GPIO_60 RESIN_N MODE_1 AT AU GND SDC2_DA TA_0 SDC2_CM D GPIO_24 GPIO_110 GPIO_115 GPIO_117 SSC_24 SSC_21 SSC_14 SSC_3 SSC_17 GND GND GND GND GPIO_52 GND SLEEP_CL K GND AU AV SDC2_DA TA_1 SDC2_CL K SDC2_DA TA_2 GND GPIO_111 GPIO_118 GPIO_119 SSC_22 GND SSC_15 SSC_5 PMIC_SP MI_CLK DNC DNC DNC DNC DNC GND PS_HOLD AV AW NC4 GND SDC2_DA TA_3 GND GPIO_99 GPIO_116 GPIO_120 SSC_23 SSC_20 SSC_19 SSC_4 PMIC_SP MI_DATA GND DNC DNC DNC DNC DNC GND NC3 AW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 ## Pin descriptions Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html) The following table describes the pin functions, pin pull types, and pin voltages. It also provides a mapping of pin numbers and pin names for all the pins on the device. These include general pins, GPIO pins, and power pins. | Pad number | Pad name and/or function | Pad characteristics[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#kxg1605206453609__fn_w2v_dfb_w1c) | Pad characteristics[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#kxg1605206453609__fn_w2v_dfb_w1c) | Functional description | | --- | --- | --- | --- | --- | | Pad number | Pad name and/or function | Voltage | Type | Functional description | | L7 | CSI0\_NC\_CLK\_P | CSI | AI | MIPI CSI 0 (D-PHY), differential clock – positive

MIPI CSI 0 (C-PHY), no
connect | | M6 | CSI0\_A0\_CLK\_N | CSI | AI, AO | MIPI CSI 0 (D-PHY), differential clock – negative

MIPI CSI 0 (C-PHY), trio
lane 0 – A | | L5 | CSI0\_A1\_LN1\_P | CSI | AI, AO | MIPI CSI 0 (D-PHY), differential lane 1 – positive

MIPI CSI 0 (C-PHY),
trio lane 1 – A | | P4 | CSI0\_A2\_LN2\_N | CSI | AI, AO | MIPI CSI 0 (D-PHY), differential lane 2 – negative

MIPI CSI 0 (C-PHY),
trio lane 2 – A | | N7 | CSI0\_B0\_LN0\_P | CSI | AI, AO | MIPI CSI 0 (D-PHY), differential lane 0 – positive

MIPI CSI 0 (C-PHY),
trio lane 0 – B | | M4 | CSI0\_B1\_LN1\_N | CSI | AI, AO | MIPI CSI 0 (D-PHY), differential lane 1 – negative

MIPI CSI 0 (C-PHY),
trio lane 1 – B | | R5 | CSI0\_B2\_LN3\_P | CSI | AI, AO | MIPI CSI 0 (D-PHY), differential lane 3 – positive

MIPI CSI 0 (C-PHY),
trio lane 2 – B | | P6 | CSI0\_C0\_LN0\_N | CSI | AI, AO | MIPI CSI 0 (D-PHY), differential lane 0 – negative

MIPI CSI 0 (C-PHY),
trio lane 0 – C | | N5 | CSI0\_C1\_LN2\_P | CSI | AI, AO | MIPI CSI 0 (D-PHY), differential lane 2 – positive

MIPI CSI 0 (C-PHY),
trio lane 1 – C | | T4 | CSI0\_C2\_LN3\_N | CSI | AI, AO | MIPI CSI 0 (D-PHY), differential lane 3 – negative

MIPI CSI 0 (C-PHY),
trio lane 2 – C | | N1 | CSI1\_NC\_CLK\_P | CSI | AI | MIPI CSI 1 (D-PHY), differential clock – positive

MIPI CSI 1 (C-PHY), no
connect | | P2 | CSI1\_A0\_CLK\_N | CSI | AI, AO | MIPI CSI 1 (D-PHY), differential clock – negative

MIPI CSI 1 (C-PHY), trio
lane 0 – A | | U1 | CSI1\_A1\_LN1\_P | CSI | AI, AO | MIPI CSI 1 (D-PHY), differential lane 1 – positive

MIPI CSI 1 (C-PHY),
trio lane 1 – A | | Y2 | CSI1\_A2\_LN2\_N | CSI | AI, AO | MIPI CSI 1 (D-PHY), differential lane 2 – negative

MIPI CSI 1 (C-PHY),
trio lane 2 – A | | R1 | CSI1\_B0\_LN0\_P | CSI | AI, AO | MIPI CSI 1 (D-PHY), differential lane 0 – positive

MIPI CSI 1 (C-PHY),
trio lane 0 – B | | V2 | CSI1\_B1\_LN1\_N | CSI | AI, AO | MIPI CSI 1 (D-PHY), differential lane 1 – negative

MIPI CSI 1 (C-PHY),
trio lane 1 – B | | AA1 | CSI1\_B2\_LN3\_P | CSI | AI, AO | MIPI CSI 1 (D-PHY), differential lane 3 – positive

MIPI CSI 1 (C-PHY),
trio lane 2 – B | | T2 | CSI1\_C0\_LN0\_N | CSI | AI, AO | MIPI CSI 1 (D-PHY), differential lane 0 – negative

MIPI CSI 1 (C-PHY),
trio lane 0 – C | | W1 | CSI1\_C1\_LN2\_P | CSI | AI, AO | MIPI CSI 1 (D-PHY), differential lane 2 – positive

MIPI CSI 1 (C-PHY),
trio lane 1 – C | | AB2 | CSI1\_C2\_LN3\_N | CSI | AI, AO | MIPI CSI 1 (D-PHY), differential lane 3 – negative

MIPI CSI 1 (C-PHY),
trio lane 2 – C | | V6 | CSI2\_NC\_CLK\_P | CSI | AI | MIPI CSI 2 (D-PHY), differential clock – positive

MIPI CSI 2 (C-PHY), no
connect | | W7 | CSI2\_A0\_CLK\_N | CSI | AI, AO | MIPI CSI 2 (D-PHY), differential clock – negative

MIPI CSI 2 (C-PHY), trio
lane 0 – A | | V4 | CSI2\_A1\_LN1\_P | CSI | AI, AO | MIPI CSI 2 (D-PHY), differential lane 1 – positive

MIPI CSI 2 (C-PHY),
trio lane 1 – A | | AA5 | CSI2\_A2\_LN2\_N | CSI | AI, AO | MIPI CSI 2 (D-PHY), differential lane 2 – negative

MIPI CSI 2 (C-PHY),
trio lane 2 – A | | Y6 | CSI2\_B0\_LN0\_P | CSI | AI, AO | MIPI CSI 2 (D-PHY), differential lane 0 – positive

MIPI CSI 2 (C-PHY),
trio lane 0 – B | | W5 | CSI2\_B1\_LN1\_N | CSI | AI, AO | MIPI CSI 2 (D-PHY), differential lane 1 – negative

MIPI CSI 2 (C-PHY),
trio lane 1 – B | | AB4 | CSI2\_B2\_LN3\_P | CSI | AI, AO | MIPI CSI 2 (D-PHY), differential lane 3 – positive

MIPI CSI 2 (C-PHY),
trio lane 2 – B | | AA7 | CSI2\_C0\_LN0\_N | CSI | AI, AO | MIPI CSI 2 (D-PHY), differential lane 0 – negative

MIPI CSI 2 (C-PHY),
trio lane 0 – C | | Y4 | CSI2\_C1\_LN2\_P | CSI | AI, AO | MIPI CSI 2 (D-PHY), differential lane 2 – positive

MIPI CSI 2 (C-PHY),
trio lane 1 – C | | AC5 | CSI2\_C2\_LN3\_N | CSI | AI, AO | MIPI CSI 2 (D-PHY), differential lane 3 – negative

MIPI CSI 2 (C-PHY),
trio lane 2 – C | | V34 | CXO | PX\_11 | DI | Core crystal oscillator (digital 19.2 MHz system clock) | | AA37 | DP\_REXT | – | AI | External resistor for display port | | AC33 | DP\_AUX\_N | – | AI, AO | DisplayPort auxiliary channel – minus | | AB34 | DP\_AUX\_P | – | AI, AO | DisplayPort auxiliary channel – plus | | AB38 | DP\_LANE0\_M | – | AO | DisplayPort lane 0– minus | | AA39 | DP\_LANE0\_P | – | AO | DisplayPort lane 0– plus | | AD38 | DP\_LANE1\_M | – | AO | DisplayPort lane 1– minus | | AC39 | DP\_LANE1\_P | – | AO | DisplayPort lane 1– plus | | AB36 | DP\_LANE2\_M | – | AO | DisplayPort lane 2– minus | | AA35 | DP\_LANE2\_P | – | AO | DisplayPort lane 2– plus | | AD36 | DP\_LANE3\_M | – | AO | DisplayPort lane 3 – minus | | AC35 | DP\_LANE3\_P | – | AO | DisplayPort lane 3 – plus | | K36 | DSI0\_CLK\_N | DSI | AO | MIPI DSI 0 (D-PHY), differential clock – negative | | L35 | DSI0\_CLK\_P | DSI | AO | MIPI DSI 0 (D-PHY), differential clock – positive | | N39 | DSI0\_LN0\_N | DSI | AI, AO | MIPI DSI 0 (D-PHY), differential lane 0 – negative | | P38 | DSI0\_LN0\_P | DSI | AI, AO | MIPI DSI 0 (D-PHY), differential lane 0 – positive | | L39 | DSI0\_LN1\_N | DSI | AI, AO | MIPI DSI 0 (D-PHY), differential lane 1 – negative | | M38 | DSI0\_LN1\_P | DSI | AI, AO | MIPI DSI 0 (D-PHY), differential lane 1– positive | | J39 | DSI0\_LN2\_N | DSI | AI, AO | MIPI DSI 0 (D-PHY), differential lane 2 – negative | | K38 | DSI0\_LN2\_P | DSI | AI, AO | MIPI DSI 0 (D-PHY), differential lane 2 – positive | | G39 | DSI0\_LN3\_N | DSI | AI, AO | MIPI DSI 0 (D-PHY), differential lane 3 – negative | | H38 | DSI0\_LN3\_P | DSI | AI, AO | MIPI DSI 0 (D-PHY), differential lane 3 – positive | | G37 | DSI0\_REXT\_PLL | DSI | AI | External resistor for DSI0 | | H36 | DSI1\_CLK\_N | DSI | AO | Not used | | J35 | DSI1\_CLK\_P | DSI | AO | Not used | | A19 | DDR\_RESET\_N | PX\_1 | DO | LPDDR4X reset (shared by EBIs) | | E19 | EBI0\_CA\_CA\_0 | PX\_1 | DO | EBI0 LPDDR4X command/address bit 0 | | F20 | EBI0\_CA\_CA\_1 | PX\_1 | DO | EBI0 LPDDR4X command/address bit 1 | | F12 | EBI0\_CA\_CA\_2 | PX\_1 | DO | EBI0 LPDDR4X command/address bit 2 | | E11 | EBI0\_CA\_CA\_3 | PX\_1 | DO | EBI0 LPDDR4X command/address bit 3 | | E9 | EBI0\_CA\_CA\_4 | PX\_1 | DO | EBI0 LPDDR4X command/address bit 4 | | F10 | EBI0\_CA\_CA\_5 | PX\_1 | DO | EBI0 LPDDR4X command/address bit 5 | | E13 | EBI0\_CA\_CK\_C | PX\_1 | DO | EBI0 LPDDR4X differential clock (C) | | F14 | EBI0\_CA\_CK\_T | PX\_1 | DO | EBI0 LPDDR4X differential clock (T) | | F16 | EBI0\_CA\_CKE\_0 | PX\_1 | DO | EBI0 LPDDR4X clock enable 0 | | E15 | EBI0\_CA\_CKE\_1 | PX\_1 | DO | EBI0 LPDDR4X clock enable 1 | | E17 | EBI0\_CA\_CS\_0 | PX\_1 | DO | EBI0 LPDDR4X chip-select 0 | | F18 | EBI0\_CA\_CS\_1 | PX\_1 | DO | EBI0 LPDDR4X chip-select 1 | | D8 | EBI0\_CAL | – | AI | EBI0/1LPDDR4X calibration resistor | | A5 | EBI0\_DMI\_0 | PX\_1 | DO | EBI0 LPDDR4X data mask for byte 0 | | A13 | EBI0\_DMI\_1 | PX\_1 | DO | EBI0 LPDDR4X data mask for byte 1 | | B2 | EBI0\_DQ\_0 | PX\_1 | B | EBI0 LPDDR4X data bit 0 | | D6 | EBI0\_DQ\_1 | PX\_1 | B | EBI0 LPDDR4X data bit 1 | | C9 | EBI0\_DQ\_2 | PX\_1 | B | EBI0 LPDDR4X data bit 2 | | A9 | EBI0\_DQ\_3 | PX\_1 | B | EBI0 LPDDR4X data bit 3 | | C7 | EBI0\_DQ\_4 | PX\_1 | B | EBI0 LPDDR4X data bit 4 | | A7 | EBI0\_DQ\_5 | PX\_1 | B | EBI0 LPDDR4X data bit 5 | | B4 | EBI0\_DQ\_6 | PX\_1 | B | EBI0 LPDDR4X data bit 6 | | C3 | EBI0\_DQ\_7 | PX\_1 | B | EBI0 LPDDR4X data bit 7 | | A11 | EBI0\_DQ\_8 | PX\_1 | B | EBI0 LPDDR4X data bit 8 | | C13 | EBI0\_DQ\_9 | PX\_1 | B | EBI0 LPDDR4X data bit 9 | | A15 | EBI0\_DQ\_10 | PX\_1 | B | EBI0 LPDDR4X data bit 10 | | C17 | EBI0\_DQ\_11 | PX\_1 | B | EBI0 LPDDR4X data bit 11 | | B18 | EBI0\_DQ\_12 | PX\_1 | B | EBI0 LPDDR4X data bit 12 | | A17 | EBI0\_DQ\_13 | PX\_1 | B | EBI0 LPDDR4X data bit 13 | | C11 | EBI0\_DQ\_14 | PX\_1 | B | EBI0 LPDDR4X data bit 14 | | B10 | EBI0\_DQ\_15 | PX\_1 | B | EBI0 LPDDR4X data bit 15 | | B6 | EBI0\_DQS\_C\_0 | PX\_1 | B | EBI0 LPDDR4X differential data strobe for byte 0 (C) | | C15 | EBI0\_DQS\_C\_1 | PX\_1 | B | EBI0 LPDDR4X differential data strobe for byte 1 (C) | | C5 | EBI0\_DQS\_T\_0 | PX\_1 | B | EBI0 LPDDR4X differential data strobe for byte 0 (T) | | B14 | EBI0\_DQS\_T\_1 | PX\_1 | B | EBI0 LPDDR4X differential data strobe for byte 1 (T) | | F22 | EBI1\_CA\_CA\_0 | PX\_1 | DO | EBI1 LPDDR4X command/address bit 0 | | E21 | EBI1\_CA\_CA\_1 | PX\_1 | DO | EBI1 LPDDR4X command/address bit 1 | | E29 | EBI1\_CA\_CA\_2 | PX\_1 | DO | EBI1 LPDDR4X command/address bit 2 | | F30 | EBI1\_CA\_CA\_3 | PX\_1 | DO | EBI1 LPDDR4X command/address bit 3 | | F32 | EBI1\_CA\_CA\_4 | PX\_1 | DO | EBI1 LPDDR4X command/address bit 4 | | E31 | EBI1\_CA\_CA\_5 | PX\_1 | DO | EBI1 LPDDR4X command/address bit 5 | | F28 | EBI1\_CA\_CK\_C | PX\_1 | DO | EBI1 LPDDR4X differential clock (C) | | E27 | EBI1\_CA\_CK\_T | PX\_1 | DO | EBI1 LPDDR4X differential clock (T) | | E25 | EBI1\_CA\_CKE\_0 | PX\_1 | DO | EBI1 LPDDR4X clock enable 0 | | F26 | EBI1\_CA\_CKE\_1 | PX\_1 | DO | EBI1 LPDDR4X clock enable 1 | | F24 | EBI1\_CA\_CS\_0 | PX\_1 | DO | EBI1 LPDDR4X chip-select 0 | | E23 | EBI1\_CA\_CS\_1 | PX\_1 | DO | EBI1 LPDDR4X chip-select 1 | | A35 | EBI1\_DMI\_0 | PX\_1 | DO | EBI1 LPDDR4X data mask for byte 0 | | A27 | EBI1\_DMI\_1 | PX\_1 | DO | EBI1 LPDDR4X data mask for byte 1 | | D38 | EBI1\_DQ\_0 | PX\_1 | B | EBI1 LPDDR4X data bit 0 | | B38 | EBI1\_DQ\_1 | PX\_1 | B | EBI1 LPDDR4X data bit 1 | | C31 | EBI1\_DQ\_2 | PX\_1 | B | EBI1 LPDDR4X data bit 2 | | A31 | EBI1\_DQ\_3 | PX\_1 | B | EBI1 LPDDR4X data bit 3 | | C33 | EBI1\_DQ\_4 | PX\_1 | B | EBI1 LPDDR4X data bit 4 | | A33 | EBI1\_DQ\_5 | PX\_1 | B | EBI1 LPDDR4X data bit 5 | | B36 | EBI1\_DQ\_6 | PX\_1 | B | EBI1 LPDDR4X data bit 6 | | C37 | EBI1\_DQ\_7 | PX\_1 | B | EBI1 LPDDR4X data bit 7 | | A29 | EBI1\_DQ\_8 | PX\_1 | B | EBI1 LPDDR4X data bit 8 | | C27 | EBI1\_DQ\_9 | PX\_1 | B | EBI1 LPDDR4X data bit 9 | | A25 | EBI1\_DQ\_10 | PX\_1 | B | EBI1 LPDDR4X data bit 10 | | C23 | EBI1\_DQ\_11 | PX\_1 | B | EBI1 LPDDR4X data bit 11 | | B22 | EBI1\_DQ\_12 | PX\_1 | B | EBI1 LPDDR4X data bit 12 | | A23 | EBI1\_DQ\_13 | PX\_1 | B | EBI1 LPDDR4X data bit 13 | | C29 | EBI1\_DQ\_14 | PX\_1 | B | EBI1 LPDDR4X data bit 14 | | B30 | EBI1\_DQ\_15 | PX\_1 | B | EBI1 LPDDR4X data bit 15 | | B34 | EBI1\_DQS\_C\_0 | PX\_1 | B | EBI1 LPDDR4X differential data strobe for byte 0 (C) | | C25 | EBI1\_DQS\_C\_1 | PX\_1 | B | EBI1 LPDDR4X differential data strobe for byte 1 (C) | | C35 | EBI1\_DQS\_T\_0 | PX\_1 | B | EBI1 LPDDR4X differential data strobe for byte 0 (T) | | B26 | EBI1\_DQS\_T\_1 | PX\_1 | B | EBI1 LPDDR4X differential data strobe for byte 1 (T) | | AR37 | MODE\_0 | PX\_0 | DI-SPD | Mode control bit 0 – unconnected for mission mode | | AT38 | MODE\_1 | PX\_0 | DI-SPD | Mode control bit 1 – unconnected for mission mode | | V36 | PCIE\_REFCLK\_M | – | AO | PCIe Gen 2 reference clock – minus | | W37 | PCIE\_REFCLK\_P | – | AO | PCIe Gen 2 reference clock – plus | | U39 | PCIE\_REXT | – | AI | External resistor for PCIe | | R39 | PCIE\_RX\_M | – | AI | PCIe Gen 2 receive – minus | | T38 | PCIE\_RX\_P | – | AI | PCIe Gen 2 receive – plus | | V38 | PCIE\_TX\_M | – | AO | PCIe Gen 2 transmit – minus | | W39 | PCIE\_TX\_P | – | AO | PCIe Gen 2 transmit – plus | | AV24 | PMIC\_SPMI\_CLK | PX\_0 | DO | Slave and PBUS interface for PMICs – clock | | AW23 | PMIC\_SPMI\_DATA | PX\_0 | B | Slave and PBUS interface for PMICs – data | | AV38 | PS\_HOLD | PX\_3 | DO | Power-supply hold signal to PMIC | | Y38 | QREFS\_CXO\_REXT | PX\_11 | AI | External resistor for on-die clocking | | AT36 | RESIN\_N | PX\_0 | DI | Reset input | | B20 | RESOUT\_N | PX\_3 | DO | Reset output | | H8 | RF\_XO\_CLK | PX\_3 | DI | WLAN reference clock | | H22 | SDC1\_CLK | PX\_7 | DO | Secure digital controller 1 clock | | J21 | SDC1\_CMD | PX\_7 | B | Secure digital controller 1 command | | J31 | SDC1\_DATA\_0 | PX\_7 | B | Secure digital controller 1 data bit 0 | | H30 | SDC1\_DATA\_1 | PX\_7 | B | Secure digital controller 1 data bit 1 | | J29 | SDC1\_DATA\_2 | PX\_7 | B | Secure digital controller 1 data bit 2 | | J27 | SDC1\_DATA\_3 | PX\_7 | B | Secure digital controller 1 data bit 3 | | H26 | SDC1\_DATA\_4 | PX\_7 | B | Secure digital controller 1 data bit 4 | | J25 | SDC1\_DATA\_5 | PX\_7 | B | Secure digital controller 1 data bit 5 | | H24 | SDC1\_DATA\_6 | PX\_7 | B | Secure digital controller 1 data bit 6 | | J23 | SDC1\_DATA\_7 | PX\_7 | B | Secure digital controller 1 data bit 7 | | H28 | SDC1\_RCLK | PX\_7 | DI | Secure digital controller 1 return clock | | AV4 | SDC2\_CLK | PX\_2 | DO | Secure digital controller 2 clock | | AU5 | SDC2\_CMD | PX\_2 | B | Secure digital controller 2 command | | AU3 | SDC2\_DATA\_0 | PX\_2 | B | Secure digital controller 2 data bit 0 | | AV2 | SDC2\_DATA\_1 | PX\_2 | B | Secure digital controller 2 data bit 1 | | AV6 | SDC2\_DATA\_2 | PX\_2 | B | Secure digital controller 2 data bit 2 | | AW5 | SDC2\_DATA\_3 | PX\_2 | B | Secure digital controller 2 data bit 3 | | AU37 | SLEEP\_CLK | PX\_3 | DI | Sleep clock | | E33 | SRST\_N | PX\_3 | DI-PU | JTAG reset for debug | | D36 | TCK | PX\_3 | DI-PU | JTAG clock input | | D34 | TDI | PX\_3 | DI-



PU:nppdkp | JTAG data input | | E37 | TDO | PX\_3 | DO-Z | JTAG data output | | E39 | TMS | PX\_3 | DI-



PU:nppdkp | JTAG mode select input | | E35 | TRST\_N | PX\_3 | DI-



PD:nppukp | JTAG reset | | J17 | UFS\_L0\_RXM | – | AI | UFS receive lane 0 – minus | | H18 | UFS\_L0\_RXP | – | AI | UFS receive lane 0 – plus | | J11 | UFS\_L0\_TXM | – | AO | UFS transmit lane 0 – minus | | H12 | UFS\_L0\_TXP | – | AO | UFS transmit lane 0 – plus | | H14 | UFS\_REF\_CLK | PX\_10 | DO-Z



PD:nppukp | UFS reference clock | | J13 | UFS\_RESET | PX\_10 | DO-Z



PD:nppukp | UFS reset | | G11 | UFS\_REXT | – | AI | External resistor for UFS | | AH34 | USB0\_HS\_DM | – | AI, AO | USB high-speed 0 data – minus | | AG33 | USB0\_HS\_DP | – | AI, AO | USB high-speed 0 data – plus | | AK38 | USB0\_HS\_REXT | – | AI | External resistor for USB high speed 0 | | AE39 | USB0\_SS\_REXT | – | AI | External resistor for USB SuperSpeed 0 | | AG39 | USB0\_SS\_RX0\_M | | AI | USB SuperSpeed 0 receive lane 0 – minus | | AF38 | USB0\_SS\_RX0\_P | | AI | USB SuperSpeed 0 receive lane 0 – plus | | AJ39 | USB0\_SS\_RX1\_M | | AI | USB SuperSpeed 0 receive lane 1 – minus | | AH38 | USB0\_SS\_RX1\_P | | AI | USB SuperSpeed 0 receive lane 1 – plus | | AG35 | USB0\_SS\_TX0\_M | | AO | USB SuperSpeed 0 transmit lane 0 – minus | | AF36 | USB0\_SS\_TX0\_P | | AO | USB SuperSpeed 0 transmit lane 0 – plus | | AJ35 | USB0\_SS\_TX1\_M | | AO | USB SuperSpeed 0 transmit lane 1 – minus | | AH36 | USB0\_SS\_TX1\_P | | AO | USB SuperSpeed 0 transmit lane 1 – plus | | AE33 | USB1\_HS\_DM | – | AI, AO | USB high-speed 1 data – minus | | AD34 | USB1\_HS\_DP | – | AI, AO | USB high-speed 1 data – plus | | AE37 | USB1\_HS\_REXT | – | AI | External resistor for USB high speed 1 | | G9 | WCSS\_CXM\_RFA\_CMD\_CLK | PX\_3 | DO | WLAN coexistence module command clock (WSI 1.0) – power-on default | | F8 | WCSS\_CXM\_RFA\_CMD\_DATA | PX\_3 | B | WLAN coexistence module command data (WSI 1.0) – power-on default | | K10 | WCSS1\_BBD\_RFA\_CMD\_CLK | PX\_3 | DO | WLAN chain 1 baseband command clock (WSI 2.0) – power-on default | | K6 | WCSS1\_BBD\_RFA\_CMD\_DATA | PX\_3 | B | WLAN chain 1 baseband command data (WSI 2.0) – power-on default | | D2 | WLAN\_PWR\_EN | PX\_3 | DO



PD:nppukp | WLAN power enable | | H2 | WLAN1\_DAC\_I\_N | PX\_3 | AI, AO | WLAN chain 1 digital-to-analog converter, in-phase minus | | J3 | WLAN1\_DAC\_I\_P | PX\_3 | AI, AO | WLAN chain 1 digital-to-analog converter, in-phase plus | | J1 | WLAN1\_DAC\_Q\_N | PX\_3 | AI, AO | WLAN chain 1 digital-to-analog converter, quadrature minus | | K2 | WLAN1\_DAC\_Q\_P | PX\_3 | AI, AO | WLAN chain 1 digital-to-analog converter, quadrature plus | | G1 | WLAN1\_DAC\_REXT | PX\_3 | AI | External resistor for WLAN chain 1 digital-to-analog converter | | E3 | WLAN1\_ADC\_I\_N | PX\_3 | AI, AO | WLAN chain 1 analog-to-digital converter, in-phase minus | | E1 | WLAN1\_ADC\_I\_P | PX\_3 | AI, AO | WLAN chain 1 analog-to-digital converter, in-phase plus | | F4 | WLAN1\_ADC\_Q\_N | PX\_3 | AI, AO | WLAN chain 1 analog-to-digital converter, quadrature minus | | F2 | WLAN1\_ADC\_Q\_P | PX\_3 | AI, AO | WLAN chain 1 analog-to-digital converter, quadrature plus | | | | | | | ^1^ For parameter and acronym definitions, see [Table : I/O description (pad type) parameters](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#lwx1605206318030__table_qrk_mnk_b3b). Note: - GPIO pins can support multiple functions. To assign GPIOs to particular functions as in [Table : Pin descriptions – general pins](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#kxg1605206453609__table_bkv_zjf_rnb), identify all application requirements and map each GPIO to its function. Ensure to avoid GPIO assignment conflicts. See the following table for a list of all supported functions for each GPIO. - Some GPIOs can wake up the SoC from sleep. For more information, see [Table : Pin descriptions–general-purpose input/output ports](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#kxg1605206453609__table_u1k_vdn_tnb). To avoid excessive current leakage, examine each GPIO external connection and programmed configuration. Ensure control of the following factors: - GPIO configuration - Input vs. output - Pull-up or pull-down - External connections - Unused inputs - Connections to high impedance (tri-state) outputs - Unattached connections to external devices For GPIO assignments, see [QCS615 Pin Assignment and GPIO Configuration Spreadsheet (80-73480-1A)](https://docs.qualcomm.com/bundle/80-73480-1A/resource/80-73480-1A.xlsm). It lists all pad names and/or function for QCS615 GPIOs (in numeric order), pad numbers, pad voltages, pull states, and available configurations. | Pad number | Pad name | Configurable function | Pad

characteristics [^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#kxg1605206453609__fn_o3b_dfb_w1c) | Pad

characteristics [^2^](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#kxg1605206453609__fn_o3b_dfb_w1c) | Functional description | Wake-up function | | --- | --- | --- | --- | --- | --- | --- | | Pad number | Pad name | Configurable function | Voltage | Type | Functional description | Wake-up function | | AM38 | GPIO[0] | | 3 | PD:nppukp | Configurable I/O | – | | AM38 | GPIO[0] | QUP\_L0[2] | 3 | PD:nppukp | QUP 2, lane 0: SPI\_ MISO/UART\_CTS/I2C\_SDA/SPI-S\_MOSI | – | | AM38 | GPIO[0] | QDSS\_GPIO\_TRACEDATA\_LOCB[6] | 3 | PD:nppukp | QDSS trace data 6 B | – | | AN39 | GPIO[1] | | 3 | PD:nppukp | Configurable I/O | Y | | AN39 | GPIO[1] | QUP\_L1[2] | 3 | PD:nppukp | QUP 2, lane 1: SPI\_ MOSI/UART\_RFR/I2C\_SCL/SPI-S\_MISO | Y | | AN39 | GPIO[1] | QDSS\_GPIO\_TRACEDATA\_LOCB[7] | 3 | PD:nppukp | QDSS trace data 7 B | Y | | AP38 | GPIO[2] | | 3 | PD:nppukp | Configurable I/O | – | | AP38 | GPIO[2] | QUP\_L2[2] | 3 | PD:nppukp | QUP 2, lane 2: SPI\_ CLK/UART\_TX/SPI-S\_CLK | – | | AP38 | GPIO[2] | QDSS\_GPIO\_TRACEDATA\_LOCB[8] | 3 | PD:nppukp | QDSS trace data 8 B | – | | AR39 | GPIO[3] | | 3 | PD:nppukp | Configurable I/O | Y | | AR39 | GPIO[3] | QUP\_L3[2] | 3 | PD:nppukp | QUP 2, lane 3: SPI\_CS\_ N/UART\_RX/SPI-S\_CS\_N | Y | | AR39 | GPIO[3] | QDSS\_GPIO\_TRACEDATA\_LOCB[9] | 3 | PD:nppukp | QDSS trace data 9 B | Y | | AN37 | GPIO[4] | | 3 | PD:nppukp | Configurable I/O | – | | AN37 | GPIO[4] | QUP\_L0[1] | 3 | PD:nppukp | QUP1, lane 0: I2C\_SDA | – | | AP36 | GPIO[5] | | 3 | PD:nppukp | Configurable I/O | – | | AP36 | GPIO[5] | QUP\_L1[1] | 3 | PD:nppukp | QUP1, lane 1: I2C\_SCL | – | | AP4 | GPIO[6] | | 3 | PD:nppukp | Configurable I/O | – | | AP4 | GPIO[6] | QUP\_L0[6] | 3 | PD:nppukp | QUP 6, lane 0: SPI\_ MISO/UART\_CTS/I2C\_SDA/SPI-S\_MOSI | – | | AP4 | GPIO[6] | QDSS\_GPIO\_TRACEDATA\_LOCA[0] | 3 | PD:nppukp | QDSS trace data 0 A | – | | AN5 | GPIO[7] | | 3 | PD:nppukp | Configurable I/O | Y | | AN5 | GPIO[7] | QUP\_L1[6] | 3 | PD:nppukp | QUP 6, lane 1: SPI\_ MOSI/UART\_RFR/I2C\_SCL/SPI-S\_MISO | Y | | AN5 | GPIO[7] | QDSS\_GPIO\_TRACEDATA\_LOCA[1] | 3 | PD:nppukp | QDSS trace data 1 A | Y | | AM4 | GPIO[8] | | 3 | PD:nppukp | Configurable I/O | – | | AM4 | GPIO[8] | QUP\_L2[6] | 3 | PD:nppukp | QUP 6, lane 2: SPI\_ CLK/UART\_TX/SPI-S\_CLK | – | | AM4 | GPIO[8] | GP\_PDM\_MIRB[1] | 3 | PD:nppukp | General-purpose PDM output 1 B | – | | AM4 | GPIO[8] | QDSS\_GPIO\_TRACEDATA\_LOCA[2] | 3 | PD:nppukp | QDSS trace data 2 A | – | | AL5 | GPIO[9] | | 3 | PD:nppukp | Configurable I/O | Y | | AL5 | GPIO[9] | QUP\_L3[6] | 3 | PD:nppukp | QUP 6, lane 3: SPI\_CS\_ N/UART\_RX/SPI-S\_CS\_N | Y | | AL5 | GPIO[9] | QDSS\_GPIO\_TRACEDATA\_LOCA[3] | 3 | PD:nppukp | QDSS trace data 3 A | Y | | E5 | GPIO[10] | | 3 | PD:nppukp | Configurable I/O | – | | E5 | GPIO[10] | QUP\_L0[7] | 3 | PD:nppukp | QUP 7, lane 0: UART\_ CTS/SPI\_MISO/I2C SDA | – | | F6 | GPIO[11] | | 3 | PD:nppukp | Configurable I/O | Y | | F6 | GPIO[11] | QUP\_L1[7] | 3 | PD:nppukp | QUP 7, lane 1: UART\_ RFR/SPI\_MOSI/I2C\_SCL | Y | | G5 | GPIO[12] | | 3 | PD:nppukp | Configurable I/O | – | | G5 | GPIO[12] | QUP\_L2[7] | 3 | PD:nppukp | QUP7, lane 2: UART\_TX/SPI\_ SCLK | – | | E7 | GPIO[13] | | 3 | PD:nppukp | Configurable I/O | Y | | E7 | GPIO[13] | QUP\_L3[7] | 3 | PD:nppukp | QUP7, lane 3: UART\_RX/SPI\_ CS\_N | Y | | AJ1 | GPIO[14] | | 3 | PD:nppukp | Configurable I/O | Y | | AJ1 | GPIO[14] | QUP\_L0[5] | 3 | PD:nppukp | QUP5, lane 0: I2C\_SDA | Y | | AJ1 | GPIO[14] | QDSS\_GPIO\_TRACECTL\_LOCA | 3 | PD:nppukp | QDSS trace control A | Y | | AK2 | GPIO[15] | | 3 | PD:nppukp | Configurable I/O | – | | AK2 | GPIO[15] | QUP\_L1[5] | 3 | PD:nppukp | QUP5, lane 1: I2C\_SCL | – | | AK2 | GPIO[15] | QDSS\_GPIO\_TRACECLK\_LOCA | 3 | PD:nppukp | QDSS trace clock A | – | | F36 | GPIO[16] | | 3 | PD:nppukp | Configurable I/O | – | | F36 | GPIO[16] | QUP\_L2[0] | 3 | PD:nppukp | QUP0, lane 2: UART\_TX | – | | F38 | GPIO[17] | | 3 | PD:nppukp | Configurable I/O | Y | | F38 | GPIO[17] | QUP\_L3[0] | 3 | PD:nppukp | QUP0, lane 3: UART\_RX | Y | | AM34 | GPIO[18] | | 3 | PD:nppukp | Configurable I/O | – | | AM34 | GPIO[18] | QUP\_L0[3] | 3 | PD:nppukp | QUP3, lane 0: I2C\_SDA | – | | AM36 | GPIO[19] | | 3 | PD:nppukp | Configurable I/O | Y | | AM36 | GPIO[19] | QUP\_L1[3] | 3 | PD:nppukp | QUP3, lane 1: I2C\_SCL | Y | | AF4 | GPIO[20] | | 3 | PD:nppukp | Configurable I/O | – | | AF4 | GPIO[20] | QUP\_L0[4] | 3 | PD:nppukp | QUP4, lane 0: UART\_ CTS/SPI\_MISO/I2C\_SDA | – | | AF4 | GPIO[20] | QDSS\_GPIO\_TRACEDATA\_LOCB[4] | 3 | PD:nppukp | QDSS trace data 4 B | – | | AG5 | GPIO[21] | | 3 | PD:nppukp | Configurable I/O | Y | | AG5 | GPIO[21] | QUP\_L1[4] | 3 | PD:nppukp | QUP4, lane 1: UART\_ RFR/SPI\_MOSI/I2C\_SCL | Y | | AG5 | GPIO[21] | GCC\_GP2\_CLK\_MIRB | 3 | PD:nppukp | Global general-purpose clock 2 B | Y | | AG5 | GPIO[21] | QDSS\_GPIO\_TRACEDATA\_LOCB[5] | 3 | PD:nppukp | QDSS trace data 5 B | Y | | AH2 | GPIO[22] | | 3 | PD:nppukp | Configurable I/O | Y | | AH2 | GPIO[22] | QUP\_L2[4] | 3 | PD:nppukp | QUP4, lane 2: UART\_TX/SPI\_ SCLK | Y | | AH2 | GPIO[22] | GCC\_GP3\_CLK\_MIRB | 3 | PD:nppukp | Global general-purpose clock 3 B | Y | | AG3 | GPIO[23] | | 3 | PD:nppukp | Configurable I/O | – | | AG3 | GPIO[23] | QUP\_L3[4] | 3 | PD:nppukp | QUP4, lane 3: UART\_RX/SPI\_ CS\_N | – | | AU7 | GPIO[24] | | 3 | PD:nppukp | Configurable I/O | – | | AU7 | GPIO[24] | SD\_WRITE\_PROTECT | 3 | PD:nppukp | Secure digital card write protection | – | | AU7 | GPIO[24] | HS1\_MI²S\_SCK | 3 | PD:nppukp | High-speed1 MI²S clock | – | | AT6 | GPIO[25] | | 3 | PD:nppukp | Configurable I/O | – | | AT6 | GPIO[25] | HS1\_MI²S\_WS | 3 | PD:nppukp | High-speed1 MI²S serial data word select | – | | AR5 | GPIO[26] | | 3 | PD:nppukp | Configurable I/O | Y | | AR5 | GPIO[26] | CCI\_ASYNC\_IN0 | 3 | PD:nppukp | Camera control interface async 0 | Y | | AR5 | GPIO[26] | HS1\_MI²S\_DATA0 | 3 | PD:nppukp | High-speed1 MI²S serial data channel 0 | Y | | AT4 | GPIO[27] | | 3 | PD:nppukp | Configurable I/O | – | | AT4 | GPIO[27] | BOOT\_CONFIG[2] | 3 | PD:nppukp | Boot configuration bit 2 | – | | AT4 | GPIO[27] | HS1\_MI²S\_DATA1 | 3 | PD:nppukp | High-speed1 MI²S serial data channel 1 | – | | AC3 | GPIO[28] | | 3 | PD:nppukp | Configurable I/O | – | | AC3 | GPIO[28] | CAM\_MCLK0 | 3 | PD:nppukp | Camera master clock 0 | – | | AC3 | GPIO[28] | QDSS\_GPIO\_TRACEDATA\_LOCA[4] | 3 | PD:nppukp | QDSS trace data 4 A | – | | AD4 | GPIO[29] | | 3 | PD:nppukp | Configurable I/O | – | | AD4 | GPIO[29] | CAM\_MCLK1 | 3 | PD:nppukp | Camera master clock 1 | – | | AD4 | GPIO[29] | GP\_MN | 3 | PD:nppukp | General-purpose M/N: D counter output | – | | AD4 | GPIO[29] | QDSS\_GPIO\_TRACEDATA\_LOCA[5] | 3 | PD:nppukp | QDSS trace data 5 A | – | | AE5 | GPIO[30] | | 3 | PD:nppukp | Configurable I/O | – | | AE5 | GPIO[30] | CAM\_MCLK2 | 3 | PD:nppukp | Camera master clock 2 | – | | AE5 | GPIO[30] | QDSS\_GPIO\_TRACEDATA\_LOCA[6] | 3 | PD:nppukp | QDSS trace data 6 A | – | | AE3 | GPIO[31] | | 3 | PD:nppukp | Configurable I/O | – | | AE3 | GPIO[31] | CAM\_MCLK3 | 3 | PD:nppukp | Camera master clock 3 | – | | AE3 | GPIO[31] | QDSS\_GPIO\_TRACEDATA\_LOCA[7] | 3 | PD:nppukp | QDSS trace data 7 A | – | | AJ3 | GPIO[32] | | 3 | PD:nppukp | Configurable I/O | – | | AJ3 | GPIO[32] | CCI\_I2C\_SDA0 | 3 | PD:nppukp | Dedicated camera control interface I2C 0 serial data | – | | AJ3 | GPIO[32] | QDSS\_GPIO\_TRACEDATA\_LOCA[8] | 3 | PD:nppukp | QDSS trace data 8 A | – | | AH4 | GPIO[33] | | 3 | PD:nppukp | Configurable I/O | – | | AH4 | GPIO[33] | CCI\_I2C\_SCL0 | 3 | PD:nppukp | Dedicated camera control interface I2C 0 clock | – | | AH4 | GPIO[33] | QDSS\_GPIO\_TRACEDATA\_LOCA[9] | 3 | PD:nppukp | QDSS trace data 9 A | – | | AK4 | GPIO[34] | | 3 | PD:nppukp | Configurable I/O | – | | AK4 | GPIO[34] | CCI\_I2C\_SDA1 | 3 | PD:nppukp | Dedicated camera control interface I2C 1 serial data | – | | AK4 | GPIO[34] | QDSS\_GPIO\_TRACEDATA\_LOCA[10] | 3 | PD:nppukp | QDSS trace data 10 A | – | | AJ5 | GPIO[35] | | 3 | PD:nppukp | Configurable I/O | Y | | AJ5 | GPIO[35] | CCI\_I2C\_SCL1 | 3 | PD:nppukp | Dedicated camera control interface I2C 1 clock | Y | | AJ5 | GPIO[35] | QDSS\_GPIO\_TRACEDATA\_LOCA[11] | 3 | PD:nppukp | QDSS trace data 11 A | Y | | AR9 | GPIO[36] | | 3 | PD:nppukp | Configurable I/O | – | | AR9 | GPIO[36] | HS0\_MI²S\_SCK | 3 | PD:nppukp | High-speed0 MI²S clock | – | | AP10 | GPIO[37] | | 3 | PD:nppukp | Configurable I/O | – | | AP10 | GPIO[37] | CCI\_TIMER2 | 3 | PD:nppukp | Camera control interface timer 2 | – | | AP10 | GPIO[37] | HS0\_MI²S\_WS | 3 | PD:nppukp | High-speed0 MI²S serial data word select | – | | AP8 | GPIO[38] | | 3 | PD:nppukp | Configurable I/O | – | | AP8 | GPIO[38] | CCI\_TIMER0 | 3 | PD:nppukp | Camera control interface timer 0 | – | | AP8 | GPIO[38] | HS0\_MI²S\_DATA0 | 3 | PD:nppukp | High-speed0 MI²S serial data channel 0 | – | | AT8 | GPIO[39] | | 3 | PD:nppukp | Configurable I/O | Y | | AT8 | GPIO[39] | CCI\_TIMER1 | 3 | PD:nppukp | Camera control interface timer 1 | Y | | AT8 | GPIO[39] | HS0\_MI²S\_DATA1 | 3 | PD:nppukp | High-speed0 MI²S serial data channel 1 | Y | | AD2 | GPIO[40] | – | 3 | PD:nppukp | Configurable I/O | – | | AE1 | GPIO[41] | | 3 | PD:nppukp | Configurable I/O | Y | | AE1 | GPIO[41] | CCI\_ASYNC\_IN1 | 3 | PD:nppukp | Camera control interface async 1 | Y | | AE1 | GPIO[41] | CCI\_TIMER3 | 3 | PD:nppukp | Camera control interface timer 3 | Y | | AF2 | GPIO[42] | | 3 | PD:nppukp | Configurable I/O | – | | AF2 | GPIO[42] | CCI\_ASYNC\_IN2 | 3 | PD:nppukp | Camera control interface async 2 | – | | AF2 | GPIO[42] | CCI\_TIMER4 | 3 | PD:nppukp | Camera control interface timer 4 | – | | AG1 | GPIO[43] | | 3 | PD:nppukp | Configurable I/O | – | | AG1 | GPIO[43] | FORCED\_USB\_BOOT\_POLARITY\_SEL | 3 | PD:nppukp | Forced USB boot polarity select | – | | AC7 | GPIO[44] | | 3 | PD:nppukp | Configurable I/O | – | | AC7 | GPIO[44] | QSPI\_CS\_N\_0 | 3 | PD:nppukp | Quad-SPI chip-select 0 | – | | AC7 | GPIO[44] | QDSS\_GPIO\_TRACEDATA\_LOCA[12] | 3 | PD:nppukp | QDSS trace data 12 A | – | | AD6 | GPIO[45] | | 3 | PU:nppdkp | Configurable I/O | – | | AD6 | GPIO[45] | QSPI\_DATA0 | 3 | PU:nppdkp | Quad-SPI data bit 0 | – | | AD6 | GPIO[45] | QDSS\_GPIO\_TRACEDATA\_LOCA[13] | 3 | PU:nppdkp | QDSS trace data 13 A | – | | AE7 | GPIO[46] | | 3 | PD:nppukp | Configurable I/O | – | | AE7 | GPIO[46] | QSPI\_DATA1 | 3 | PD:nppukp | Quad-SPI data bit 1 | – | | AE7 | GPIO[46] | QDSS\_GPIO\_TRACEDATA\_LOCA[14] | 3 | PD:nppukp | QDSS trace data 14 A | – | | AF6 | GPIO[47] | | 3 | PD:nppukp | Configurable I/O | Y | | AF6 | GPIO[47] | QSPI\_DATA2 | 3 | PD:nppukp | Quad-SPI data bit 2 | Y | | AF6 | GPIO[47] | QDSS\_GPIO\_TRACEDATA\_LOCA[15] | 3 | PD:nppukp | QDSS trace data 15 A | Y | | AG7 | GPIO[48] | | 3 | PD:nppukp | Configurable I/O | Y | | AG7 | GPIO[48] | QSPI\_CLK | 3 | PD:nppukp | Quad-SPI clock | Y | | AH6 | GPIO[49] | | 3 | PD:nppukp | Configurable I/O | – | | AH6 | GPIO[49] | QSPI\_DATA[3] | 3 | PD:nppukp | Quad-SPI data bit 3 | – | | AJ7 | GPIO[50] | | 3 | PD:nppukp | Configurable I/O | Y | | AJ7 | GPIO[50] | QSPI\_CS\_N\_1 | 3 | PD:nppukp | Quad-SPI chip-select 1 | Y | | AT32 | GPIO[51] | – | 3 | PD:nppukp | Configurable I/O | Y | | AU33 | GPIO[52] | – | 3 | PD:nppukp | Configurable I/O | – | | AN33 | GPIO[53] | – | 3 | PD:nppukp | Configurable I/O | | | AP34 | GPIO[54] | | 3 | PD:nppukp | Configurable I/O | – | | AP34 | GPIO[54] | GP\_PDM\_MIRB[0] | 3 | PD:nppukp | General-purpose PDM output 0 B | – | | AP34 | GPIO[54] | BOOT\_CONFIG[13] | 3 | PD:nppukp | Boot configuration bit 13 | – | | AL31 | GPIO[55] | | 3 | PD:nppukp | Configurable I/O | Y | | AL31 | GPIO[55] | BOOT\_CONFIG[14] | 3 | PD:nppukp | Boot configuration bit 14 | Y | | AM32 | GPIO[56] | | 3 | PD:nppukp | Configurable I/O | Y | | AM32 | GPIO[56] | BOOT\_CONFIG[6] | 3 | PD:nppukp | Boot configuration bit 6 | Y | | AN31 | GPIO[57] | | 3 | PD:nppukp | Configurable I/O | Y | | AN31 | GPIO[57] | GCC\_GP1\_CLK\_MIRA | 3 | PD:nppukp | Global general-purpose clock 1 A | Y | | AN31 | GPIO[57] | BOOT\_CONFIG[0] | 3 | PD:nppukp | Boot configuration bit 0 | Y | | AP32 | GPIO[58] | | 3 | PD:nppukp | Configurable I/O | – | | AP32 | GPIO[58] | GCC\_GP2\_CLK\_MIRA | 3 | PD:nppukp | Global general-purpose clock 2 A | – | | AR33 | GPIO[59] | | 3 | PD:nppukp | Configurable I/O | – | | AR33 | GPIO[59] | GCC\_GP3\_CLK\_MIRA | 3 | PD:nppukp | Global general-purpose clock 3 A | – | | AT34 | GPIO[60] | – | 3 | PD:nppukp | Configurable I/O | Y | | AN25 | GPIO[61] | | 3 | PD:nppukp | Configurable I/O | – | | AN25 | GPIO[61] | BOOT\_CONFIG[10] | 3 | PD:nppukp | Boot configuration bit 10 | – | | AP26 | GPIO[62] | – | 3 | PD:nppukp | Configurable I/O | – | | AR25 | GPIO[63] | | 3 | PD:nppukp | Configurable I/O | – | | AR25 | GPIO[63] | GP\_PDM\_MIRB[2] | 3 | PD:nppukp | General-purpose PDM output 2 B | – | | AR25 | GPIO[63] | BOOT\_CONFIG[11] | 3 | PD:nppukp | Boot configuration bit 11 | – | | AT26 | GPIO[64] | – | 3 | PD:nppukp | Configurable I/O | – | | AT30 | GPIO[65] | | 3 | PD:nppukp | Configurable I/O | – | | AT30 | GPIO[65] | BOOT\_CONFIG[8] | 3 | PD:nppukp | Boot configuration bit 8 | – | | AR29 | GPIO[66] | | 3 | PD:nppukp | Configurable I/O | – | | AR29 | GPIO[66] | GP\_PDM\_MIRA[1] | 3 | PD:nppukp | General-purpose PDM output 1 A | – | | AR27 | GPIO[67] | | 3 | PD:nppukp | Configurable I/O | – | | AR27 | GPIO[67] | BOOT\_CONFIG[9] | 3 | PD:nppukp | Boot configuration bit 9 | – | | AT28 | GPIO[68] | – | 3 | PD:nppukp | Configurable I/O | – | | AP30 | GPIO[69] | | 3 | PD:nppukp | Configurable I/O | – | | AP30 | GPIO[69] | BOOT\_CONFIG[12] | 3 | PD:nppukp | Boot configuration bit 12 | – | | AN29 | GPIO[70] | – | 3 | PD:nppukp | Configurable I/O | – | | AP28 | GPIO[71] | – | 3 | PD:nppukp | Configurable I/O | Y | | AN27 | GPIO[72] | | 3 | PD:nppukp | Configurable I/O | – | | AN27 | GPIO[72] | BOOT\_CONFIG[7] | 3 | PD:nppukp | Boot configuration bit 7 | – | | AP2 | GPIO[73] | – | 6 | PD:nppukp | Configurable I/O | – | | AR1 | GPIO[74] | – | 6 | PD:nppukp | Configurable I/O | – | | AT2 | GPIO[75] | – | 6 | PD:nppukp | Configurable I/O | – | | AR3 | GPIO[76] | – | 3 | PD:nppukp | Configurable I/O | Y | | AL1 | GPIO[77] | – | 5 | PD:nppukp | Configurable I/O | – | | AN1 | GPIO[78] | | 5 | PD:nppukp | Configurable I/O | – | | AN1 | GPIO[78] | GCC\_GP1\_CLK\_MIRB | 5 | PD:nppukp | Global general-purpose clock 1 B | – | | AN3 | GPIO[79] | | 5 | PD:nppukp | Configurable I/O | – | | AN3 | GPIO[79] | GP\_PDM\_MIRA[2] | 5 | PD:nppukp | General-purpose PDM output 2 A | – | | AM2 | GPIO[80] | – | 3 | PD:nppukp | Configurable I/O | Y | | R33 | GPIO[81] | | 3 | PD:nppukp | Configurable I/O | Y | | R33 | GPIO[81] | RGMII\_RXD2 | 3 | PD:nppukp | RGMII receive data 2 | Y | | R33 | GPIO[81] | MDP\_VSYNC\_P\_MIRA | 3 | PD:nppukp | MDP vertical sync – primary A | Y | | R33 | GPIO[81] | QDSS\_GPIO\_TRACEDATA\_LOCB[14] | 3 | PD:nppukp | QDSS trace data 14 B | Y | | T32 | GPIO[82] | | 3 | PD:nppukp | Configurable I/O | Y | | T32 | GPIO[82] | RGMII\_RXD1 | 3 | PD:nppukp | RGMII receive data 1 | Y | | T32 | GPIO[82] | MDP\_VSYNC\_S\_MIRA | 3 | PD:nppukp | MDP vertical sync – secondary A | Y | | T32 | GPIO[82] | QDSS\_GPIO\_TRACEDATA\_LOCB[15] | 3 | PD:nppukp | QDSS trace data 15 B | Y | | U33 | GPIO[83] | | 3 | PD:nppukp | Configurable I/O | Y | | U33 | GPIO[83] | RGMII\_RXD0 | 3 | PD:nppukp | RGMII receive data 0 | Y | | U33 | GPIO[83] | MDP\_VSYNC\_E | 3 | PD:nppukp | MDP vertical sync – external | Y | | U33 | GPIO[83] | QDSS\_CTI\_TRIG0\_OUT\_MIRB | 3 | PD:nppukp | QDSS trigger output 0 B | Y | | AR7 | GPIO[84] | – | 3 | PD:nppukp | Configurable I/O | Y | | AP6 | GPIO[85] | – | 3 | PD:nppukp | Configurable I/O | Y | | AN7 | GPIO[86] | – | 3 | PD:nppukp | Configurable I/O | Y | | AL7 | GPIO[87] | | 3 | PD:nppukp | Configurable I/O | Y | | AL7 | GPIO[87] | BOOT\_CONFIG[15] | 3 | PD:nppukp | Boot configuration bit 15 | Y | | G35 | GPIO[88] | | 3 | PD:nppukp | Configurable I/O | Y | | G35 | GPIO[88] | BOOT\_CONFIG[1] | 3 | PD:nppukp | Boot configuration bit 1 | Y | | G35 | GPIO[88] | USB2PHY\_AC\_EN0 | 3 | PD:nppukp | USB0 AC coupling control | – | | M36 | GPIO[89] | | 3 | PD:nppukp | Configurable I/O | Y | | M36 | GPIO[89] | EMAC\_PHY\_INTR(OPTIONAL) | 3 | PD:nppukp | Bit-banged Ethernet interrupt [^3^](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#kxg1605206453609__fn_dwq_hll_wcc) | Y | | M36 | GPIO[89] | PCIE\_RST\_N(OPTIONAL) | 3 | PD:nppukp | Bit-banged PCIe reset RC output [^3^](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#kxg1605206453609__fn_dwq_hll_wcc) | Y | | M36 | GPIO[89] | USB2PHY\_AC\_EN1 | 3 | PD:nppukp | USB1 AC coupling control | Y | | Y34 | GPIO[90] | | 3 | PU:nppdkp | Configurable I/O | Y | | Y34 | GPIO[90] | MDP\_VSYNC\_P | 3 | PU:nppdkp | MDP vertical sync – primary | Y | | Y34 | GPIO[90] | PCIE\_CLK\_REQ | 3 | PU:nppdkp | PCIe clock request | Y | | J33 | GPIO[91] | – | 3 | PD:nppukp | Configurable I/O | – | | N35 | GPIO[92] | | 3 | PD:nppukp | Configurable I/O | Y | | N35 | GPIO[92] | RGMII\_TXC | 3 | PD:nppukp | RGMII transmit clock signal | Y | | N35 | GPIO[92] | QDSS\_GPIO\_TRACEDATA\_LOCB[10] | 3 | PD:nppukp | QDSS trace data 10 B | Y | | P34 | GPIO[93] | | 3 | PD:nppukp | Configurable I/O | Y | | P34 | GPIO[93] | RGMII\_TXD3 | 3 | PD:nppukp | RGMII transmit data 3 | Y | | P34 | GPIO[93] | QDSS\_GPIO\_TRACEDATA\_LOCB[11] | 3 | PD:nppukp | QDSS trace data 11 B | Y | | R35 | GPIO[94] | | 3 | PD:nppukp | Configurable I/O | Y | | R35 | GPIO[94] | RGMII\_TXD2 | 3 | PD:nppukp | RGMII transmit data 2 | Y | | R35 | GPIO[94] | QDSS\_GPIO\_TRACEDATA\_LOCB[12] | 3 | PD:nppukp | QDSS trace data 12 B | Y | | T34 | GPIO[95] | | 3 | PD:nppukp | Configurable I/O | Y | | T34 | GPIO[95] | RGMII\_TXD1 | 3 | PD:nppukp | RGMII transmit data 1 | Y | | T34 | GPIO[95] | GP\_PDM\_MIRA[0] | 3 | PD:nppukp | General-purpose PDM output 0 A | Y | | T34 | GPIO[95] | QDSS\_GPIO\_TRACEDATA\_LOCB[13] | 3 | PD:nppukp | QDSS trace data 13 B | Y | | T36 | GPIO[96] | | 3 | PD:nppukp | Configurable I/O | Y | | T36 | GPIO[96] | RGMII\_TXD0 | 3 | PD:nppukp | RGMII transmit data 0 | Y | | T36 | GPIO[96] | QDSS\_CTI\_TRIG0\_IN\_MIRB | 3 | PD:nppukp | QDSS trigger input 0 B | Y | | U35 | GPIO[97] | | 3 | PD:nppukp | Configurable I/O | Y | | U35 | GPIO[97] | RGMII\_TX\_CTL | 3 | PD:nppukp | RGMII transmit control | Y | | U35 | GPIO[97] | MDP\_VSYNC\_P\_MIRB | 3 | PD:nppukp | MDP vertical sync – primary B | Y | | U35 | GPIO[97] | QDSS\_CTI\_TRIG1\_OUT\_MIRB | 3 | PD:nppukp | QDSS trigger output 1 B | Y | | M34 | GPIO[98] | | 3 | PD:nppukp | Configurable I/O | Y | | M34 | GPIO[98] | MDP\_VSYNC\_S\_MIRB | 3 | PD:nppukp | MDP vertical sync – secondary B | Y | | M34 | GPIO[98] | QDSS\_CTI\_TRIG1\_IN\_MIRB | 3 | PD:nppukp | QDSS trigger input 1 B | Y | | AW9 | GPIO[99] | | 3 | PD:nppukp | Configurable I/O | Y | | AW9 | GPIO[99] | SD\_CARD\_DET\_N | 3 | PD:nppukp | SD card detect | Y | | V32 | GPIO[100] | | 3 | PD:nppukp | Configurable I/O | Y | | V32 | GPIO[100] | PCIE\_WAKE\_N | 3 | PD:nppukp | PCIe wake | Y | | W33 | GPIO[101] | | 3 | PD:nppukp | Configurable I/O | Y | | W33 | GPIO[101] | FORCED\_USB\_BOOT | 3 | PD:nppukp | Forced USB boot | Y | | N33 | GPIO[102] | | 3 | PD:nppukp | Configurable I/O | Y | | N33 | GPIO[102] | RGMII\_RXC | 3 | PD:nppukp | RGMII receive clock signal | Y | | N33 | GPIO[102] | BOOT\_CONFIG[4] | 3 | PD:nppukp | Boot configuration bit 4 | Y | | P32 | GPIO[103] | | 3 | PD:nppukp | Configurable I/O | Y | | P32 | GPIO[103] | RGMII\_RXD3 | 3 | PD:nppukp | RGMII receive data 3 | Y | | P32 | GPIO[103] | QDSS\_CTI\_TRIG1\_IN\_MIRA | 3 | PD:nppukp | QDSS trigger input 1 A | Y | | AL37 | GPIO[104] | | 3 | PD:nppukp | Configurable I/O | Y | | AL37 | GPIO[104] | USB\_PHY\_PS | 3 | PD:nppukp | USBPHY port select | Y | | AL37 | GPIO[104] | QDSS\_CTI\_TRIG1\_OUT\_MIRA | 3 | PD:nppukp | QDSS trigger output 1 A | Y | | AL37 | GPIO[104] | DP\_HOT\_PLUG\_DETECT | 3 | PD:nppukp | DisplayPort hot plug detect | Y | | AL39 | GPIO[105] | – | 3 | PD:nppukp | Configurable I/O | Y | | J5 | GPIO[106] | – | 3 | PD:nppukp | Configurable I/O | – | | L3 | GPIO[107] | – | 3 | PD:nppukp | Configurable I/O | Y | | AT10 | GPIO[108] | | 3 | PD:nppukp | Configurable I/O | Y | | AT10 | GPIO[108] | PRI\_MI²S\_SCK/PCM1\_CLK/TDM1\_CLK | 3 | PD:nppukp | Primary MI²S clock | Y | | AT10 | GPIO[108] | QDSS\_GPIO\_TRACECLK\_LOCB | 3 | PD:nppukp | QDSS trace clock B | Y | | AR11 | GPIO[109] | | 3 | PD:nppukp | Configurable I/O | – | | AR11 | GPIO[109] | PRI\_MI²S\_WS/PCM1\_SYNC/TDM1\_SYNC | 3 | PD:nppukp | Primary MI²S word select | – | | AR11 | GPIO[109] | QDSS\_GPIO\_TRACECTL\_LOCB | 3 | PD:nppukp | QDSS trace control B | – | | AU9 | GPIO[110] | | 3 | PD:nppukp | Configurable I/O | – | | AU9 | GPIO[110] | PRI\_MI²S\_DATA0/PCM1\_DIN/TDM1\_DIN | 3 | PD:nppukp | Primary MI²S serial data channel 0 | – | | AV10 | GPIO[111] | | 3 | PD:nppukp | Configurable I/O | – | | AV10 | GPIO[111] | PRI\_MI²S\_DATA1/PCM1\_DOUT/TDM1\_DOUT | 3 | PD:nppukp | Primary MI²S serial data channel 1 | – | | M32 | GPIO[112] | | 3 | PD:nppukp | Configurable I/O | Y | | M32 | GPIO[112] | RGMII\_RX\_CTL | 3 | PD:nppukp | RGMII receive control | Y | | M32 | GPIO[112] | QDSS\_CTI\_TRIG0\_OUT\_MIRA | 3 | PD:nppukp | QDSS trigger output 0 A | Y | | L33 | GPIO[113] | | 3 | PD:nppukp | Configurable I/O | Y | | L33 | GPIO[113] | RGMII\_MDC | 3 | PD:nppukp | RGMII management interface clock | Y | | L33 | GPIO[113] | QDSS\_CTI\_TRIG0\_IN\_MIRA | 3 | PD:nppukp | QDSS trigger input 0 A | Y | | K34 | GPIO[114] | | 3 | PD:nppukp | Configurable I/O | – | | K34 | GPIO[114] | RGMII\_MDIO | 3 | PD:nppukp | RGMII management interface I/O | – | | AU11 | GPIO[115] | | 3 | PD:nppukp | Configurable I/O | – | | AU11 | GPIO[115] | TER\_MI²S\_SCK/PCM3\_CLK/TDM3\_CLK | 3 | PD:nppukp | Tertiary MI²S clock | – | | AW11 | GPIO[116] | | 3 | PD:nppukp | Configurable I/O | – | | AW11 | GPIO[116] | TER\_MI²S\_WS/PCM3\_SYNC/TDM3\_SYNC | 3 | PD:nppukp | Tertiary MI²S serial data word select | – | | AU13 | GPIO[117] | | 3 | PD:nppukp | Configurable I/O | Y | | AU13 | GPIO[117] | TER\_MI²S\_DATA0/PCM3\_DIN/TDM3\_DIN | 3 | PD:nppukp | Tertiary MI²S serial data channel 0 | Y | | AU13 | GPIO[117] | QDSS\_GPIO\_TRACEDATA\_LOCB[0] | 3 | PD:nppukp | QDSS trace data 0 B | Y | | AV12 | GPIO[118] | | 3 | PD:nppukp | Configurable I/O | Y | | AV12 | GPIO[118] | TER\_MI²S\_DATA1/PCM3\_DOUT/TDM3\_DOUT | 3 | PD:nppukp | Tertiary MI²S serial data channel 1 | Y | | AV12 | GPIO[118] | QDSS\_GPIO\_TRACEDATA\_LOCB[1] | 3 | PD:nppukp | QDSS trace data 1 B | Y | | AV14 | GPIO[119] | | 3 | PD:nppukp | Configurable I/O | Y | | AV14 | GPIO[119] | QDSS\_GPIO\_TRACEDATA\_LOCB[2] | 3 | PD:nppukp | QDSS trace data 2 B | Y | | AW13 | GPIO[120] | | 3 | PD:nppukp | Configurable I/O | Y | | AW13 | GPIO[120] | QDSS\_GPIO\_TRACEDATA\_LOCB[3] | 3 | PD:nppukp | QDSS trace data 3 B | Y | | AW13 | GPIO[120] | BOOT\_CONFIG[3] | 3 | PD:nppukp | Boot configuration bit 3 | Y | | AP12 | GPIO[121] | | 3 | PD:nppukp | Configurable I/O | Y | | AP12 | GPIO[121] | MCLK1 | 3 | PD:nppukp | Audio master clock 1 | Y | | AR13 | GPIO[122] | | 3 | PD:nppukp | Configurable I/O | Y | | AR13 | GPIO[122] | MCLK2 | 3 | PD:nppukp | Audio master clock 2 | Y | | AP24 | SSC[0] | | 3 | PD:nppukp | SSC I/O 0 | – | | AP24 | SSC[0] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AP24 | SSC[0] | SSC\_QUP\_L0[0] | 3 | PD:nppukp | SSC QUP0, lane 0: UART\_ CTS/I2C\_SDA/SPI\_MISO | – | | AR23 | SSC[1] | | 3 | PD:nppukp | SSC I/O 1 | – | | AR23 | SSC[1] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AR23 | SSC[1] | SSC\_QUP\_L1[0] | 3 | PD:nppukp | SSC QUP0, lane 1: UART\_ RFR/I2C\_SCL/SPI\_MOSI | – | | AT22 | SSC[2] | | 3 | PD:nppukp | SSC I/O 2 | – | | AT22 | SSC[2] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AT22 | SSC[2] | SSC\_QUP\_L0[1] | 3 | PD:nppukp | SSC QUP1, lane 0: UART\_ CTS/I2C\_SDA/SPI\_MISO | – | | AU21 | SSC[3] | | 3 | PD:nppukp | SSC I/O 3 | – | | AU21 | SSC[3] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AU21 | SSC[3] | SSC\_QUP\_L1[1] | 3 | PD:nppukp | SSC QUP1, lane 1: UART\_ RFR/I2C\_SCL/SPI\_MOSI | – | | AW21 | SSC[4] | | 3 | PD:nppukp | SSC I/O 4 | – | | AW21 | SSC[4] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AW21 | SSC[4] | SSC\_QUP\_L2[1] | 3 | PD:nppukp | SSC QUP1, lane 2: UART\_ Tx/SPI\_SCLK | – | | AW21 | SSC[4] | SSC\_QUP\_L6[3] | 3 | PD:nppukp | SSC QUP3, lane 6: SPI\_CS\_3 | – | | AW21 | SSC[4] | SSC\_QUP\_L4[3] | 3 | PD:nppukp | SSC QUP3, lane 4: SPI\_CS\_1 | – | | AV22 | SSC[5] | | 3 | PD:nppukp | SSC I/O 5 | – | | AV22 | SSC[5] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AV22 | SSC[5] | SSC\_QUP\_L3[1] | 3 | PD:nppukp | SSC QUP1, lane 3: UART\_ Rx/SPI\_CS\_0 | – | | AV22 | SSC[5] | SSC\_QUP\_L3[0] | 3 | PD:nppukp | SSC QUP0, lane 3: UART\_ Rx/SPI\_CS\_0 | – | | AV22 | SSC[5] | SSC\_QUP\_L6[2] | 3 | PD:nppukp | SSC QUP2, lane 6: SPI\_CS\_3 | – | | AP22 | SSC[6] | | 3 | PD:nppukp | SSC I/O 6 | – | | AP22 | SSC[6] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AP22 | SSC[6] | SSC\_QUP\_L4[1] | 3 | PD:nppukp | SSC QUP1, lane 4: SPI\_CS\_1 | – | | AP22 | SSC[6] | SSC\_QUP\_L4[2] | 3 | PD:nppukp | SSC QUP2, lane 4: SPI\_CS\_1 | – | | AP22 | SSC[6] | SSC\_QUP\_L2[0] | 3 | PD:nppukp | SSC QUP0, lane 2: UART\_ Tx/SPI\_SCLK | – | | AP22 | SSC[6] | SSC\_QUP\_L0[4]\_B | 3 | PD:nppukp | SSC QUP4, lane 0: UART\_ CTS/I2C\_SDA/SPI\_MISO | – | | AP22 | SSC[6] | SSC\_QUP\_L4[5]\_B | 3 | PD:nppukp | SSC QUP5, lane 4: SPI\_CS\_1 | – | | AN23 | SSC[7] | | 3 | PD:nppukp | SSC I/O 7 | – | | AN23 | SSC[7] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AN23 | SSC[7] | SSC\_QUP\_L5[1] | 3 | PD:nppukp | SSC QUP1, lane 5: SPI\_CS\_2 | – | | AN23 | SSC[7] | SSC\_QUP\_L5[2] | 3 | PD:nppukp | SSC QUP2, lane 5: SPI\_CS\_2 | – | | AN23 | SSC[7] | SSC\_QUP\_L5[3] | 3 | PD:nppukp | SSC QUP3, lane 5: SPI\_CS\_2 | – | | AN23 | SSC[7] | SSC\_QUP\_L1[4]\_B | 3 | PD:nppukp | SSC QUP4, lane 1: UART\_ RFR/I2C\_SCL/SPI\_MOSI | – | | AN21 | SSC[8] | | 3 | PD:nppukp | SSC I/O 8 | – | | AN21 | SSC[8] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AN21 | SSC[8] | SEC\_MI²S\_CLK/PCM2\_CLK/TDM2\_CLK | 3 | PD:nppukp | Secondary MI²S clock | – | | AN21 | SSC[8] | SSC\_QUP\_L0[2] | 3 | PD:nppukp | SSC QUP2, lane 0: UART\_ CTS/I2C\_SDA/SPI\_MISO | – | | AN21 | SSC[8] | SSC\_QUP\_L4[0] | 3 | PD:nppukp | SSC QUP0, lane 4: SPI\_CS\_1 | – | | AP20 | SSC[9] | | 3 | PD:nppukp | SSC I/O 9 | – | | AP20 | SSC[9] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AP20 | SSC[9] | SEC\_MI²S\_WS/PCM2\_SYNC/TDM2\_SYNC | 3 | PD:nppukp | Secondary MI²S serial data word select | – | | AP20 | SSC[9] | SSC\_QUP\_L1[2] | 3 | PD:nppukp | SSC QUP2, lane 1: UART\_ RFR/I2C\_SCL/SPI\_MOSI | – | | AP20 | SSC[9] | SSC\_QUP\_L6[1] | 3 | PD:nppukp | SSC QUP1, lane 6: SPI\_CS3 | – | | AT20 | SSC[10] | | 3 | PD:nppukp | SSC I/O 10 | – | | AT20 | SSC[10] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AT20 | SSC[10] | SEC\_MI²S\_DATA0/PCM2\_DIN/TDM2\_DIN | 3 | PD:nppukp | Secondary MI²S serial data channel 0 | – | | AT20 | SSC[10] | SSC\_QUP\_L2[2] | 3 | PD:nppukp | SSC QUP2, lane 2: UART\_ Tx/SPI\_SCLK | – | | AT20 | SSC[10] | SSC\_QUP\_L6[4] | 3 | PD:nppukp | SSC QUP4, lane 6: SPI\_CS3 | – | | AT20 | SSC[10] | SSC\_QUP\_L6[5] | 3 | PD:nppukp | SSC QUP5, lane 6: SPI\_CS3 | – | | AR19 | SSC[11] | | 3 | PD:nppukp | SSC I/O 11 | – | | AR19 | SSC[11] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AR19 | SSC[11] | SEC\_MI²S\_DATA1/PCM2\_DOUT/TDM2\_DOUT | 3 | PD:nppukp | Secondary MI²S serial data channel 1 | – | | AR19 | SSC[11] | SSC\_QUP\_L3[2] | 3 | PD:nppukp | SSC QUP2, lane 3: UART\_ Rx/SPI\_CS\_0 | – | | AP18 | SSC[12] | | 3 | PD:nppukp | SSC I/O 12 | – | | AP18 | SSC[12] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AP18 | SSC[12] | SSC\_QUP\_L2[3] | 3 | PD:nppukp | SSC QUP3, lane 2: UART\_ Tx/SPI\_SCLK | – | | AN19 | SSC[13] | | 3 | PD:nppukp | SSC I/O 13 | – | | AN19 | SSC[13] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AN19 | SSC[13] | SSC\_QUP\_L3[3] | 3 | PD:nppukp | SSC QUP3, lane 3: UART\_ Rx/SPI\_CS\_0 | – | | AN19 | SSC[13] | SSC\_QUP\_L4[5] | 3 | PD:nppukp | SSC QUP5, lane 4: SPI\_CS\_1 | – | | AU19 | SSC[14] | | 3 | PD:nppukp | SSC I/O 14 | – | | AU19 | SSC[14] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AU19 | SSC[14] | SSC\_QUP\_L2[4] | 3 | PD:nppukp | SSC QUP4, lane 2: UART\_ Tx/SPI\_SCLK | – | | AU19 | SSC[14] | SSC\_QUP\_L0[5] | 3 | PD:nppukp | SSC QUP5, lane 0: UART\_ CTS/I2C\_SDA/SPI\_MISO | – | | AV20 | SSC[15] | | 3 | PD:nppukp | SSC I/O 15 | – | | AV20 | SSC[15] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AV20 | SSC[15] | SSC\_QUP\_L3[4] | 3 | PD:nppukp | SSC QUP4, lane 3: UART\_ Rx/SPI\_CS\_0 | – | | AV20 | SSC[15] | SSC\_QUP\_L1[5] | 3 | PD:nppukp | SSC QUP5, lane 1: UART\_ RFR/I2C\_SCL/SPI\_MOSI | – | | AT24 | SSC[16] | | 3 | PD:nppukp | SSC I/O 16 | – | | AT24 | SSC[16] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AT24 | SSC[16] | SSC\_QUP\_L2[5] | 3 | PD:nppukp | SSC QUP5, lane 2: UART\_ Tx/SPI\_SCLK | – | | AT24 | SSC[16] | SSC\_QUP\_L0[4] | 3 | PD:nppukp | SSC QUP4, lane 0: UART\_ CTS/I2C\_SDA/SPI\_MISO | – | | AT24 | SSC[16] | SSC\_QUP\_L0[3] | 3 | PD:nppukp | SSC QUP3, lane 0: UART\_ CTS/I2C\_SDA/SPI\_MISO | – | | AU23 | SSC[17] | | 3 | PD:nppukp | SSC I/O 17 | – | | AU23 | SSC[17] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AU23 | SSC[17] | SSC\_QUP\_L3[5] | 3 | PD:nppukp | SSC QUP5, lane 3: UART\_ Rx/SPI\_CS\_0 | – | | AU23 | SSC[17] | SSC\_QUP\_L1[4] | 3 | PD:nppukp | SSC QUP4, lane 1: UART\_ RFR/I2C\_SCL/SPI\_MOSI | – | | AU23 | SSC[17] | SSC\_QUP\_L1[3] | 3 | PD:nppukp | SSC QUP3, lane 1: UART\_ RFR/I2C\_SCL/SPI\_MOSI | – | | AT18 | SSC[18] | | 3 | PD:nppukp | SSC I/O 18 | – | | AT18 | SSC[18] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AT18 | SSC[18] | AUD\_SLIMBUS\_CLK | 3 | PD:nppukp | Low-power audio SLIMbus clock | – | | AT18 | SSC[18] | QUI\_MI²S\_SCK/PCM5\_CLK/TDM5\_CLK | 3 | PD:nppukp | Quinary MI²S clock | – | | AW19 | SSC[19] | | 3 | PD:nppukp | SSC I/O 19 | – | | AW19 | SSC[19] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AW19 | SSC[19] | QUI\_MI²S\_MCLK\_A | 3 | PD:nppukp | Quinary MI²S master clock A | – | | AW17 | SSC[20] | | 3 | PD:nppukp | SSC I/O 20 | – | | AW17 | SSC[20] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AW17 | SSC[20] | AUD\_SLIMBUS\_DATA0 | 3 | PD:nppukp | Low-power audio SLIMbus data 0 | – | | AW17 | SSC[20] | QUI\_MI²S\_DATA0/PCM5\_DIN/TDM5\_DIN | 3 | PD:nppukp | Quinary MI²S data 0 | – | | AU17 | SSC[21] | | 3 | PD:nppukp | SSC I/O 21 | – | | AU17 | SSC[21] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AU17 | SSC[21] | AUD\_SLIMBUS\_DATA1 | 3 | PD:nppukp | Low-power audio SLIMbus data 1 | – | | AU17 | SSC[21] | QUI\_MI²S\_WS/PCM5\_SYNC/TDM5\_SYNC | 3 | PD:nppukp | Quinary MI²S word select | – | | AV16 | SSC[22] | | 3 | PD:nppukp | SSC I/O 22 | – | | AV16 | SSC[22] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AV16 | SSC[22] | AUD\_SLIMBUS\_DATA2 | 3 | PD:nppukp | Low-power audio SLIMbus data 2 | – | | AV16 | SSC[22] | QUI\_MI²S\_DATA1/PCM5\_DOUT/TDM5\_DOUT | 3 | PD:nppukp | Quinary MI²S data 1 | – | | AV16 | SSC[22] | MCLK3\_A | 3 | PD:nppukp | Audio master clock 3 - A | – | | AW15 | SSC[23] | | 3 | PD:nppukp | SSC I/O 23 | – | | AW15 | SSC[23] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AW15 | SSC[23] | QUA\_MI²S\_SCK/PCM4\_CLK/TDM4\_CLK | 3 | PD:nppukp | Quaternary MI²S clock | – | | AU15 | SSC[24] | | 3 | PD:nppukp | SSC I/O 24 | – | | AU15 | SSC[24] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AU15 | SSC[24] | QUA\_MI²S\_WS/PCM4\_SYNC/TDM4\_SYNC | 3 | PD:nppukp | Quaternary MI²S serial data word select | – | | AR15 | SSC[25] | | 3 | PD:nppukp | SSC I/O 25 | – | | AR15 | SSC[25] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AR15 | SSC[25] | QUA\_MI²S\_DATA0/PCM4\_DIN/TDM4\_DIN | 3 | PD:nppukp | Quaternary MI²S serial data channel 0 | – | | AT14 | SSC[26] | | 3 | PD:nppukp | SSC I/O 26 | – | | AT14 | SSC[26] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AT14 | SSC[26] | QUA\_MI²S\_DATA1/PCM4\_DOUT/TDM4\_DOUT | 3 | PD:nppukp | Quaternary MI²S serial data channel 1 | – | | AT16 | SSC[27] | | 3 | PD:nppukp | SSC I/O 27 | – | | AT16 | SSC[27] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AT16 | SSC[27] | QUA\_MI²S\_DATA2/TDM4\_DATA2 | 3 | PD:nppukp | Quaternary MI²S serial data channel 2 | – | | AT16 | SSC[27] | BOOT\_CONFIG[5] | 3 | PD:nppukp | Boot configuration bit 5 | – | | AN15 | SSC[28] | | 3 | PD:nppukp | SSC I/O 28 | – | | AN15 | SSC[28] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AN15 | SSC[28] | QUA\_MI²S\_DATA3/TDM4\_DATA3 | 3 | PD:nppukp | Quaternary MI²S serial data channel 3 | – | | AN15 | SSC[28] | QUI\_MI²S\_MCLK\_B | 3 | PD:nppukp | Quinary MI²S master clock B | – | | AN17 | SSC[29] | | 3 | PD:nppukp | SSC I/O 29 | – | | AN17 | SSC[29] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AN17 | SSC[29] | MCLK3\_B | 3 | PD:nppukp | Audio master clock 3 B | – | | AR17 | SSC[30] | | 3 | PD:nppukp | SSC I/O 30 | – | | AR17 | SSC[30] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AR17 | SSC[30] | QCA\_SB\_DATA | 3 | PD:nppukp | SLIMbus data (for Bluetooth/FM) | – | | AP16 | SSC[31] | | 3 | PD:nppukp | SSC I/O 31 | – | | AP16 | SSC[31] | GPIO | 3 | PD:nppukp | Configurable I/O | – | | AP16 | SSC[31] | QCA\_SB\_CLK | 3 | PD:nppukp | SLIMbus clock (for Bluetooth/FM) | – | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ^2^ For parameter and acronym definitions, see [Table : I/O description (pad type) parameters](https://docs.qualcomm.com/doc/80-73480-1/topic/pin-definitions.html#lwx1605206318030__table_qrk_mnk_b3b). ^3^ PCIE\_RST\_N and EMAC\_PHY\_INTR are a software implementation as bit bang. Table : Pin descriptions – Do not connect (DNC), ground, and power-supply pins | Pad number | Pad name | Functional description | | --- | --- | --- | | AE35, AJ33, AK34, AL33, D32, AR31, AR35, AW33, AV32, AW31, AV30, AW29, AV28,
AW27, AV26, AW35, AV34 | DNC | Do not connect; connected internally, do not connect externally. | | A1, A39, AW39, AW1 | NC | No connect; not connected internally. | | A3, A21, A37, AA3, AA9, AA11, AA13, AA17, AA19, AA23, AA25, AA27, AA29, AA33,
AB6, AB30, AC1, AC9, AC11,AC13, AC15, AC17, AC19, AC21, AC23, AC25, AC27, AC37, AD30,
AD32, AE9, AE11, AE13, AE15, AE17, AE19, AE21, AE23, AE25, AE27, AF30, AG11, AG13,
AG15, AG17, AG19, AG21, AG23, AG25, AG27, AG37, AH8, AH30, AJ9, AJ11, AJ13, AJ15,
AJ17, AJ19, AJ21, AJ23, AJ25, AJ27, AJ29, AJ37, AK6, AK30, AK36, AL3, AL9, AL13, AL15,
AL19, AL27, AL35, AM6, AM12, AM16, AM18, AM22, AM26, AN9, AN11, AN35, AP14, AR21,
AT12, AU1, AU25, AU27, AU29, AU31, AU35, AU39, AV8, AV18, AV36, AW3, AW7, AW25, AW37,
B8, B12,B16, B24, B28, B32, C1, C19, C21, C39, D4, D10, D12, D14, D16, D18, D20,
D22,D24, D26, D28, D30, F34,G3, G7, G13, G15, G17, G19, G21, G23, G25, G27, G29,G31,
H4, H6, H10, H34, J9, J15, J37, K4, L1, L19, L37, M2, M10, M12, M14, M16,M20, M22,
M24, M26, M28, N3, N9, N23, N25, N27, N29, N31, N37, P30, P36, R3,R7, R9, R13, R15,
R17, R19, R21, R23, R25, R27, R29, R37, T6, T30, U3, U5, U7,U9, U11, U13, U15, U17,
U19, U21, U23, U25, U27, U29, U37, V30, W3, W9, W11,W13, W15, W17, W19, W21, W23, W25,
W27, W29, W35, Y36 | GND | Ground | | AA15, AB12, AB14, AB16, R11, T10, T12, T14, V10, V12, V14, V16, V18,
V20, Y10, Y12, Y14, Y16, Y18, Y20 | VDD\_APC0 | Power for Kryo Silver application processor | | AD10, AD12, AD14, AD16, AD18, AD20, AD22, AD24, AF10, AF12, AF14, AF16, AF18,
AF20, AF22, AF24, AG9, AH10, AH12, AH14, AH16, AH18, AH20, AH22, AH24, AH26, AK10,
AK12, AK14, AK16, AK18, AK20, AK22, AK24, AL11, AL17, AL21, AL23 | VDD\_APC1 | Power for Kryo Gold application processor | | AC29, AD26, AD28, AE29, AF26, AF28, AG29, AH28, AK26, AK28 | VDD\_Internal1\_0P9 | Power for internal circuits | | AE31 | VDD\_QFPROM | Power for programming the QFPROM | | N11, N13, P10, P12 | VDD\_WCSS | Power for WCSS circuits | | AB10 | VDDA\_APC\_CS\_1P8 | Power for application processor current-sensor 1.8 V circuits | | K24 | VDDA\_CC\_EBI | Power for EBI0/EBI1 clock circuits | | P8 | VDDA\_CSI0\_1P2 | Power for MIPI CSI0 1.2 V circuits | | T8 | VDDA\_CSI1\_1P2 | Power for MIPI CSI1 1.2 V circuits | | Y8 | VDDA\_CSI2\_1P2 | Power for MIPI CSI2 1.2 V circuits | | L31 | VDDA\_DSI0\_0P9 | Power for MIPI DSI0 0.9 V circuits | | H32 | VDDA\_DSI0\_1P2 | Power for MIPI DSI0 1.2 V circuits | | M30 | VDDA\_DSI0\_PLL | Power for MIPI DSI0 PLL circuits | | K12, K14, K16, L11, L13 | VDDA\_EBI | Power for EBI0/EBI1 PHY circuits | | K20 | VDDA\_EBI\_PLL | Power for EBI0/EBI1 PLL circuits | | AL25 | VDDA\_LPAAUDIO\_PLL | Power for LPA AUDIO PLL circuits | | U31 | VDDA\_PCIE\_1P8 | Power for PCIe 1.8 V circuits | | W31 | VDDA\_PCIE\_CORE | Power for PCIe core circuits | | K28 | VDDA\_PLL\_HV\_CC\_EBI | Power for EBI0/EBI1 PLL high-voltage circuits | | AL29 | VDDA\_Internal2\_0P9 | Power for internal 0.9 V circuits | | AM28 | VDDA\_Internal2\_0P9 | Power for internal 0.9 V circuits | | AJ31 | VDDA\_QREFS\_1P25 | Reference voltage for QREFS 1.25 V circuits | | H16 | VDDA\_UFS\_1P8 | Power for UFS 1.8 V circuits | | H20, J19 | VDDA\_UFS\_CORE | Power for UFS core circuits | | AB32 | VDDA\_USB\_HS\_1P8 | Power for USB0/1 high speed (HS) 1.8 V circuits | | AH32 | VDDA\_USB\_HS\_3P1 | Power for USB0/1 HS 3.1 V circuits | | AF32 | VDDA\_USB0\_HS\_0P9 | Power for USB0 high speed (HS) 0.9 V circuits | | Y30 | VDDA\_USB1\_HS\_0P9 | Power for USB1 high speed (HS) 0.9 V circuits | | AF34, AG31 | VDDA\_USB\_SS\_DP\_CORE | Power for USB SS and DisplayPort core circuits | | AC31 | VDDA\_USB\_SS\_DP\_1P8 | Power for USB SS and DisplayPort 1.8 V circuits | | K8, L9 | VDDA\_WCSS\_ADCDAC | Power for WCSS ADC and DAC | | J7 | VDDA\_WCSS\_PLL | Power for WCSS PLL circuits | | L21 | VDDA\_CAMSS\_PLL | Power for CAMSS PLL circuits | | AA21, AB18, AB20, AB22, AB24, AB26, AB28, N15, N17, N19, N21, P14, P16, P18, P20,
P22, P24, P26, P28, T16, T18, T20, T22, T24, T26, T28, V22, V24, V26, V28, Y22, Y24,
Y26, Y28 | VDDCX | Power for digital core circuits, SSC circuits, and multimedia subsystem
circuits | | M18 | VDDIO\_CK\_EBI0 | Power for EBI0 I/O clock circuits | | K30 | VDDIO\_CK\_EBI1 | Power for EBI1 I/O clock circuits | | K18, L15, L17, L23, L25, L27, L29 | VDDIO\_EBI | Power for EBI0/1 I/O memory circuits | | AA31, AM24 | VDDPX\_0 | Power for pad group 0 – control signals | | K22 | VDDPX\_1 | Power for pad group 1 – EBI and DDR input/output pads | | V8 | VDDPX\_2 | Power for pad group 2 - SDC2 pads | | AD8, AF8, AK32, AM14, AM20, AM30, AN13, K32, M8, R31 | VDDPX\_3 | Power for pad group 3 – most I/O pads | | AM8 | VDDPX\_5 | Power for pad group 5 – GPIO pads | | AK8 | VDDPX\_6 | Power for pad group 6 – GPIO pads | | G33 | VDDPX\_7 | Power for pad group 7 – SDC1 pads | | K26 | VDDPX\_10 | Power for pad group 10 – UFS | | Y32 | VDDPX\_11 | Power for pad group 11 – CXO | | AB8 | VDDPX\_VBIAS\_SDC | Reference voltage for SDC | | AM10 | VDDPX\_VBIAS\_Internal | Connect to ground using 100 Ω resistor | Last Published: Mar 09, 2026 [Previous Topic Introduction](https://docs.qualcomm.com/bundle/publicresource/80-73480-1/topics/Introduction.md) [Next Topic Electrical specifications](https://docs.qualcomm.com/bundle/publicresource/80-73480-1/topics/electrical-specifications.md)