# Overview
Source: [https://docs.qualcomm.com/doc/80-78832-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-78832-1/topic/introduction.html)
This topic provides the module component information, high-level functional block
diagram, and the device features.
## Product overview
Source: [https://docs.qualcomm.com/doc/80-78832-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-78832-1/topic/introduction.html)
Powered by Qualcomm high performance 1x1 2.4 GHz Wi-Fi 6/Bluetooth 5.4/802.15.4 combo
all-in-one SoC QCC748, Qualcomm QCC748M LGA module is
purposely designed to pack processing capabilities, Wi-Fi/Bluetooth/802.15.4 combo
connectivity, and on-module memory into a single 46-pin LGA form factor.
QCC748M has an integrated powerful 32‑bit RISC-V processor with FPU and DSP
running up to 325 MHz, on-chip 484 KB SRAM and 128 KB ROM, optional 4/8MB pSRAM, and
8/16MB flash System-in-Package (SiP), multimedia features such as audio and video codec
and interfaces, and 35x multiplexed GPIO rich peripherals. Its all-in-one design and
capability contribute to reduced costs and enhanced performance, making it an attractive
choice for IoT edge devices requiring single chip solution.
QCC748M operates in hostless mode, capable of running both the protocol
stack all the way to application level as well as IoT applications without requiring an
external MCU. Built on FreeRTOS, its software SDK is open-sourced on codelinaro coupled
with VS Code IDE market extension to facilitate rapid IoT application development. It
can also be used as an IoT connectivity transceiver in hosted mode with an external host
running all upper protocol stacks and applications.
## QCC748M functional block diagram
QCC748M integrates 8/16/32MB 3x4 WSON NOR Flash and optional 32KHz RTC
crystal. The design also supports PCB antenna to allow customized antenna implementation
on the motherboard. The block diagram is shown below.

Note:
- To support BLE connection retention in low power mode, connect an external 32KHz
sleep clock source crystal to GPIO 16 and GPIO 17, or an oscillator to GPIO 17.
For further details, please consult the Qualcomm support team.
- Power-on sequence for bootstrap pins CHIP\_EN and Boot (GPIO2): The
requirement is that the CHIP\_EN pin should come up after a 3.3ms delay from
the Boot pin. To achieve this, an RC circuit on the CHIP\_EN pin is required
in the customer design for hostless mode. In hosted mode, this power-up
sequence should be managed by the MCU pin connected to the CHIP\_EN pin. For
further details, please consult the Qualcomm support team.
## QCC748M features
Source: [https://docs.qualcomm.com/doc/80-78832-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-78832-1/topic/introduction.html)
| Features | Capability | Capability | Capability | Capability |
| --- | --- | --- | --- | --- |
| Microcontroller | 32‑bit RISC-V processor up to
325 MHz | 32‑bit RISC-V processor up to
325 MHz | 32‑bit RISC-V processor up to
325 MHz | 32‑bit RISC-V processor up to
325 MHz |
| On-chip Memory |