# USB
Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/106_USB.html](https://docs.qualcomm.com/doc/80-88500-4/topic/106_USB.html)
The Qualcomm Robotics RB5 supports super speed (SS) USB (Gen2) controllers. The USB 3.1
core is supported.
Figure : USB Block Diagram
Table : Supported features on USB hardware
| Feature | Support | Description |
| --- | --- | --- |
| USB 3.1 cores | 2 (Gen2) | Two super speed (SS) USB (Gen2) controllers |
| USB DP PHY | 1 |
- Only one SS-USB + DP combo PHY
- No external switch is needed for supporting SS-USB + DP (two-lane)
concurrency
|
| VBUS indication | Software | VBUS USB PHY input connection is not required |
| HS/SS-IC core | N/A | No HS/SS-IC core |
| PHY access methods | AHB2PHY | Allows PHY access through the AHB2PHY path |
| Integrated USB Type-C capability | Yes | Supported if PM8150B is used |
| Integrated SS-USB lane switch | Yes | No external switch is needed to select the proper SS-USB Tx/Rx pins (for USB
Type-C); this applies only to the primary USB controller |
- **[USB memory addresses](https://docs.qualcomm.com/doc/80-88500-4/topic/108_Hardware_specifications.html)**
The USB host controller uses the memory addresses to find a USB device and communicate with it.
- **[USB clocks and interrupts](https://docs.qualcomm.com/doc/80-88500-4/topic/usb_clocks_and_interrupts.html)**
The USB and USB PHY primary and secondary controller clocks operate at different frequencies based on the speed modes (HS and SS). The controller clocks also manage the various reset mechanisms and interrupts for USB and USB SS-PHY and HS-PHY.
- **[USB power management](https://docs.qualcomm.com/doc/80-88500-4/topic/111_USB_power_management.html)**
The USB power management helps assess the impact of power supply and consumption in the system when USB is being used.
- **[Software specifications](https://docs.qualcomm.com/doc/80-88500-4/topic/109_Software_specifications.html)**
The USB software uses Linux kernel 5.4. The kernel should be configured to enable USB support and drive the USB connection on the device.
- **[USB composition](https://docs.qualcomm.com/doc/80-88500-4/topic/110_USB_composition.html)**
The default USB composition is 0x90B8 – Diag + DUN + RMNET + DPL + ADB.
- **[MTP function over FFS](https://docs.qualcomm.com/doc/80-88500-4/topic/113_MTP_function_over_FFS.html)**
The usage of the f\_mtp driver has been replaced with the f\_fs driver.
- **[USB Type-C power delivery](https://docs.qualcomm.com/doc/80-88500-4/topic/114_USB_Type_C.html)**
The USB Type-C can transmit both data and power using a single cable. PM8150B handles the USB Type-C power delivery (PD) detection.
- **[USB analog audio](https://docs.qualcomm.com/doc/80-88500-4/topic/115_USB_analog_audio.html)**
The USB Type-C specification introduces the ability to detect audio adapter accessories. It includes a an adapter for 3.5 mm audio headset jack.
- **[USB charging](https://docs.qualcomm.com/doc/80-88500-4/topic/116_USB_charging.html)**
The USB Type-C charging rate is 5 V at 1.5 A and 3 A, which supports fast charging.
- **[USB and DisplayPort concurrency](https://docs.qualcomm.com/doc/80-88500-4/topic/117_USB_and_DisplayPort_concurrency.html)**
The DisplayPort can use the two and four high-speed data lanes in USB-Type-C and provide 4K ˟ 2K display resolution at 60 fps with USB3 concurrency.
- **[USB KPIs](https://docs.qualcomm.com/doc/80-88500-4/topic/118_USB_KPIs.html)**
The USB key performance indicators (KPI) are the test platform (MTP) performance numbers and test setup that includes the secondary boot image with Interactive mode.
- **[USB DWC3 driver](https://docs.qualcomm.com/doc/80-88500-4/topic/119_USB_DWC3_driver.html)**
The DWC3 driver is open source and supports the subsystem high speed (HS), full speed (FS), and low speed (LS) modes.
**Parent Topic:** [Wired connectivity](https://docs.qualcomm.com/doc/80-88500-4/topic/100_Wired_connectivity.html)
Last Published: Aug 18, 2023
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USB memory addresses](https://docs.qualcomm.com/bundle/publicresource/80-88500-4/topics/108_Hardware_specifications.md)