# DLBC

Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/149_DLBC.html](https://docs.qualcomm.com/doc/80-88500-4/topic/149_DLBC.html)

The deep learning bandwidth compression (DLBC) is an internal compression for private
      Qualcomm^®^ Hexagon™ Tensor Accelerator (HTA) data and is not visible to any SoC
    cores outside the HTA.

The bandwidth to and from the double data rate (DDR) is compressed; the DDR footprint is not
      compressed.

The main benefits include the following:

- Reduces DDR bandwidth usage by the HTA (more bandwidth available to other cores)
- Reduces DDR power consumption due to HTA bandwidth reduction

Lossless compression (no degradation in accuracy due to compression) takes places. Also, there is a noticeable DDR bandwidth/power reduction when applied to the activation data.

**Parent Topic:** [Qualcomm® Hexagon™ Tensor Accelerator](https://docs.qualcomm.com/doc/80-88500-4/topic/147_HTA.html)

Last Published: Aug 18, 2023

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