# GPIO registers configuration Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/20_GPIO_registers_configuration.html](https://docs.qualcomm.com/doc/80-88500-4/topic/20_GPIO_registers_configuration.html) The GPIO control registers are part of the top-level mode multiplexer (TLMM) controller in the SOC architecture. The TLMM\_GPIO\_CFGn registers control the configuration of GPIOs. The table lists the bitfields of the TLMM\_GPIO\_CFGn registers. Table : TLMM_GPIO_CFGn register bitfield | Bit | Name | Description | | --- | --- | --- | | 31:11 | Reserved | Reserved field | | 10 | GPIO\_HIHYS\_EN | Controls the hihys\_en for GPIO[n]

0 – Disable

1 – Enable

| | 9 | GPIO\_OE | Controls the output enable (OE) for GPIO[n] when GPIO[n] is in GPIO mode

0 – Input

1 – Output

| | 8:6 | DRV\_STRENGTH | Controls the GPIO pad drive strength; the drive strength applies regardless of the FUNC\_SEL field selection.

000 – 2 mA

001 – 4 mA

010 – 6 mA

011 – 8 mA

100 – 10 mA

101 – 12 mA

110 – 14 mA

111 – 16 mA

| | 5:2 | FUNC\_SEL | Controls the function of the GPIO pad (many GPIO pads have one or more functional hardware interfaces behind them).

Set this field to the appropriate value for the required function. When this field is set to 0, the pad is in GPIO mode.

For a list of alternate functions, see QRB5165 Pin Assignment and GPIO
Configuration Spreadsheet(80-PV086-1A). | | 1:0 | GPIO\_PULL | Controls the pull of a GPIO pad. GPIO pads can be configured to employ an internal weak pull up, pull down, keeper, or no-pull function. The pull applies regardless of the FUNC\_SEL field selection.

00 – No pull

01 – Pull down (PD)

10 – Keeper

11 – Pull up (PU)

| Table : TLMM_GPIO_LP_CFGn bitfield. The TLMM_GPIO_LP_CFGn registers are used to store the low-power configuration of GPIOs. These registers are initialized during boot. When the driver invokes the TLMM API to place a GPIO into an inactive state, the configuration data stored in this register is retrieved and written to the TLMM_GPIO_CFGn register. | Bits | Name | Description | | --- | --- | --- | | 31:12 | Reserved | Reserved field | | 11:0 | GPIO\_LP\_CFG | Stores the low-power configuration of GPIO n. | ## Input and output When the FUNC\_SEL bit of a GPIO is set to 0, the GPIO is used as a general-purpose pin, and it can be used as input or output. The GPIO\_OE bit of the TLMM\_GPIO\_CFGn register controls the direction. - When this bit is set to 1, the pin is used as an output pin. If the bit is set to 0, the pin is used as an input pin. - When a GPIO is set as output, bit 1 of the TLMM\_GPIO\_IN\_OUTn register controls its state. When set as input, the state of a GPIO can be read from bit 0 in the same register. The table lists the bitfields of the TLMM\_GPIO\_IN\_OUTn register. Table : TLMM_GPIO_IN_OUTn register bitfield | Bit | Name | Description | | --- | --- | --- | | 31:2 | Reserved | Reserved field | | 1 | GPIO\_OUT | Controls the output state of an output pin

0 – Low

1 – High

| | 0 | GPIO\_IN | Reads the state of an input pin | ## Interrupt All GPIOs can be set up as interrupt sources. The registers TLMM\_GPIO\_INTR\_CFGn, n = 0…179 control the GPIO interrupt functionality. Table : TLMM_GPIO_INTR_CFGn register bitfield | Bit | Name | Description | | --- | --- | --- | | 31:9 | Reserved | Reserved field | | 8 | DIR\_CONN\_EN | Determines the TLMM that GPIO[n] uses as a direct connect interrupt. The values are:

0 – Disable; disables the GPIO as a direct connect interrupt

1 – Enable; enables the GPIO as a direct connect interrupt

| | 7:5 | TARGET\_PROC | Determines to which processor a summary interrupt from GPIO[n] is routed

0x0 – SENSORS; routes the GPIO signal to the SENSORS summary interrupt

0x1 – LPA_DSP; routes the GPIO signal to the LPASS summary interrupt

0x2 – RPM; routes the GPIO signal to the RPM summary interrupt

0x3 – HMSS; routes the GPIO signal to the HMSS summary interrupt

0x4 – GSS; routes the GPIO signal to the GSS summary interrupt

0x5 – TZ; routes the GPIO signal to the TrustZone summary interrupt

0x7 – None; does not route the GPIO signal to any processor subsystem (default)

| | 4 | INTR\_RAW\_STATUS\_EN | Enables the RAW status for the summary interrupt on GPIO[n]. This field is a power-saving mechanism. Leave this bit disabled unless it is required. The values are:

0 – Disable

1 – Enable

| | 3:2 | INTR\_DECT\_CTL | Controls the edge or level detection of the interrupt controller.

The values are:

00 – Level

01 – Positive edge

10 – Negative edge

11 – Dual edge

| | 1 | INTR\_POL\_CTL | Controls the polarity detection of the interrupt controller.

The values are:

0 – Polarity 0; active low

1 – Polarity 1; active high

| | 0 | INTR\_ENABLE | Controls whether GPIO[n] generates a summary interrupt. The values are:

0 – Disable

1 – Enable

| The INTR\_POL\_CTL and INTR\_DETC\_CTL bitfields control the trigger type of an interrupt. Setting or clearing the INTR\_ENABLE field enables or disables the corresponding GPIO interrupt. The interrupt status is recorded in the TLMM\_GPIO\_INTR\_STATUSn, n = 0…179 registers. Table : TLMM_GPIO_INTR_STATUS n register bitfield | Bit | Name | Description | | --- | --- | --- | | 31:1 | Reserved | Reserved field | | 0 | INTR\_STATUS | When read, returns the interrupt status of GPIO[n]

0 – The interrupt is not active

1 – The interrupt is active

When written, clears or sets the interrupt for GPIO[n]

0 – Clear the interrupt

1 – Set the interrupt

| **Parent Topic:** [GPIO pad configuration](https://docs.qualcomm.com/doc/80-88500-4/topic/19_Hardware_overview.html) Last Published: Aug 18, 2023 [Previous Topic GPIO pad configuration](https://docs.qualcomm.com/bundle/publicresource/80-88500-4/topics/19_Hardware_overview.md) [Next Topic GPIO software driver code overview](https://docs.qualcomm.com/bundle/publicresource/80-88500-4/topics/21_Software_overview.md)