# Power
Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/38_Power.html](https://docs.qualcomm.com/doc/80-88500-4/topic/38_Power.html)
To supply power to the CPU, the application subsystem (APSS) uses the APC0 and APC1
power rails. Similar power rails are used to maintain power supply to the other
subsystems.
The table lists the subsystems for which power supply is maintained. Additionally, some of
the subsystems support power features that enhance the power consumption.
Table : Power features
| Features/subsystem | Description |
| --- | --- |
| 7-nm FinFET technology | Improved process maturity |
| Application subsystem (APSS or CPU subsystem (CPUSS)) |
- 15% performance increase with no power degradation when operating at lower
legacy performance.
- CPU configuration: 4 (Silver) + 3 (Gold) + 1 (Prime) clusters
- CPU power rails: APC0 for Silver cluster, APC1 for Gold cluster
- Prime with dedicated PLL
- L3 cache: 4 MB
- Frequencies – Silver (1.78 GHz), Gold (2.23+ GHz), Prime (2.7+ GHz)
|
| Double data rate subsystem (DDRSS) |
- Supports combo LPDDR4 (2.09 GHz) and LPDDR5 (2.73 GHz)
- Supports Deep Sleep mode for LPDDR5 DRAM
|
| Graphics processing unit subsystem (GPUSS) |
- Graphic core power efficiency improvement (~15%)
- SVS_L2 corner
|
| Display | Inline rotation v2: Rotates and displays in a single pass without using system
cache or DDR read/write |
| Neural processing unit subsystem (NPUSS) |
- Improved NPU230
- 2 cores
- L2 cache (256 KB)
- 1.0 GHz at Fmax (Turbo)
|
| Low-power audio subsystem (LPASS) |
- Audio architecture to support Qualcomm® Voice Activation in Island mode
- Shared LPI_CX and LPI_MX with sensor subsystem and LPI_MX with always on
subsystem (AOSS)
|
| ComputeSS | Adds limits management hardening (LMh) for Qualcomm® Hexagon™ Vector eXtensions
(HVX) |
| CameraSS |
- Architecture upgrade targeting low multimedia (MM) voltage operation across
camera use cases
- 2pix/cycle at IFEs, 4pix/cycle at IPE
- Single IPE
- 6 X 4-lane camera sensor interface (CSI)
- Bandwidth (BW) reduction by UBWC 4.0
|
| Legacy power features | Optimized features from the previous generation:
- XO Shutdown
- CX Power Collapse
- Subsystem power collapse clock gating
- Resource power management hardening (RPMh) for power state transitions
- Dynamic clock and voltage scaling (DCVS)
- UBWC
- System efficiency and cache architecture optimization
|
The figure shows the interactions among various subsystems and their core power domains
through system buses.
Figure : Power architecture
The table lists the various subsystems and their core power domains within the power
architecture:
| **1. Application processor or CPU subsystem** | **1. Application processor or CPU subsystem** | **2. Always-on subsystem** | **2. Always-on subsystem** | **2. Always-on subsystem** |
| --- | --- | --- | --- | --- |
| Silver CPU | VDD\_APC0 | Core circuits | VDD\_SSC\_MX | VDD\_SSC\_MX |
| Gold CPU | VDD\_APC1 | | | |
| L3 | VDD\_APC0 | | | |
| **3. Multimedia subsystem** | **3. Multimedia subsystem** | **4. Low-power audio subsystem** | **4. Low-power audio subsystem** | **4. Low-power audio subsystem** |
| Adreno 650 core | VDD\_GFX | Core circuits | VDD\_CX | VDD\_CX |
| GMEM | VDDMX | Audio DSP | VDD\_LPI\_CX | VDD\_LPI\_CX |
| Camera | VDDMM | | | |
| Video | VDDMM | | | |
| Display (DPU) | VDDMM | | | |
| **5. Peripheral subsystem** | **5. Peripheral subsystem** | **6. Sensor subsystem** | **6. Sensor subsystem** | **6. Sensor subsystem** |
| Core circuits | VDD\_CX | Sensor core | VDD\_LPI\_CX | VDD\_LPI\_CX |
| | | Sensor DSP | VDD\_LPI\_CX | VDD\_LPI\_CX |
| | | L2 | VDD\_LPI\_MX | VDD\_LPI\_MX |
| **7. DDR subsystem** | **7. DDR subsystem** | **8. Compute subsystem** | **8. Compute subsystem** | **8. Compute subsystem** |
| PHY | VDDA\_EBI | Core circuits | VDD\_CX | VDD\_CX |
| I/O | VDDIO\_EBI | Compute DSP | VDD\_CX | VDD\_CX |
| System Cache | VDD\_MX | L2 | VDD\_MX | VDD\_MX |
| System Cache | VDD\_MX | HVX | VDD\_CX | VDD\_CX |
| **9. Secure processor** | **9. Secure processor** | **10. NPU subsystem** | **10. NPU subsystem** | **10. NPU subsystem** |
| Core circuits | VDDPX\_13 | NPU | VDD\_CX | VDD\_CX |
| QFPROM | VDD\_QFPROM\_SP | Memory | VDD\_MX | VDD\_MX |
| | | | | |
| | | | | |
- **[CPU subsystem features](https://docs.qualcomm.com/doc/80-88500-4/topic/39_CPU_subsystem_features.html)**
Qualcomm^®^ Kryo™ CPU 585 is the CPU subsystem (CPUSS) that supports customized 64‑bit Arm v8.2 architecture-compliant octa-core application processor . It operates in Prime, Gold and Silver clusters.
- **[Double data rate subsystem and voltage supply](https://docs.qualcomm.com/doc/80-88500-4/topic/40_DDRSS.html)**
There are two supported voltage levels (SVS/Turbo) for the voltage supply (VDDA) compatibility with the LPDDR5 I/O performance.
- **[Power grid](https://docs.qualcomm.com/doc/80-88500-4/topic/41_Power_grid.html)**
The power grid supplies power to various power domains, which can be switched on and off on the supported reference device.
- **[PMIC](https://docs.qualcomm.com/doc/80-88500-4/topic/42_PMIC.html)**
There are two types of power management integrated circuits (PMIC) – PM8250 and PM8150L/PM8150A, and PM8150B.
- **[Resource power manager hardening](https://docs.qualcomm.com/doc/80-88500-4/topic/45_RPMh.html)**
The resource power manager hardening (RPMh) is a hardware-based solution with software assistance. With the hardware-accelerated transitions, RPMh achieves significant improvement in transition latency.
**Parent Topic:** [System](https://docs.qualcomm.com/doc/80-88500-4/topic/7_System.html)
Last Published: Aug 18, 2023
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