# Hardware reset
Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/73_Hardware_reset.html](https://docs.qualcomm.com/doc/80-88500-4/topic/73_Hardware_reset.html)
The hardware reset can be caused by a secure watchdog, temperature sensor (TSENSE),
power management integrated circuit (PMIC) or sudden momentary power loss (SMPL).
Figuring out the cause is crucial for reset debugging. A further debugging approach might be
different based on this information.
Any of the error handlers in software may not run for the reset issues. Therefore, the data may
not be saved before a reset happens. This results in lack of information for finding out the
root cause of the issues.
Watchdog reset debugging is improved by debug-through-watchdog. It reserves power rail to CPU
core and system cache when a secure watchdog reset happens, allowing system debug image (SDI)
and DCC to flush the cache and save debug information upon hardware reset before resetting the
system.
RST\_STAT.BIN and PMIC\_PON.BIN are generated when a reset occurs, and these hold the AOSS\_CC\_RESET\_STATUS value and PMIC power on status register dump.
The following figure is an example of the hardware reset registers:
Figure : Sample summary of reset registers
The following is the general warm reset sequence with PMIC:
1. MSM pulls PS\_HOLD low.
2. PMIC pulls PON\_RESET\_N low to keep MSM in reset.
3. PMIC executes the warm reset.
4. PMIC pulls PON\_RESET\_N high to take MSM out of reset.
## SDM reset status
After a reset comes into the processor by watchdog and other reasons. The hardware register
AOSS\_CC\_RESET\_STATUS (which is used to be called GCC\_RESET\_STATUS) holds the reset
status.
Table : Hardware AOSS_CC_RESET_STATUS. The table shows a description of the hardware register AOSS_CC_RESET_STATUS. In
general, writing to the status bits clears the status.
| Bits | Name | Type | Description |
| --- | --- | --- | --- |
| 9 | PS\_HOLD\_STATUS | Read-write | - Set when PS_HOLD drops. If this bit is set together with another status bit, then the status should be interpreted as PS_HOLD caused by the condition indicated by the status bit.
- 1 – PS_HOLD dropped
|
| 8 | RESERVED | – | – |
| 7 | RESERVED | – | – |
| 6 | PMIC\_ABNORMAL\_RESIN\_RESET\_STATUS | Read-write | 1 – pmic resin\_n occurred because of the abnormal conditions of PMIC and not because of
PS\_HOLD |
| 5 | MSM\_TSENSE1\_RESET\_STATUS | Read-write | Set when temperature sensor activates
1 – tsens1 triggered reset |
| 4 | PROC\_HALT\_CTI\_STATUS | Read-write | |
| 3 | SRST\_RESET\_STATUS | Read-write | Set high when any SRST triggered
- 1 – srst triggered
- Reset state – 0x0
|
| 2 | MSM\_TSENSE0\_RESET\_STATUS | Read-write | Set when temperature sensor activates
1 – tsens0 triggered reset |
| 1 | PMIC\_RESIN\_RESET\_STATUS | Read-write | Set when PMIC reset in occurs
- 1 – pmic resin_n triggered
- Reset state – 0x0
|
| 0 | SECURE\_WDOG\_EXPIRE\_RESET\_STATUS | Read-write | Helps track watchdog reset loops
- 1 – Watchdog triggered
- Reset state – 0x0
|
Most of system crashes including software errors like panic, BUG, or
TrustZone (TZ) error eventually assert PS\_HOLD (which causes PMIC\_RESIN) and then fall into
secure watchdog reset by design. Therefore, bit0 and bit1 are displayed, which are set on
most of the crash dumps.
- **[PMIC PON reset status](https://docs.qualcomm.com/doc/80-88500-4/topic/74_PMIC_PON_reset_status.html)**
The reasons for PMIC PON reset can be found in the PMON\_HIS.BIN.
**Parent Topic:** [Debug](https://docs.qualcomm.com/doc/80-88500-4/topic/58_Debug.html)
Last Published: Aug 18, 2023
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