# PMIC PON reset status
Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/74_PMIC_PON_reset_status.html](https://docs.qualcomm.com/doc/80-88500-4/topic/74_PMIC_PON_reset_status.html)
The reasons for PMIC PON reset can be found in the PMON\_HIS.BIN.
PMIC\_PON.bin was used to check for the PMIC reset reason, but because the system debug image
(SDI) hardware and software execute the PS\_HOLD warm resets before the RAM dump occurs, it is
preferred to use PMON\_HIS.BIN over PMIC\_PON.BIN.
The following is a PMIC\_PON from PON\_HSI.bin dump:

There are three logs in the dump. It starts from offset +0x0C from the top. Each entry is 8 bytes and can be decoded like the following.
The third log has the oldest real-time clock (RTC) time stamp and first log is the latest, which
means the third log was recorded first. The logging starts from the bottom and grows to the
top side. So the third (oldest) log provides the details regarding the reset.
| Register Name | First
reset | Second reset | Third reset | Description |
| --- | --- | --- | --- | --- |
| PON\_PON\_REASON1 | 80 | 80 | 80 | 0x80: Triggered from KPDPWR press |
| PON\_WARM\_RESET\_REASON1 | 02 | 02 | 02 | 0x0 : PS\_HOLD |
| PON\_ON\_REASON | 80 | 40 | 40 | 0x40: warm reset
0x80: normal powering-on |
| PON\_POFF\_REASON1 | 00 | 00 | 00 | N/A |
| PON\_OFF\_REASON | 04 | 04 | 04 | 0x04: RAW\_DVDD\_RB\_OCCURED |
| PON\_FAULT\_REASON1 | 00 | 00 | 00 | N/A |
| PON\_FAULT\_REASON2 | 00 | 00 | 00 | N/A |
| Coded RTC time | 7D | 7D | 82 | RTC time |
In this example, PON\_ON\_REASON of the first reset was 0x80, which is normal powering-on. This is the usual reset caused by PS\_HOLD. This reset is followed by twice the amount of 0x40:warm resets because a couple of warm resets happen before entering the dump mode.
Table : PON reason
| Bit | Name | Description |
| --- | --- | --- |
| 7 | PON\_SEQ |