# System hang during power collapse

Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/75_System_hang_during_power_collapse.html](https://docs.qualcomm.com/doc/80-88500-4/topic/75_System_hang_during_power_collapse.html)

The power consumption is minimized by placing the cores in the Power Collapse mode. The
    Power Collapse mode is supported in most of the cores to maximize the device standby time.

Entering Power Collapse requires clock and voltage manipulation. Some abnormal behaviors may be
      observed during such operations. Being stuck while waking up from power collapse is an issue
      since an error handler is not expected to cover the situation. Multiple hardware components
      are involved during the operations.

For example, while applications processor subsystem (APSS) wakes up from a power collapse, modem
      power manager (MPM), resource power manager hardening (RPMh), subsystem power manager (SPM),
      and TrustZone (TZ) are all involved since RPMh wakes up APSS, and the TZ image runs on APSS
      upon wake-up. Many clock and power rails are accessed during the operation, which may cause
      abnormal behavior of CPU cores.

Identifying which stage of power collapse the device was running on is crucial. The RPMh log and
      TZ counter are used to identify the image level first. After the module is identified, the
      Qualcomm Debug Subsystem (QDSS) hardware events and software events can be used. Major events
      on the device can be tracked and monitored by those.

For additional information on power collapse/wake-up debugging, see
        <cite class="cite">Resource Power Manager (RPM.BF) Debug Manual</cite> (80-P9301-16).

**Parent Topic:** [Debug](https://docs.qualcomm.com/doc/80-88500-4/topic/58_Debug.html)

Last Published: Aug 18, 2023

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