# UFS hardware
Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/90_UFS_hardware.html](https://docs.qualcomm.com/doc/80-88500-4/topic/90_UFS_hardware.html)
Qualcomm Robotics RB5 provides slots for embedded UFS (eUFS) card within the device and
a removable UFS memory card.
The table lists the voltage and maximum frequency details of both eUFS and removable UFS
card:
Table : UFS controller and capabilities
| Slots | Lane | I/O voltage (V) | Card voltage (V) | Maximum frequency | Timing modes |
| --- | --- | --- | --- | --- | --- |
| eUFS on board | 2 | 1.2/1.8 | 2.95/2.5 | Gear 4 |
- Pulse width modulation (PWM) Gear 1, 2, 3, and 4
- High speed (HS) Gear 1, 2, 3, and 4
|
| UFS Card | 1 | 1.8 | 2.95 | Gear 3 |
- PWM Gear 1, 2, 3, and 4
- HS Gear 1, 2, and 3
|
The table lists the hardware specifications that are supported JEDEC and MIPI storage
interfaces.
| Hardware features | Support | Comments |
| --- | --- | --- |
| UFS 4.0.0 core\* | 2 cores | Embedded UFS controller, Gear 4 (2 lane)
UFS card controller, Gear 3 (1 lane) |
| Clock speeds supported | 9.98 Gbps (Rate A) | HS Gear 4 (2 lane) |
| Clock speeds supported | 5.83 Gbps (Rate B)
4.99 Gbps (Rate A) | HS Gear 3 (1 lane) |
| JEDEC UFS specification | v2.1 | JEDEC Specification for UFS – JESD220B UFS |
| JEDEC UFS specification | v3.0 | JEDEC Specification for UFS – JESD220D UFS |
| JEDEC UFS HCI | v2.1 | JEDEC Specification for UFS Host Controller Interface (HCI) – JESD223B UFS HCI –
Ver 2.0 |
| JEDEC UFS HCI | v3.0 | JEDEC Specification for UFS HCI – JESD223D UFS HCI – Ver 3.0 |
| Mobile industry processor interface (MIPI) UniPro | v1.61 | MIPI Alliance Specification for Unified Protocol (UniPro) – Ver 1.6 |
| MIPI M\_PHY | v3.1 | MIPI Alliance Specification for M-PHY Specification – Ver 3.00 |
| UFS hot-plug detect | No | Embedded UFS |
| UFS hot-plug detect | Yes | UFS card |
| Low-Power Mode (LPM) | Yes |
- Supports Link Hibernate and Sleep modes
- In LPM, both VCC and VCCQ go to 0 V
|
| \*UFS core internal v4.0.0 is supported. | \*UFS core internal v4.0.0 is supported. | \*UFS core internal v4.0.0 is supported. |
| | | |
Figure : Embedded UFS memory address
Figure : UFS card memory address
Figure : UFS block diagram
| Voltage signal | Voltage rail | Voltage level (V) | Comments |
| --- | --- | --- | --- |
| VREG\_L10A\_2P95 | LDO17A | 2.95 | VCC – Provides power to the UFS flash |
| VREG\_L6A\_1P2 | LDO6A | 1.2 | VCCQ – Provides power to the I/O and memory controller |
| VREG\_S4A\_1P8\* | S4A | 1.8 | VCCQ2 – Provides power to the I/O and memory controller; most vendors need both
VCCQ and VCCQ2 to power their devices |
| VREG\_L9A\_1P2 | LDO9C | 1.2 | Analog power – Shared by multiple peripherals; low noise analog power for PLL and
bandgap reference blocks |
| VREG\_L5A\_0P875 | LDO5A | 1.0 | Analog power – Shared between PCIe and SATA/UFS; main PHY analog power, low noise
domain |
| VREG\_L9A\_1P2 | LDO6A | 1.2 | Provides voltage to reset and clock pads |
| \*VCCQ (S4A\_1P2) is not connected to the UFS device but may be connected if required
by a device. | \*VCCQ (S4A\_1P2) is not connected to the UFS device but may be connected if required
by a device. | \*VCCQ (S4A\_1P2) is not connected to the UFS device but may be connected if required
by a device. | \*VCCQ (S4A\_1P2) is not connected to the UFS device but may be connected if required
by a device. |
Note: UFS host core is on CX digital domain. UFS PHY uses both CX and MX for digital
domain.
| Clock name | Normal frequency | SVS frequency | Description |
| --- | --- | --- | --- |
| cc\_ufs\_sys\_clk | 200 MHz | 100 MHz |
- UFS system clock
- AXI master clock
|
| cc\_ufs\_hclk | 75 MHz | 37.5 MHz | AHB slave clock |
| cc\_ufs\_unipro\_core\_clk | 150 MHz | 75 MHz | Unified Protocol (UniPro) core clock |
| cc\_ufs\_tx\_symbol\_clk |
- 75 to 225 kHz (PWM-G1)
- 150 to 450 kHz (PWM-G2)
- 300 to 900 kHz (PWM-G3)
- 600 to 900 kHz (PWM-G4)
- 31.2 MHz (HS-G1, RATE A)
- 36.48 MHz (HS-G1, RATE B)
- 62.4 MHz (HS-G2, RATE A)
- 72.96 MHz (HS-G2, RATE B)
- 124.8 MHz (HS-G3, RATE A)
- 145.92 MHz (HS-G3, RATE B)
|
- 75 to 225 kHz (PWM-G1)
- 150 to 450 kHz (PWM-G2)
- 300 to 900 kHz (PWM-G3)
- 31.2 MHz (HS-G1, RATE A)
- 36.48 MHz (HS-G1, RATE B)
- 62.4 MHz (HS-G2, RATE A)
- 72.96 MHz (HS-G2, RATE B)
| Tx symbol clock source from M-PHY lane 0 to controller |
| cc\_ufs\_rx\_symbol\_clk\_0 |
- 75 to 225 kHz (PWM-G1)
- 150 to 450 kHz (PWM-G2)
- 300 to 900 kHz (PWM-G3)
- 600 to 900 kHz (PWM-G4)
- 31.2 MHz (HS-G1, RATE A)
- 36.48 MHz (HS-G1, RATE B)
- 62.4 MHz (HS-G2, RATE A)
- 72.96 MHz (HS-G2, RATE B)
- 124.8 MHz (HS-G3, RATE A)
- 145.92 MHz (HS-G3, RATE B)
|
- 75 to 225 kHz (PWM-G1)
- 150 to 450 kHz (PWM-G2)
- 300 to 900 kHz (PWM-G3)
- 31.2 MHz (HS-G1, RATE A)
- 36.48 MHz (HS-G1, RATE B)
- 62.4 MHz (HS-G2, RATE A)
- 72.96 MHz (HS-G2, RATE B)
| Rx symbol clock source from M-PHY lane 0 to controller |
| cc\_ufs\_rx\_symbol\_clk\_1 |
- 75 to 225 kHz (PWM-G1)
- 150 to 450 kHz (PWM-G2)
- 300 to 900 kHz (PWM-G3)
- 600 to 900 kHz (PWM-G4)
- 31.2 MHz (HS-G1, RATE A)
- 36.48 MHz (HS-G1, RATE B)
- 62.4 MHz (HS-G2, RATE A)
- 72.96 MHz (HS-G2, RATE B)
- 124.8 MHz (HS-G3, RATE A)
- 145.92 MHz (HS-G3, RATE B)
|
- 75 to 225 kHz (PWM-G1)
- 150 to 450 kHz (PWM-G2)
- 300 to 900 kHz (PWM-G3)
- 31.2 MHz (HS-G1, RATE A)
- 36.48 MHz (HS-G1, RATE B)
- 62.4 MHz (HS-G2, RATE A)
- 72.96 MHz (HS-G2, RATE B)
| Not used |
| | | | |
| | | | |
Table : UFS reset signals
| Reset name | Corresponding clock name | Async reset |
| --- | --- | --- |
| cc\_ufs\_sys\_clk\_ares | cc\_ufs\_sys\_clk cc\_ufs\_tx\_cfg\_clk cc\_ufs\_rx\_cfg\_clk | FFs in cc\_ufs\_sys\_clk, cc\_ufs\_tx\_cfg\_clk, and cc\_ufs\_rx\_cfg\_clk\_clk clock
domains |
| cc\_ufs\_hclk\_ares | cc\_ufs\_hclk | FFs in cc\_ufs\_hclk domain |
| cc\_ufs\_phy\_ares | cc\_ufs\_phy | PHY |
| cc\_ufs\_unipro\_core\_clk\_ares | cc\_ufs\_unipro\_core\_clk | Qunipro FFs in cc\_ufs\_unipro\_core\_clk domain |
| cc\_ufs\_tx\_symbol\_clk\_ares | cc\_ufs\_tx\_symbol\_clk | FFs in cc\_ufs\_tx\_symbol\_clk domain |
| cc\_ufs\_rx\_symbol\_clk\_0\_ares | cc\_ufs\_rx\_symbol\_clk\_0 | FFs in cc\_ufs\_rx\_symbol\_clk\_0 domain |
Table : UFS interrupts – Embedded UFS
| Interrupt name | Description |
| --- | --- |
| ufs\_irq | UFS HCI |
**Parent Topic:** [Universal flash storage](https://docs.qualcomm.com/doc/80-88500-4/topic/89_UFS.html)
Last Published: Aug 18, 2023
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