# UFS device driver and kernel configuration
Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/92_UFS_software.html](https://docs.qualcomm.com/doc/80-88500-4/topic/92_UFS_software.html)
The UFS device driver support is provided for both boot and storage. UFS uses both MIPI
M-PHY and UniPro standards to configure the device driver for providing high-speed connectivity
and power efficiency.
MIPI M-PHY defines three gears for low and high speed modes. The table lists the supported
speed modes for embedded and removable UFS.
Table : Supported speed modes for UFS
| Feature | Support | Comments |
| --- | --- | --- |
| Gear 4 Lane 2 | Yes | Gear 4 Lane 2 for UFS embedded |
| Gear 3 Lane 1 | Yes | Gear 3 Lane 1 for external UFS card |
| JEDEC UFS 3.0 | Yes | UFS embedded device |
| JEDEC UFS 2.1 | Yes | UFS card |
The following figure provides the driver path for the embedded UFS on device, which uses
M-PHY and UniPro specifications to configure the device driver for high speed mode.
Figure : UFS device driver path
The following figure shows the UFS PHY driver configured for high speed mode.
Figure : UFS PHY driver path
Table : UFS kernel configuration
| Configuration | Enabled
(Yes/No) | Description |
| --- | --- | --- |
| CONFIG\_DEBUG\_FS | Yes | Enables debugging through the debugfs node |
| CONFIG\_UFS\_FAULT\_INJECTION | No | Injects the failure command for debugging |
| CONFIG\_SMP | Yes | Enables the driver to work in a multiprocessor environment |
| CONFIG\_PM\_RUNTIME | Yes | Enables the driver to perform runtime power management, that is, runtime suspend and runtime resume |
| CONFIG\_SCSI\_UFSHCD | Yes | Enables the UFS host control driver in the kernel |
| CONFIG\_SCSI\_UFSHCD\_PLATFORM | Yes | States that the UFS controller is supported by the platform bus |
| CONFIG\_SCSI\_UFS\_QCOM | Yes | Enables a Qualcomm-specific addition to access the hardware, that is, PHY configuration and
vendor-specific registers |
| CONFIG\_SCSI\_UFS\_TEST | Yes | Enables unit test |
| CONFIG\_PHY\_QCOM\_UFS | Yes | Supports UFS PHY |
Table : Expected key performance indicators
| Test name | Lane 2 |
| --- | --- |
| Sequential write G3 (MB/s) | 178 |
| Sequential read G3 (MB/s) | 758 |
## UFS testing and debugging
The Qualcomm Memory Validation Suite (QMVS) tool executes the flash validation compliance
test for a UFS device. For installation and execution procedures, see the readme text file
within the QMVS directory.
For information on debugging, see UFS Overview (80-NN752-1).
**Parent Topic:** [Universal flash storage](https://docs.qualcomm.com/doc/80-88500-4/topic/89_UFS.html)
Last Published: Aug 18, 2023
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