# SD/SDIO hardware
Source: [https://docs.qualcomm.com/doc/80-88500-4/topic/97_SD_SDIO_hardware.html](https://docs.qualcomm.com/doc/80-88500-4/topic/97_SD_SDIO_hardware.html)
The SD/SDIO storage controller provides an interface for SD cards and handles the flow
the data between SD/SDIO and the CPU.
The table lists the storage controller capabilities:
Table : SD storage controller and capabilities
| Slots | Bits | I/O voltage (V) | Card voltage (V) | Max frequency | Timing modes | Functions |
| --- | --- | --- | --- | --- | --- | --- |
| SDC2 | 4 | 1.8/2.95 | 3.0 |
- SDR – 200 MHz
- DDR – 50 MHz
| DS, HS, SDR12, SDR25, SDR50, SDR104, and DDR50 | SDIO 3.0/SD 3.0 |
| SDC4 | 4 | 1.8 | 1.8 |
- SDR – 100 MHz
- DDR – 50 MHz
| DS, HS, SDR12, SDR25, SDR50, and DDR50 | SDIO 3.0/SD 3.0 |
| Hardware features | Support | Description |
| --- | --- | --- |
| SDCC5\* core | 2 cores |
- SDC2 – 4 bit
- SDC4 – 4 bit
|
| Clock speeds supported | |
- SDC2 at SDR104
- SDC4 at SDR50
|
| SD hot-plug detect | Yes | GPIO\_95 is used in the Qualcomm reference design |
| Low-power mode (LPM) | Yes | Only VDD (VCC) goes to 0 V on runtime suspend and system suspend |
| \*SDCC5 is the fifth generation of the SDCC core. | \*SDCC5 is the fifth generation of the SDCC core. | \*SDCC5 is the fifth generation of the SDCC core. |
Note: The internal DLL and pad configuration is different for each SDC slot, so each SDC slot supports different timing modes.
## SDCC memory address
Figure : SDC 2 memory address
Figure : SDC 4 memory address
## Power rails
Table : SD card power rails
| Voltage rail | Voltage level (V) | Comments |
| --- | --- | --- |
| VREG S4 | 1.8 | SD card detect (GPIO) |
| VREG L9C | 2.95 | SD card |
| VREG L6C | 1.8/2.95 | SD card I/O |
| VREG S4 | 1.8 | SDIO card I/O |
## SDCC clocks
Table : SDC2 clocks
| Clock | Operating frequency | Comments |
| --- | --- | --- |
| cc\_sdcc2\_h\_clk (HCLK) | 4 kHz to 128 MHz | HCLK |
| cc\_sdcc2\_m\_clk (MCLK) | 100 kHz to 208 MHz | MCLK |
| sdcc2\_clk\_fb | 100 MHz | Feedback clock from the PAD; used up to 100 MHz |
Table : SDC4 clocks
| Clock | Operating frequency | Comments |
| --- | --- | --- |
| cc\_sdcc4\_h\_clk (HCLK) | 4 kHz to 128 MHz | HCLK |
| cc\_sdcc4\_m\_clk (MCLK) | 100 kHz to 208 MHz | MCLK |
| sdcc4\_clk\_fb | 100 MHz | Feedback clock from the PAD; used up to 100 MHz |
**Parent Topic:** [SD/SDIO](https://docs.qualcomm.com/doc/80-88500-4/topic/96_SD_SDIO.html)
Last Published: Aug 18, 2023
[Previous Topic
SD/SDIO](https://docs.qualcomm.com/bundle/publicresource/80-88500-4/topics/96_SD_SDIO.md) [Next Topic
SD/SDIO software](https://docs.qualcomm.com/bundle/publicresource/80-88500-4/topics/98_SD_SDIO_software_examples.md)