# Frequently Asked Questions

## General

- [What are the PCB file formats supported?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#what-are-the-pcb-file-formats-supported)
- [What’s the recommendation on the board configuration description?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#what-s-the-recommendation-on-the-board-configuration-description)
- [Is it recommended to do simulations with all the devices at once?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#is-it-recommended-to-do-simulations-with-all-the-devices-at-once)
- [How much time does it take for the simulation?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#how-much-time-does-it-take-for-the-simulation)
- [What’s the allowed format for the custom capacitor models?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#what-s-the-allowed-format-for-the-custom-capacitor-models)
- [What if there is no matching VRM port found in the port selection?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#what-if-there-is-no-matching-vrm-port-found-in-the-port-selection)
- [How to select a capacitor for VRM?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#how-to-select-a-capacitor-for-vrm)
- [What to do if certain functions aren’t being used from the device?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#what-to-do-if-certain-functions-aren-t-being-used-from-the-device)
- [What’s a rail and what’s a port?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#what-s-a-rail-and-what-s-a-port)
- [How to understand the plot?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#how-to-understand-the-plot)
- [I get a message about a mismatch in stack-up between the board file and board configuration.](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#i-get-a-message-about-a-mismatch-in-stack-up-between-the-board-file-and-board-configuration)
- [Do models need to be assigned for the PMIC and SOC?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#do-models-need-to-be-assigned-for-the-pmic-and-soc)
- [What’s the temperature setting at which the simulation is run?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#what-s-the-temperature-setting-at-which-the-simulation-is-run)
- [I get a huge list of components for which the model needs to be assigned; some of them are irrelevant.](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#i-get-a-huge-list-of-components-for-which-the-model-needs-to-be-assigned-some-of-them-are-irrelevant)
- [Where can I get details on Vdrop calculations?](https://docs.qualcomm.com/doc/80-99775-1/topic/pdn-checker_faq.html#where-can-i-get-details-on-vdrop-calculations)

## What are the PCB file formats supported?

Cadence .BRD, Cadence .SPD and tool independent format - ODB++.

## What’s the recommendation on the board configuration description?

You can use any name of your choice, but avoid use of special characters.

## Is it recommended to do simulations with all the devices at once?

Yes, particularly when there are shared rails between multiple devices and have cross-impedance, effective impedance and voltage drop specifications for the ports from multiple devices. If there is none, simulation can be run for individual rails or few selected ones, based on the areas of interest.

## How much time does it take for the simulation?

It depends on the PCB size, complexity, and the number of rails under simulation. For a rail, it can range from 15 minutes to 2 hours. You will be able to see the report (PDF) only when all the rail simulations are completed.

## What’s the allowed format for the custom capacitor models?

S-parameter files

## What if there is no matching VRM port found in the port selection?

If there is only an AC specification specified for that rail, a VRM isn’t provided, and you will see this message. It’s okay to ignore this message and move forward. However, if a DCR specification also exists, it’s recommended to go back and check the selected VRM devices. If the VRM is a third-party device, try using the cap VRM as a substitute.

## How to select a capacitor for VRM?

Capacitors placed closest to the VRM output pin should be selected. This will ensure the measured DCR is closer to the actual value.

## What to do if certain functions aren’t being used from the device?

You can clear those ports or rails altogether if they’re not being used. For example, if a rail supplies voltage to all the camera PHYs and only partial PHYs are being used, you can clear the PHY ports that aren’t being used. If the camera PHYs aren’t being used at all, you can clear the complete rail altogether.

## What’s a rail and what’s a port?

Rails are the power nets driving the load. A port is an input/output with the definition of device pins; the exact pins (positive and negative) are mentioned in the processor device’s -1P document (PDN Specifications).

## How to understand the plot?

Plots provide PDN impedance response over frequency with the red-colored mask; measured PDN impedance must be smaller than the mask across the entire range of frequencies of the mask.

## I get a message about a mismatch in stack-up between the board file and board configuration.

If the stack-up layer name or number of layers has changed compared to the previous run where the board configuration info was used, this message is shown. In this case, allow the overwrite of the board configuration.

## Do models need to be assigned for the PMIC and SOC?

No, models shouldn’t be assigned for the PMIC and the SOC.

## What’s the temperature setting at which the simulation is run?

By default, it’s 25°C. However, you can alter the temperature in the stack-up step. Note that only copper conductivity is altered based on the temperature selection.

## I get a huge list of components for which the model needs to be assigned; some of them are irrelevant.

This can happen if there is an electrical path (through resistors) between the SOC rails and VPH\_PWR. To avoid a big list of components, delete the components forming the bridge to VPH\_PWR (just temporarily for simulation) and submit for simulation.

## Where can I get details on Vdrop calculations?

See 80-VT310-90 PDN Vdrop Methodology.

Last Published: Oct 19, 2026

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