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# Snapdragon X2 AI/ML software introduction Snapdragon X2 pairs new hardware AI accelerators with the Qualcomm AI Runtime software stack so you can run machine learning (ML) and generative AI models on device. The platform targets two workload classes: general AI use cases on the Qualcomm^®^ Hexagon^™^ Tensor Processor, and audio and always-on use cases on the LPASS AI accelerator. The sections that follow describe the accelerator hardware, the runtime and toolchain that drive it, and other resources you can use to go deeper. ## Hardware AI accelerators Snapdragon X2 has two new AI accelerators: the Qualcomm Hexagon Tensor Processor for general AI use cases and the LPASS AI accelerator, a second-generation embedded NPU (eNPU), for audio-specific use cases. The Hexagon Tensor Processor combines scalar, vector, and matrix processing on a single Hexagon V81 core, while the eNPU handles low-power, always-on audio workloads in the low-power audio subsystem (LPASS). The following figure shows the internal blocks of the Snapdragon X2 Hexagon Tensor Processor, grouped into scalar, memory, vector, and matrix processing. **Figure: Hexagon Tensor Processor block architecture: scalar, memory, vector (HVX), and matrix (HMX) processing.** The Hexagon Tensor Processor scalar block is a Hexagon V81 core with a 4-way very long instruction word (VLIW) pipeline, a 32-bit scalar register file (RF), separate instruction (`I$`) and data (`D$`) caches, and 12 hardware threads. The memory block provides the AXI bus unit, `L2$` and its control logic, direct memory access (DMA) with compression, and L2 prefetch. Vector processing uses the Hexagon Vector eXtensions (HVX), with four execution slots, a 1024-bit vector RF, scatter/gather, and vector tightly coupled memory (TCM) across eight HVX layers. Matrix processing (HMX) adds two accumulator RFs and separate 2D FP16 and 2D integer multiply-accumulate (MAC) arrays. Alongside the Hexagon Tensor Processor, the LPASS AI accelerator sits in the low-power island (LPI) of the audio subsystem. The audio digital signal processor (DSP) runs the echo cancellation (EC), noise suppression (NS), and Stage 1 voice activation (VA) path, hands off to Stage 2 VA on the apps processor, and shares local `L2/TCM` memory and DDR. The AI accelerator and the voice UI hardware accelerator provide the always-on audio processing. ## Hexagon DSP evolution The Hexagon Tensor Processor on Snapdragon X2 uses the V81 core, which roughly doubles the thread count, clock-normalized MAC throughput, and bus bandwidth of the prior V73 generation. Use the comparison to size expected performance gains when you port workloads from V73 architecture to V81 architecture. The following table compares the V73 and V81 core architectures, each shown with and without HVX plus matrix processing. Hexagon Tensor Processor core comparison | Attribute | Hexagon V73 (SC8380XP) | HVX V73 + Matrix processing (SC8380XP) | Hexagon V81 (Snapdragon X2) | HVX V81 + Matrix processing (Snapdragon X2) | | --- | --- | --- | --- | --- | | Threads/Core | 6 scalar threads |

4 128-byte vector threads + 1 matrix thread

| 12 scalar threads |

8 128-byte vector threads + 1 matrix thread

| | Processor Clock | 1171.2 MHz nominal (1401.6 MHz Turbo) |

1171.2 MHz nominal (+ 1401.6 MHz Turbo)

| 1248 MHz nominal (1593.6 MHz Turbo) |

1248 MHz nominal (+ 1593.6 MHz Turbo)

| | Arithmetic | Fixed and floating point | Fixed point and floating point | Fixed and floating point | Fixed point and floating point | | Caches | L1 Instruction: 32 KB, L1 Data: 16 KB, L2: 1024 KB | Same L2 | L1 Instruction: 32 KB, L1 Data: 16 KB, L2: 1024 KB | Same L2 | | Performance | 16 MMAC/MHz (16-bit fixed point), 32 MMAC/MHz (8-bit fixed point), 8
MFLOP (SP)/MHz | 4x HVX, + 128 MMAC/MHz (16-bit fixed point), + 512 MMAC/MHz (8-bit fixed
point), + 512 Mops/MHz (16-bit fixed point) | 32 MMAC/MHz (16-bit fixed point), 64 MMAC/MHz (8-bit fixed point), 16
MFLOP (SP)/MHz | 8x HVX, + 256 MMAC/MHz (16-bit fixed point), + 1024 MMAC/MHz (8-bit
fixed point), + 1024 Mops/MHz (16-bit fixed point) | | Architecture | Simultaneous Multi-Threading (SMT) | — | Simultaneous Multi-Threading (SMT) | — | | Bus interface | 59 GB per second, direct interface to DDR | — | 170 GB per second, direct interface to DDR | — | | Instruction/System Enhancements | Multimedia enhanced, Dual-Clusters, Co-processor capability, Automatic
Power Collapse (APC) | HVX, Matrix processing, Scatter-Gather, Large VTCM, User DMA, Deep
Learning Bandwidth Compression | Multimedia enhanced, Quad-Clusters, Co-processor capability, Automatic
Power Collapse (APC) | HVX, Matrix processing, Scatter-Gather, Large VTCM, User DMA, Deep
Learning Bandwidth Compression | ## Hexagon Tensor Processor software improvements The Hexagon Tensor Processor software stack adds performance, concurrency, precision, and tooling improvements on Snapdragon X2. Use these improvements to plan which models and precisions to target and which host tools to adopt. Note Availability is subject to change and is updated through the respective AI/ML SDK releases. The following table lists the Hexagon Tensor Processor software improvement areas and what each one covers. Software improvement areas | Area of improvement | Description | | --- | --- | | Hexagon Tensor Processor performance and utilization | Scheduler, tiling, allocator, and sequencer improvement | | Concurrency | Improved concurrencies between ML workload and ML workload, and between
ML workload and non-ML workload (for example, computer vision (CV)) | | INT4 precision support | Hexagon Tensor Processor INT4 (8-bit activation with 4-bit weights) support | | Mixed precision | FP16 in mixed precision support; mixed precision supports INT8, INT16,
and FP16 activations | | NLP support | Natural language processing (NLP) models, BERTs, and transformers | | Tools | New tools for model viewing, model inspection, model execution
simulation, and model accuracy checking on host | ## Low-power AI with the eNPU The second-generation embedded NPU (eNPU) on Snapdragon X2 adds hardware acceleration for low-power AI and always-on use cases. Compared with the first-generation eNPU, it supports a wider set of operations so you can run more of an audio or always-on pipeline on the accelerator. The following table compares the operations supported by the first-generation eNPU and the second-generation eNPU on Snapdragon X2. Supported operations comparison | First generation eNPU | Second generation eNPU on Snapdragon X2 | | --- | --- | |

Matrix-matrix multiplication

Matrix-vector multiplication

Matrix-matrix multiplication

Matrix-vector multiplication

Elementwise multiplication

Output quantization

Non-linear activations

CNN support

Multi-layer linked list

Weights decompression

| ## Hexagon Tensor Processor and LPASS AI accelerator benefits The Hexagon Tensor Processor and the LPASS AI accelerator serve complementary roles: the Hexagon Tensor Processor delivers high-performance general AI offload, while the LPASS AI accelerator delivers low-power, always-on audio processing. Use the comparison to decide which accelerator fits a specified workload. The following table lists the benefits of the Hexagon Tensor Processor and the LPASS AI accelerator for AI offload. Hexagon Tensor Processor and LPASS AI accelerator benefits | Hexagon Tensor Processor | LPASS AI accelerator for AI offload support | | --- | --- | |

Reduces handoff effort, improving performance and power

Leverages existing expertise

Low-power, high-performance DSP design

Hardware-software synergy

Core-SoC synergy

Efficiencies allow for higher performance

Single compute engine allows for full performance on batch=1

Unified programming model

Low power island (LPI) support for always-on voice UI (noise suppression, keyword detection, and context detection)

Non-LPI support for voice call

Embedded AI (eAI) runtime library for deeply embedded use cases is self-contained (no need for application processor)

Qualcomm^® AI Engine direct available for OEMs

| For more information, see the Hexagon Tensor Processor overview for Snapdragon X2 for Windows Mobile PC (80-A0399-86) and the Snapdragon X2 Windows Mobile PC audio overview (80-A0399-50). ## AI inferencing compute platforms The Snapdragon X2 compute platform maps trained models from common ML frameworks through Qualcomm AI Runtime to the on-device backends. You bring your own model, convert it to ONNX (or a framework-specific format), and run inference on the CPU, GPU, Hexagon Tensor Processor, or LPASS AI accelerator, each with its own supported precisions. The following figure shows the AI inferencing compute platform flow, from training frameworks through the runtime to the on-device backends. **Figure: AI inferencing compute platform flow** Trained models come from ML frameworks such as Caffe2, PyTorch, MXNet, Cognitive Toolkit, PaddlePaddle, and TensorFlow, and are exported to ONNX (`.onnx`), PyTorch (`.pth/onnx`), or TensorFlow (`.pb/onnx`) formats. The runtime framework layer exposes Qualcomm AI Runtime APIs and ONNX Runtime and supports a bring-your-own-model flow. The Qualcomm AI Runtime low-level library provides `QML`, `KERNELS`, `eAI`, `NEON`, and `Hexagon Tensor Processor Core`. On-device execution runs on the AI Engine backends with these precisions: - CPU: INT8, FP32 - GPU: FP16, FP32 - Hexagon Tensor Processor: INT4, INT8, INT16, FP16, Mixed - Audio LPAI/eNPU: INT8, INT16 Model preparation uses the AIMET and AI compiler tools. ## GenieX on-device generative AI runtime GenieX is an on-device generative AI inference runtime for Qualcomm platforms. It runs frontier large language models (LLMs) and vision language models (VLMs) on the Hexagon Tensor Processor, Adreno GPU, or CPU through one programming interface. GenieX ships as a unified SDK with several developer-facing interfaces, so you can choose the interface that fits your workflow. The following figure shows the GenieX stack, from the developer interfaces down to the CPU, GPU, and NPU hardware. **Figure: GenieX layered stack: Interfaces, SDK, plugins, runtimes (GGML and Qualcomm AI Runtime SDK), and CPU/GPU/NPU hardware.** The GenieX stack layers the developer interfaces over the GenieX SDK, which routes work through the llama.cpp and Qualcomm AI Runtime plugins. The llama.cpp plugin uses the third-party GGML runtime with its GGML CPU, GPU, and NPU kernels and the Qualcomm AI Runtime plugin uses the Qualcomm AI Runtime SDK. Both paths target the CPU, GPU, and NPU hardware. The following table describes each GenieX interface and lists the setup and tutorial resources for it. GenieX interfaces | Interface | Description | Resources | | --- | --- | --- | | Command-line interface (CLI) | Run, benchmark, and serve AI models from the terminal for
experimentation, validation, and deployment workflows. |

GenieX CLI setup (prerequisites and setup)

GenieX CLI tutorial (tutorial)

| | Python | Add model inference to Python applications and services through a Python
API. |

GenieX Python setup (prerequisites and setup)

GenieX Python tutorial (tutorial)

| | Docker | Run GenieX in a container for reproducible, portable development and
deployment workflows. | [GenieX Docker setup (prerequisites, setup, and tutorial)](https://geniex.aihub.qualcomm.com/en/run/linux/install#prerequisites) | | OpenAI-Compatible Server | Serve models through an OpenAI API-compatible endpoint so existing
OpenAI-based applications and tooling run locally with minimal or no
code changes. | [Local Inference Server (OpenAI-compatible API)](https://geniex.aihub.qualcomm.com/en/run/cli/local-server) | Note GenieX is in the early stages of development. If you encounter issues, submit a support ticket through [Qualcomm support](https://mysupport.qualcomm.com/). Last Published: Aug 27, 2026 [Previous Topic AI/ML software overview documentation](https://docs.qualcomm.com/bundle/publicresource/80-A0399-65/topics/home.md) [Next Topic AI/ML software solutions](https://docs.qualcomm.com/bundle/publicresource/80-A0399-65/topics/software-solutions.md)