# Snapdragon X2 interface architecture
The peripheral, PCIe, and USB interfaces each build on a distinct
hardware block.
The QUP v3 wrapper for serial buses, dedicated PCIe
controllers and PHYs, and multiport USB controllers with SuperSpeed and
eUSB2 PHYs. Use the following architecture overview to understand how
each block connects to the rest of the SoC before you configure it.
The three interface families share the same SoC but follow different
data paths. The QUP v3 subsystem multiplexes low-speed serial protocols
through shared serial engines, the PCIe subsystem routes controller
traffic through PHY layers to internal pins and external devices, and
the USB subsystem connects controllers through SuperSpeed and eUSB2 PHYs
to Type-C and Type-A connectors.
## QUP v3 architecture
The QUP v3 module is a programmable block that supports UART, SPI, I^2^C,
and I^3^C on the same hardware. A single QUP v3 module provides up to
eight serial interfaces through its internal serial engines (SE), and
the protocol of each interface is set by the firmware loaded to the SE.
To load a protocol, modify the `oem_qupac_config.h` file in TrustZone.
QUP v3 supports access from multiple hardware entities, where each
entity has its own execution environment (EE), address space, and
interrupt line.
The following figure shows how the QUP v3 module connects the SoC
processors and system memory to external UART, SPI, I^2^C, and I^3^C
devices.
**Figure : QUP v3 module connections**
The QUP v3 wrapper receives its clocks, interrupts, and pin control from
separate SoC blocks.
The following figure shows the connections between the QUP v3 wrapper,
the clock controller, the interrupt controller, and the Top-Level Mode
Multiplexer (TLMM).
**Figure : QUPv3 wrapper clock interrupt TLMM**
## QUP v3 operation modes
QUP v3 supports three transfer modes, and the driver selects the mode at
runtime based on the use case. There is no separate data path for UART,
SPI, or I^2^C; they share a common QUP v3 wrapper. The mode depends on the
use case, such as multi-EE, single-EE, transfer size, and protocol. For
any multi-EE use case, such as the application processor and TrustZone
both using SPI, the transfer must go through the generic software
interface (GSI) mode.
- **FIFO mode** — The application processor programs the generic
interface (GENI), and then receives or transmits data to or from GENI
and memory.
- **DMA mode** — The application processor initializes DMA, and then
the SE configures GENI and starts the transfer.
- **GSI mode** — The application processor prepares a transfer ring
element (TRE) and informs the QUP GSI. The GSI processes the TRE, the
TRE completes and is sent to GENI, and the SE processes the Rx and Tx
data. GSI acts as the SE manager interface that queues transfers using
TREs.
The following table lists the transfer modes that each subsystem
supports for each protocol.
| Protocol | HLOS | UEFI | aDSP | TrustZone |
| --- | --- | --- | --- | --- |
| UART | FIFO (enable DMA flag available) | FIFO | FIFO | FIFO |
| I^2^C | GSI/FIFO | GSI/FIFO | GSI/FIFO | GSI |
| I^3^C | NA | NA | GSI | GSI |
| SPI | GSI | GSI | GSI | GSI |
| QSPI | GSI | GSI | GSI | GSI |
The following figure shows the SPI controller-to-target signal
connections used by the SPI protocol.
**Figure : SPI controller target signals**
The following figure shows the QSPI controller-to-target signal
connections used by the quad SPI protocol.
**Figure : QSPI controller target signals**
## PCIe architecture
The PCIe subsystem routes each root complex through a PHY layer to
internal pins and external devices such as WLAN, NVMe, WWAN, and a GPU.
Each port maps to a specific use case and generation and lane
configuration.
The following figure shows the PCIe data flow from the controllers
through the PHY layers to internal pins and external components.
**Figure : PCIe data flow**
The following table lists the PCIe port characteristics, including the
use case, generation and lane configuration, and PHY configuration for
each port.
| Package interface numbering | `PCIE_3A` | `PCIE_3B` | `PCIE_4` | `PCIE_5` | `PCIE_6` |
| --- | --- | --- | --- | --- | --- |
| SoC IP numbering | `PCIE_3` | `PCIE_3B` | `PCIE_4` | `PCIE_5` | `PCIE_6` |
| Use case mapping | GPU (8L) / SDXC (4L) | NVMe | WLAN | NVMe | WWAN / SD Express |
| Gen/lane config | Gen5/8L | Gen5/4L | Gen4/2L | Gen5/4L | Gen4/2L |
| PHY config | 4L Gen5 | 4L Gen5 | PCIe | 4L Gen5 | PCIe |
Each root complex draws from a phase-locked loop (PLL) rail at 1.2 V and
a core rail at 0.88 V. The following table lists the power rails and
voltages for each root complex.
| Root complex | Rail | Voltage |
| --- | --- | --- |
| `PCIE3A_GEN5X8` (Gen5 8-lane) | `VREG_L2C` → `VDD_A_PCIE_3_PLL_1P2` | 1.2 V |
| `PCIE3A_GEN5X8` (Gen5 8-lane) | `VREG_L3C` → `VDD_A_PCIE_3_0P9` | 0.88 V |
| `PCIE4_GEN4X2` (Gen4 2-lane) | `VREG_L4F` → `VDD_A_PCIE_4_PLL_1P2` | 1.2 V |
| `PCIE4_GEN4X2` (Gen4 2-lane) | `VREG_L1C` → `VDD_A_PCIE_4_0P9` | 0.88 V |
| `PCIE5_GEN5X4` (Gen5 4-lane) | `VREG_L4C` → `VDD_A_PCIE_5_PLL_1P2` | 1.2 V |
| `PCIE5_GEN5X4` (Gen5 4-lane) | `VREG_L2F` → `VDD_A_PCIE_5_0P9` | 0.88 V |
| `PCIE6_GEN4X2` (Gen4 2-lane) | `VREG_L4F` → `VDD_A_PCIE_6_PLL_1P2` | 1.2 V |
| `PCIE6_GEN4X2` (Gen4 2-lane) | `VREG_L1C` → `VDD_A_PCIE_6_0P9` | 0.88 V |
Each PCIe port uses three sideband signals for clock request, wake, and
reset. The following table lists the sideband signals, their pin
assignments, and their function.
| Signal | Pin number | Description |
| --- | --- | --- |
| CLKREQ |
PCIe4 – GPIO_147
PCIe5 – GPIO_153
PCIe6 – GPIO_150
| CLKREQ signal (active low, special function within the PCIe hardware block) used for PCIe ASPM. |
| WAKE\_n |
PCIe4 – GPIO_148
PCIe5 – GPIO_154
PCIe6 – GPIO_151
| Root complex input and endpoint (EP) output signal (active low, normal GPIO). |
| PERST\_n |
PCIe4 – GPIO_146
PCIe5 – GPIO_152
PCIe6 – GPIO_149
| Root complex output and EP input signal (active low, normal GPIO). |
The PCIe subsystem supports PCIe INTx interrupts (INTA#, INTB#, INTC#,
and INTD#), message signaled interrupt (MSI), and the `PCIe_WAKE_n`
signal.
## USB architecture
The USB subsystem connects its controllers through on-chip PHYs to
external Type-C and Type-A connectors, a fingerprint connector, and a
secure camera. The Type-C ports combine an eUSB2 PHY, a USB3 PHY, and
power delivery. Use the following figures to trace the USB components,
PHY interfaces, connectivity, and software stack from the SoC to the
external connectors.
The following figure shows the on-chip USB 3.1 components that connect
to an external USB Type-C connector.
**Figure : USB 3.1 Type-C components**
The following figure shows the on-chip DisplayPort, USB 3.x, and AHB2
PHY controllers connecting to a Type-C connector through the PHY
interfaces.
**Figure : USB DisplayPort Type-C PHY controllers**
The following figure shows the other USB interfaces, where five USB
controllers route through on-chip PHYs and interface pins to external
devices.
**Figure : USB controllers PHYs interface pins**
The following figure shows the Snapdragon X2 USB connectivity across
retimers and repeaters to the external connectors and devices.
**Figure : USB connectivity retimers repeaters**
The Linux USB software stack spans user space, the Linux kernel, and the
SoC hardware and firmware.
The following figure shows the Linux USB 3.1 software stack layers and
the flow of data and control signals between them.
**Figure : Linux USB 3.1 software stack**
The following figure shows the sequence of Linux and QTI kernel and
user-space components during USB Type-C connection events, including the
host, device, and optional DisplayPort alt-mode paths.
**Figure : USB Type-C connection sequence**
## Related
- [Configure the peripheral interfaces](https://docs.qualcomm.com/doc/80-A0399-8/topic/configure-peripheral-interfaces.html)
- [Configure the PCIe and USB interfaces](https://docs.qualcomm.com/doc/80-A0399-8/topic/configure-pcie-usb-interfaces.html)
- [Debug the USB interface](https://docs.qualcomm.com/doc/80-A0399-8/topic/debug-usb.html)
Last Published: Sep 17, 2026
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