# Configure the peripheral interfaces

Configure a QUP serial engine for I^2^C, SPI, UART, or QSPI by granting
TrustZone access and enabling the interface in each subsystem device
tree.

Use the following reference tables and procedures to enable the correct
instance without conflicting with another protocol. QUP serial engines
are shared across subsystems, so every interface change must be
consistent across TrustZone, the Linux kernel, UEFI, and XBL. Start from
the QUP serial engine reference to select the instance, base address,
interrupt, and clock, and then follow the procedure for the target
protocol and subsystem.

## Prerequisites

- Write access to the TrustZone, Linux kernel, UEFI, and XBL source
trees for the Snapdragon X2 platform.
- The QUP instance, base address, interrupt, and clock for the target
bus, from the QUP serial engine reference.
- Confirmation that the serial engine isn’t already configured for a
different protocol.

- [Map an ACPI device to a QUP instance](https://docs.qualcomm.com/doc/80-A0399-8/topic/map-acpi-device-to-qup-instance.html)
The GPIO mapping for a QUP instance depends on the configured mode.
Each Advanced Configuration and Power Interface (ACPI) device maps to
a QUP instance.
- [QUP serial engine reference](https://docs.qualcomm.com/doc/80-A0399-8/topic/qup-serial-engine-reference.html)
Each QUP instance has a fixed wrapper, base address, interrupt, clock,
and configuration macro.
- [Provide HLOS access to the SMMU](https://docs.qualcomm.com/doc/80-A0399-8/topic/provide-hlos-access-to-smmu.html)
Configure instances that require HLOS access in the System Memory
Management Unit (SMMU) device tree.
- [Enable the I2C interface](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-i2c-interface.html)
Enable an I^2^C instance for the application processor (HLOS and UEFI) by
granting TrustZone access and then enabling the instance in each
subsystem device tree.
- [Enable the SPI interface](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-spi-interface.html)
Enable an SPI instance for the application processor (HLOS and UEFI) by
granting TrustZone access and then enabling the instance in each
subsystem device tree.
- [Enable the UART interface](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-uart-interface.html)
Enable a UART instance for the application processor (HLOS and UEFI) by
granting TrustZone access and then enabling the instance in each
subsystem device tree.
- [Enable QSPI for the SPI-NOR interface](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-qspi-spi-nor-interface.html)
Enable QSPI for SPI-NOR in the pre-DDR XBL to use storage.
- [Enable a peripheral interface in the aDSP](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-peripheral-interface-adsp.html)
Enable a Sensing Hub (SSC) QUP instance in the aDSP using the
`fw_devcfg.dtsi` file.
- [Enable a peripheral interface in TrustZone](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-peripheral-interface-trustzone.html)
All TrustZone drivers and their configs are in `core/settings/buses/`.
- [Enable a peripheral interface in the SoCCP](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-peripheral-interface-soccp.html)
Charger and battery management tasks moved from the aDSP to the SoC
control processor (SoCCP).
- [Enable the debug UART in the SoCCP](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-debug-uart-soccp.html)
Enable and configure the debug UART instance in the SoCCP device tree.
- [Enable a peripheral interface in the OOB subsystem](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-peripheral-interface-oob.html)
The out-of-band (OOB) processor supports remote debug with SPI-NOR
memory access, which lets an IT team access the device and repair or
clean it if the device is stolen.

Last Published: Sep 17, 2026

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