# Enable a peripheral interface in the SoCCP

Charger and battery management tasks moved from the aDSP to the SoC
control processor (SoCCP).

Instances configured for the SoCCP must be defined in the XBL file:

/Settings/Soc/Glymur/Core/Buses/qup_fw_ac/qup_fw_ac.dtsi
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Provide GPII access to the SoCCP by adding `ac_config_1`.

1. Enable and configure the required serial engine instance in the SoCCP device tree.

    1. Open the SoCCP device tree file:

dt_settings/soc/glymur_soccp/core/buses/qupv3-se.dtsi
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    2. Enable the required instance.

        For example:

&qup1\_se5 {

compatible = “qcom,qup-i2c”;
status = “okay”;
};
    3. For the original definition of the instance, see:

dt_settings/soc/glymur_soccp/core/buses/qupv3.dtsi
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2. Provide access permissions to the SoCCP.

    1. Open the TrustZone access control configuration file:

trustzone_images/core/settings/buses/qup_access_control/config/glymur/oem_qupac_config.h
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    2. Modify the serial engine entry to grant access to the SoCCP.

        For example:

{ QUPV3\_1\_SE5, QUPV3\_PROTOCOL\_I2C, QUPV3\_MODE\_GSI,
AC\_HLOS\_SOCCP, FALSE, FALSE, FALSE }, /*USB I2C*/
3. Configure GPII access for the serial engine by adding `ac_config_1` in:

/Settings/Soc/Glymur/Core/Buses/qup_fw_ac/qup_fw_ac.dtsi
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4. When selecting a serial engine instance, follow the existing internal design to avoid conflicts.

    - `QUP_0_SE2` is used for the SPU UART.
    - `QUP_2_SE7` is used as the SoCCP debug UART.

## Related

- [Enable the debug UART in the SoCCP](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-debug-uart-soccp.html)
- [Enable a peripheral interface in the OOB subsystem](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-peripheral-interface-oob.html)
- [Configure the PCIe and USB interfaces](https://docs.qualcomm.com/doc/80-A0399-8/topic/configure-pcie-usb-interfaces.html)

Last Published: Sep 17, 2026

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