# Enable the UART interface

Enable a UART instance for the application processor (HLOS and UEFI) by
granting TrustZone access and then enabling the instance in each
subsystem device tree.

The platform supports both a standard UART and a high-speed UART (HSUART). Grant TrustZone access permission, and then enable the instance in the Linux kernel, UEFI, and XBL sources for the target UART type.

Note

Remove any existing configuration before you reconfigure an instance. To configure an instance as UART when it was previously set as SPI, review every location where it’s configured as SPI, remove those settings, and then continue.

1. Grant access permission in TrustZone in the `oem_qupac_config.h` file.

    1. Open the `oem_qupac_config.h` file.
    2. Configure the required UART instance permissions.
    3. Confirm that the subsystem in the permissions table matches the subsystem in the mapping table.
2. Enable the instance in the Linux kernel device tree.

    1. Open the Linux kernel device tree file:

/arm64/boot/dts/qcom/glymur.dtsi
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    2. Set the node status to `okay`.

uart2: serial@b88000 {
                compatible = "qcom,geni-uart";
                reg = <0x0 0x00b88000 0x0 0x4000>;
                interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
                clock-names = "se";
                pinctrl-0 = <&qup_uart2_default>;
                pinctrl-names = "default";
                status = "disabled";
            };
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3. For a UEFI high-speed UART (HSUART) use case, enable the required instance.

    1. Declare the instance in the following device tree file:

edk2-non-oss-qualcomm\Silicon\Qualcomm\Glymur\GlymurSiliconPkg\Settings\DeviceTree\Core\Buses\hsuart\hsuart.dtsi
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    2. Enable the instance in the following header file:

Silicon/Qualcomm/Glymur/GlymurSiliconPkg/Settings/DeviceTree/Include/hsuart_defines.h
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    3. Enable the required instance, for example:

#define ENABLE\_HSUART\_00
4. For a UEFI standard UART use case, enable the required instance.

    1. Declare the instance in the following device tree file:

edk2-non-oss-qualcomm\Silicon\Qualcomm\Glymur\GlymurSiliconPkg\Settings\DeviceTree\Core\Buses\uart\uart.dtsi
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    2. Enable the instance in the following header file:

Silicon/Qualcomm/Glymur/GlymurSiliconPkg/Settings/DeviceTree/Include/uart_defines.h
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    3. Enable the required instance, for example:

#define ENABLE\_UART\_00
    4. For a 2-wire UART use case, set `gpio_cts_config` and `gpio_rfr_config` to `0`.
5. For a pre-DDR XBL use case, enable the required UART instance.

    1. Declare the instance in the following source file:

QcomPkg/SocPkg/Glymur/Settings/UART/UartSettings.c
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    2. Review the default UART configuration.

        The following example shows the UART instance enabled by default in pre-DDR XBL.

UART_PROPERTIES devices =
            {
            // MAIN_PORT
            0x00894000, // uart_base
            0x008C0000, // qup_common_base
            0x2001c561, // gpio_tx_config
            0x20008571, // gpio_rx_config
            0, // gpio_cts_config
            0, // gpio_rfr_config
            0, // clock_id_index
            (void*)0, // bus_clock_id
            "gcc_qupv3_wrap2_s5_clk", // Core_clock_id
            "gcc_qupv3_wrap2_s5_clk", // Core clock str
            0, // base_freq
            0, // irq number not used
            0, // TCSR base
            0, // TCSR offset
            0, // TCSR value
            115200 // baud rate
            };
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    3. If necessary, modify the address, GPIO, and clock settings to enable a different UART instance.

## Related

- [Enable QSPI for the SPI-NOR interface](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-qspi-spi-nor-interface.html)
- [Enable a peripheral interface in the aDSP](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-peripheral-interface-adsp.html)
- [Enable the debug UART in the SoCCP](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-debug-uart-soccp.html)

Last Published: Sep 17, 2026

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