# Snapdragon X2 interfaces overview
The Snapdragon X2 Linux Mobile PC platform provides serial peripheral
buses, PCIe links, and USB ports for connecting on-board and external
devices.
Use the following overview to identify which interface fits each use
case before you configure it. The platform groups its low-speed serial
buses under the QUP v3 subsystem, provides five PCIe root complexes for
high-bandwidth storage and connectivity, and exposes six USB interfaces
for Type-C and Type-A devices. Each interface targets a distinct class
of peripherals, from touchscreens and sensors to NVMe drives and
displays.
## Peripheral interface features
The peripheral subsystem uses QUP ports to carry UART, SPI, I^2^C, and I^3^C
traffic. The platform contains 37 QUP serial engine (SE) ports: 26 QUP
SE ports for general-purpose input/output (GPIO) and 11 QUP SE ports for
the Qualcomm® Sensing Hub.
The following figure shows how the Snapdragon X2 QUP ports divide across
general-purpose I/O and the Sensing Hub, and which serial protocols each
set supports.
**Figure : QUP ports GPIO sensing hub**
The following table lists the QUP lane assignments for each supported
serial protocol.
| Generic I/O | UART | SPI | I^2^C | I^3^C |
| --- | --- | --- | --- | --- |
| `QUP_L0` | CTS | MISO | SDA | SDA |
| `QUP_L1` | RFR | MOSI | SCL | SCL |
| `QUP_L2` | Tx | SCLK | — | — |
| `QUP_L3` | Rx | `CS_0` | — | — |
| `QUP_L4` | — | `CS_1` | — | — |
| `QUP_L5` | — | `CS_2` | — | — |
| `QUP_L6` | — | `CS_3` | — | — |
The Snapdragon X2 peripheral subsystem introduces several design and
function changes from earlier platforms. The following table lists the
peripheral feature changes and their migration effect.
| Feature or technology | Change | Description | Migration |
| --- | --- | --- | --- |
| Design | QUP-based SPI-NOR | The QUP v3-based quad SPI interface for SPI-NOR provides the multi-EE
support that the latest design changes need. | Used for the storage use case. |
| Function | UEFI I^2^C moved to EDK | UEFI I^2^C moved to the open source EDK implementation, which supports
additional features. | Driver migrated to EDK. |
| Design | New subsystems introduced | The platform adds the SoC control processor (SoCCP) and out-of-band
(OOB) subsystems. SoCCP handles battery and charging functions, and OOB
handles debug functions. | Top QUP SEs can be configured to support the required protocols in these
subsystems. |
Each protocol targets a specific class of peripherals:
- **UART core** — Supports data rates up to 4 Mbps across six
high-speed UART instances. High-speed mode uses direct memory access
(DMA) to move data between the Rx and Tx buffers and system memory,
and low-speed mode uses a first-in, first-out (FIFO) buffer. Typical
use cases are a low-speed console UART, a high-speed UART for
Bluetooth, and IrDA communications.
- **SPI** — Supports controller mode at up to 50 MHz, with
programmable data bits (4 to 32 bits), programmable spacing between
transfers (SPI\_CS\_N WAIT), and programmable transfer length. Typical
use cases are the sensor hub, Qualcomm® Fingerprint Sensors, an SPI
touch panel, and a codec.
- **QSPI** — Supports controller mode at up to 100 MHz, with
programmable data bits (4 to 256 bits), programmable transfer spacing,
and programmable transfer length. Typical use cases are SPI-NOR and
high-throughput touch and trackpad.
- **I2C** — Supports the I^2^C bus protocol in Standard (100 kHz), Fast
(400 kHz), and Fast+ (1 MHz) modes with 7-bit device addressing.
Typical use cases are a touchscreen interface, sensors, an LED flash,
a charger IC, and near-field communication (NFC).
- **I3C** — Supports the I^3^C bus protocol at 12.5 MHz. Typical use
cases are a touchscreen interface, sensors, and an LED flash.
## PCIe interface features
The peripheral component interconnect express (PCIe) subsystem provides
five root complexes that conform to the PCI Express Base 5.0
Specification. The root complexes are:
- `PCIE3A_GEN5X8` — 8-lane transmit and receive
- `PCIE3B_GEN5X4` — 4-lane transmit and receive
- `PCIE4_GEN4X2` — 2-lane transmit and receive
- `PCIE5_GEN5X4` — 4-lane transmit and receive
- `PCIE6_GEN4X2` — 2-lane transmit and receive
The maximum supported rates per lane are 32.0 GT/s for Gen5, 16.0 GT/s
for Gen4, 8.0 GT/s for Gen3, 5.0 GT/s for Gen2, and 2.5 GT/s for Gen1.
The subsystem supports active state power management (ASPM) with the L1
and L1ss states, the L0, L1, L2, and L3 link power states, message
signaled interrupt (MSI), and PCI INTx interrupts.
## USB interface features
The USB subsystem provides six USB interfaces: three Type-C ports
through the PS8833 retimer (DisplayPort and USB 3.1 Gen2), two
Standard-A USB 3.1 Gen2 10 Gbps ports from a single USB 3.1 multiport
controller, and one Standard-A USB 2.0 port from the USB2S multiport
controller for the secure camera controller. The Type-C design uses a
USB Type-C Connector System Software Interface (UCSI) 2.x design, and
the power delivery (PD) and Type-C interface events are managed in the
SoC control processor (SoCCP).
The following table compares the USB features of the Snapdragon X and
Snapdragon X2 platforms.
| Feature | Snapdragon X | Snapdragon X2 |
| --- | --- | --- |
| Functional | 6 USB interfaces; 3x Type-C through PS8830 (PCIe, USB3.1 Gen2, TBT3); 2x
Standard-A USB 3.1 Gen2 10 Gbps from a single USB 3.1 multiport
controller; 1x Standard-A USB 2.0 from the USB2S multiport controller
for the secure camera controller | 6 USB interfaces; 3x Type-C through PS8833 (DisplayPort, USB3.1 Gen2);
2x Standard-A USB 3.1 Gen2 10 Gbps from a single USB 3.1 multiport
controller with independent disablement of multiport USB ports; 1x
Standard-A USB 2.0 from the USB2S multiport controller for the secure
camera controller |
| Software | Type-C UCSI-based design; PD and Type-C interface to SMB and events
managed in aDSP; UCSI design supported natively by Qualcomm
Technologies, Inc. (QTI) | Type-C UCSI 2.x-based design; PD and Type-C interface to SMB and events
managed in SoCCP; UCSI design supported natively by QTI |
| Hardware | Type-C ports at USB 3.1 Gen2 | Type-C ports at USB 3.1 Gen2 |
| USB speed | Type-C ports at 10 Gbps (SSP) in USB 3.1 Legacy mode; DisplayPort up to
10 Gbps; USB up to 10 Gbps | Type-C ports at 10 Gbps (SSP) in USB 3.1 Legacy mode; DisplayPort up to
10 Gbps; USB up to 10 Gbps |
| eUSB2 PHYs and repeaters | eUSB2 PHY; USB-C ports use the Donington PMIC repeater; USB-A ports use
a third-party repeater (NXP) | eUSB2 PHY; USB-C ports use the Barrington PMIC repeater; USB-A ports use
a third-party repeater (NXP) |
| SuperSpeed USB PHY | USB 3.1 PHY (2x multiport) | USB 3.1 PHY (2x multiport) |
| DisplayPort tunnel per port | 2x 4K displays (SST, MST) or 1x 8K display | 2x 4K displays (SST, MST) or 1x 8K display |
## Related
- [Get started with the interface configuration](https://docs.qualcomm.com/doc/80-A0399-8/topic/get-started.html)
- [Snapdragon X2 interface architecture](https://docs.qualcomm.com/doc/80-A0399-8/topic/architecture.html)
- [Configure the peripheral interfaces](https://docs.qualcomm.com/doc/80-A0399-8/topic/configure-peripheral-interfaces.html)
Last Published: Sep 17, 2026
[Previous Topic
Snapdragon X2 Linux Mobile PC interfaces guide](https://docs.qualcomm.com/bundle/publicresource/80-A0399-8/topics/landing-page.md) [Next Topic
Get started with the interface configuration](https://docs.qualcomm.com/bundle/publicresource/80-A0399-8/topics/get-started.md)