# USB controller clocks

Each USB controller uses a set of core, interface, mock UTMI, sleep, and
AHB clocks.

Use the following tables to confirm the clock names, operating
frequencies, and functions for the primary, secondary, and tertiary USB
controllers.

The following table lists the primary USB controller (USB0) clocks,
their operating frequency, and their function.

| Clock name | Operating frequency | Description |
| --- | --- | --- |
| `GCC_USB30_PRIM_MASTER_CLK` (core) | 200 MHz SuperSpeed; 66 MHz high speed | Asynchronous to the bus clock; clock rates defined within the device<br>tree node. |
| `GCC_CFG_NOC_USB3_PRIM_AXI_CLK` (cfg\_noc) | 200 MHz SuperSpeed; 66 MHz high speed | Auxiliary bus controller unit clock. |
| `GCC_AGGRE_USB3_PRIM_AXI_CLK` (iface) | 200 MHz SuperSpeed; 66 MHz high speed | Feeds the aggregator2 module, which controls data flow from the USB AXI<br>to the NoC. |
| `GCC_USB30_PRIM_MOCK_UTMI_CLK` (mock\_utmi) | 19.2 MHz | Internal controller `ref_clk` used to generate the ITP counter when<br>the USB transceiver macrocell interface (UTMI) or UTMI+ Low Pin<br>interface (ULPI) is suspended. |
| `GCC_USB30_PRIM_SLEEP_CLK` (sleep) | 32 kHz | Sleep clock. |
| `GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK` (noc\_aggr\_south) | 19.2 MHz | AHB interface clock on the south path between CFG\_NOC and USB\_ANOC. |
| `GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK` (noc\_aggr\_north) | 19.2 MHz | External reference clock source to the HS-PHY (PMIC). |

The following table lists the secondary USB controller clocks, their
operating frequency, and their function.

| Clock name | Operating frequency | Description |
| --- | --- | --- |
| `GCC_USB30_SEC_MASTER_CLK` (core) | 200 MHz SuperSpeed; 66 MHz high speed | Asynchronous to the bus clock; clock rates defined within the device<br>tree node. |
| `GCC_CFG_NOC_USB3_SEC_AXI_CLK` (cfg\_noc) | 200 MHz SuperSpeed; 66 MHz high speed | Auxiliary bus controller unit clock. |
| `GCC_AGGRE_USB3_SEC_AXI_CLK` (iface) | 200 MHz SuperSpeed; 66 MHz high speed | Feeds the aggregator2 module, which controls data flow from the USB AXI<br>to the NoC. |
| `GCC_USB30_SEC_MOCK_UTMI_CLK` (mock\_utmi) | 19.2 MHz | Internal controller `ref_clk` used to generate the ITP counter when<br>the UTMI or ULPI is suspended. |
| `GCC_USB30_SEC_SLEEP_CLK` (sleep) | 32 kHz | Sleep clock. |
| `GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK` (noc\_aggr\_south) | 19.2 MHz | AHB interface clock on the south path between CFG\_NOC and USB\_ANOC. |
| `GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK` (noc\_aggr\_north) | 19.2 MHz | External reference clock source to the HS-PHY (PMIC). |

The following table lists the tertiary USB controller (USB2) clocks,
their operating frequency, and their function.

| Clock name | Operating frequency | Description |
| --- | --- | --- |
| `GCC_USB30_TERT_MASTER_CLK` (core) | 200 MHz SuperSpeed; 66 MHz high speed | Asynchronous to the bus clock; clock rates defined within the device<br>tree node. |
| `GCC_CFG_NOC_USB3_TERT_AXI_CLK` (cfg\_noc) | 200 MHz SuperSpeed; 66 MHz high speed | Auxiliary bus controller unit clock. |
| `GCC_AGGRE_USB3_TERT_AXI_CLK` (iface) | 200 MHz SuperSpeed; 66 MHz high speed | Feeds the aggregator2 module, which controls data flow from the USB AXI<br>to the NoC. |
| `GCC_USB30_TERT_MOCK_UTMI_CLK` (mock\_utmi) | 19.2 MHz | Internal controller `ref_clk` used to generate the ITP counter when<br>the UTMI or ULPI is suspended. |
| `GCC_USB30_TERT_SLEEP_CLK` (sleep) | 32 kHz | Sleep clock. |
| `GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK` (noc\_aggr\_south) | 19.2 MHz | AHB interface clock on the south path between CFG\_NOC and USB\_ANOC. |
| `GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK` (noc\_aggr\_north) | 19.2 MHz | External reference clock source to the HS-PHY (PMIC). |

## Related

- [USB controller interrupts](https://docs.qualcomm.com/doc/80-A0399-8/topic/usb-controller-interrupts.html)
- [USB controller reset control](https://docs.qualcomm.com/doc/80-A0399-8/topic/usb-controller-reset-control.html)
- [Enable a USB controller in Device mode](https://docs.qualcomm.com/doc/80-A0399-8/topic/enable-usb-controller-device-mode.html)

Last Published: Sep 17, 2026

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