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# Instructions Instruction encoding is described in [Instruction encoding](https://docs.qualcomm.com/doc/80-N2040-60/topic/instruction-encoding.html). For detailed descriptions of the Hexagon processor instructions, see [Instruction set](https://docs.qualcomm.com/doc/80-N2040-60/topic/instruction-set.html). ## Hexagon processor instruction syntax Note The notation described here does not appear in actual assembly language instructions. It is used only to specify the instruction syntax and behavior. Most Hexagon processor instructions have the following syntax: dest = instr_name(source1,source2,...)[:option1][:option2]... Copy to clipboard The item specified on the left-hand side (LHS) of the equation is assigned the value specified by the right-hand side (RHS). For example: R2 = add(R3,R1) // Add R3 and R1, assign result to R2 Copy to clipboard - Courier New font is used for instructions - Square brackets enclose optional items, for example, [:sat] means that saturation is optional - Braces indicate a choice of items. For example, {Rs,#s16}, means that the instruction uses either Rs or a signed 16-bit immediate value. Instruction symbols | **Symbol** | **Example** | **Meaning** | | --- | --- | --- | | = | R2 = R3 | Assignment of RHS to LHS. | | # | R1 = #1 | Immediate constant value. | | ## | ##2147483647 | 32-bit immediate constant value. | | 0x | 0xBABE | Hexadecimal number prefix. | | mem**x** | R2 = mem**w**(R3) | Access memory. **x** specifies the size and type of access. | | ; | R2 = R3; R4 = R5; | Instruction delimiter, or end of the instruction. | | { … } | {R2 = R3; R5 = R6} | Instruction packet delimiter; indicates a group of parallel
instructions. | | ( … ) | R2 = memw(R0 + #100) | Source list delimiter. | | :endloop*X* | :endloop0 | Loop end. X specifies a loop instruction (0 or 1). | | :t | if (P0.new) jump:t target | Direction hint (jump taken). | | :nt | if (!P1.new) jump:nt target | Direction hint (jump not taken). | | :sat | R2 = add(R1,R2):sat | Saturate the result. | | :rnd | R2 = mpy(R1.H,R2.H):rnd | Round theresult. | | :carry | R5:4=add(R1:0,R3:2,P1):carry | Predicate used as carry input and output. | | :<<16 | R2 = add(R1.L,R2.L):<<16 | Shift the result left by a halfword. | | :mem\_noshuf | {memw(R5) = R2;

R3 = memh(R6)}:mem\_noshuf | Inhibit load/store reordering ([Section 5.5](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#slot-1-store-with-slot-0-load)). | ### Numeric operands [Instruction operands](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-tbl-instruction-operands) lists the notation that describes numeric operands in the syntax and behavior of instructions. Instruction operands | **Symbol** | **Meaning** | **Min** | **Max** | **Example** | | --- | --- | --- | --- | --- | | #uN | Unsigned N-bit immediate value | 0 | 2^N-1^ | R2 = #u16 | | #sN | Signed N-bit immediate value | -2^N-1^ | 2^N-1^-1 | R2 = add(R3,#s16) | | #mN | Signed N-bit immediate value | -(2^N-1^-1) | 2^N-1^-1 | Rd = mpyi(Rs,#m9) | | #uN:S | Unsigned N-bit immediate value representing integral multiples of 2S in specified range | 0 | (2^N-1^) x 2^S^ | R2 = memh(#u16:1) | | #sN:S | Signed N-bit immediate value representing integral multiples of 2S in specified range | (-2^N-1^) x 2^S^ | (2^N-1^-1) x 2^S^ | Rd = memw(Rs++#s4:2) | | #rN:S | Same as #sN:S, but value is offset from PC of current packet | (-2^N-1^) x 2^S^ | (2^N-1^-1) x 2^S^ | call #r22:2 | | usat_N | Saturate value to unsigned N-bit number | 0 | 2^N-1^ | usat₁₆(Rs) | | sat_N | Saturate value to signed N-bit number | -2^N-1^ | 2^N-1^-1 | sat16(Rs) | | sxt x->y | Sign-extend value from x to y bits |

| Rss >>> offset | The #uN, #sN, and #mN symbols specify immediate operands in instructions. The # symbol appears in the actual instruction to indicate the immediate operand. The #rN symbol specifies loop and branch destinations in instructions. The # symbol does not appear in the program; instead, the entire #rN symbol (including its :S suffix) represents a loop or branch symbol whose numeric value is determined by the assembler and linker. For example: call my_proc // programmed Instruction Copy to clipboard is described in the instruction definitions as call #r22:2 // #r22:2 -> scaled 22-bit PC-rel addr value Copy to clipboard The :S suffix indicates that the S least-significant bits in a value are implied zero bits and therefore not encoded in the instruction. The implied zero bits are called scale bits. For example, #s4:2 denotes a signed immediate operand represented by four bits encoded in the instruction, and two scale bits. The possible values for this operand are -32, -28, -24, -20, -16, -12, -8, -4, 0, 4, 8, 12, 16, 20, 24, and 28. The ## symbol specifies a 32-bit immediate operand in an instruction (including a loop or branch destination). The ## symbol indicates the operand in the actual instruction. Examples of operand symbols: Rd = add(Rs,#s16) // #s16 -> signed 16-bit imm value Rd = memw(Rs++#s4:2) // #s4:2 -> scaled signed 4-bit imm value call #r22:2 // #r22:2 -> scaled 22-bit PC-rel addr value Rd = ##u32 // ##u32 -> unsigned 32-bit imm value Copy to clipboard Note When an instruction contains more than one immediate operand, the operand symbols are specified in upper and lowercase (for example, #uN and #UN) to indicate where they appear in the instruction encodings ### Terminology [Data symbols](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-tbl-data-symbols) lists the symbols Hexagon processor instruction names use to specify the supported data types. Data symbols | **Size** | **Symbol** | **Type** | | --- | --- | --- | | 8-bit | B | Byte | | 8-bit | UB | Unsigned byte | | 16-bit | H | Half word | | 16-bit | UH | Unsigned half word | | 32-bit | W | Word | | 32-bit | UW | Unsigned word | | 64-bit | D | Double word | ### Register operands The following notation describes register operands in the syntax and behavior of instructions: Rds[.elst] Copy to clipboard The ds field indicates the register operand type andbit size (as defined in [Register symbols](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-tbl-register-symbols)). | **Symbol** | **Operand type** | **Size (in bits)** | | --- | --- | --- | | d | Destination | 32 | | dd | Destination | 64 | | s | First source | 32 | | ss | First source | 64 | | t | Second source | 32 | | tt | Second source | 64 | | u | Third source | 32 | | uu | Third source | 64 | | x | Source *and* destination | 32 | | xx | Source *and* destination | 64 | | | | | Examples of the ds field that describe instruction syntax: Rd = neg(Rs) // Rd -> 32-bit dest, Rs 32-bit source Rd = xor(Rs,Rt) // Rt -> 32-bit second source Rx = insert(Rs,Rtt) // Rx -> both source and dest Copy to clipboard Examples of the ds field that describe instruction behavior: Rdd = Rss + Rtt // Rdd, Rss, Rtt -> 64-bit registers Copy to clipboard The optional elst (element size and type) field specifies parts of a register when the register is used as a vector. It can specify the following values: - A signed or unsigned byte, halfword, or word within the register (as defined in [register field symbols](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-fig-register-field-symbols)) - A bit field within the register (as defined in [register bit field symbols](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-tbl-register-bit-field-symbols)) Examples of the elst field: EA = Rt.h[1] // .h[1] -> bit field 31:16 in Rt Pd = (Rss.u64 > Rtt.u64) // .u64 -> unsigned 64-bit value Rd = mpyu(Rs.L,Rt.H) // .L/.H -> low/high 16-bit fields Copy to clipboard Note The control and predicate registers use the same notation as general registers, but are written as Cx and Px (respectively) instead of Rx. **Register field symbols** | Symbol | Meaning | | --- | --- | | .sN | Bits [N-1:0] are treated as a N-bit signed number.

For example, R0.s16 means that the least significant 16-bits of R0 are treated as a 16-bit signed number. | | .uN | Bits [N-1:0] are treated as a N-bit unsigned number. | | .H | Most-significant 16 bits of a 32-bit register. | | .L | Least-significant 16 bits of a 32-bit register. | ## Instruction classes The Hexagon processor instructions assigns instructions to instruction classes. Classes determine the combinations of instructions that execute in parallel ([instruction packets](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-prm-instruction-packets)). [Instruction classes and subclasses](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-tbl-instruction-classes-and-subclasses) lists the instruction classes and how they form instruction packets. Instruction classes logically correspond with instruction types, so they serve as mnemonics for looking up specific instructions. For instance, the ALU32 class contains ALU instructions that operate on 32-bit operands. | **Class** | **Subclass** | **Description** | | --- | --- | --- | | [ALU32](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#alu32) | | 32-bit ALU operations | | [ALU32](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#alu32) | [ALU32 ALU](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#alu32-alu) | Arithmetic and logical | | [ALU32](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#alu32) | [ALU32 PERM](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#alu32-perm) | Permute | | [ALU32](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#alu32) | [ALU32 PRED](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#alu32-pred) | Predicate operations | | [CR](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#cr) | | Control register access and loops | | [JR](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#jr) | | Jumps (register indirect addressing mode) | | [J](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#j) | | Jumps (PC-relative addressing mode) | | [LD](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#ld) | | Memory load operations | | [MEMOP](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#memop) | | Memory operations | | [NV](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#nv) | | New-value operations | | [NV](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#nv) | [NV J](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#nv-j) | New-value jumps | | [NV](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#nv) | [NV ST](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#nv-st) | New-value stores | | [ST](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#st) | | Memory store operations; allocate stack frame | | [System](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#system) | | Operating system access | | [System](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#system) | [System user](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#system-user) | Application-level access | | [XTYPE](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype) | | Assorted operations | | [XTYPE](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype) | [XTYPE ALU](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype-alu) | 64-bit ALU operations | | [XTYPE](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype) | [XTYPE bit](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype-bit) | Bit operations | | [XTYPE](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype) | [XTYPE complex](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype-complex) | Complex math (using real and imaginary numbers) | | [XTYPE](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype) | [XTYPE FP](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype-fp) | Floating point operations | | [XTYPE](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype) | [XTYPE MPY](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype-mpy) | Multiply operations | | [XTYPE](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype) | [XTYPE perm](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype-perm) | Vector permute and format conversion (pack, splat, swizzle) | | [XTYPE](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype) | [XTYPE PRED](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype-pred) | Predicate operations | | [XTYPE](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype) | [XTYPE SHIFT](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#xtype-shift) | Shift operations (with optional ALU operations) | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ## Instruction packets Hexagon groups instructions into very long instruction word (VLIW) packets for parallel execution, where each packet contains one to four instructions. A program can contain packets of varying lengths. Hexagon executes individual instructions, which are not explicitly grouped in packets, as packets containing a single instruction. Vector instructions operate on single instruction multiple data (SIMD) vectors. Software explicitly defines instruction packets. Instruction packets are expressed in assembly language by enclosing groups of instructions in curly braces. For example, two instructions grouped in a packet: { R0 = R1; R2 = R3 } Copy to clipboard Four instructions grouped in a packet: { R8 = memh(R3++#2); R12 = memw(R1++#4); R = mpy(R10,R6):<<1:sat; R7 = add(R9,#2); } Copy to clipboard Packets have restrictions on instruction combinations. The instruction class of the instructions in a packet determines the primary restriction. Packet formation is subject to the following constraints: - [Resource constraints](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-prm-resource-constraints) determine how many instructions of a specific type can appear in a packet. - The Hexagon processor has a fixed number of execution units. - Each instruction executes on a particular type of unit and each unit can process at most one instruction at a time. - For example: the Hexagon processor contains only two load units so an instruction packet with three load instructions is invalid. - [Grouping constraints](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-prm-grouping-constraints) are a small set of rules that apply beyond the resource constraints. - [Dependency constraints](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-prm-instructions-dependency-constraints) ensure that no write-after-write hazards exist in a packet. - [Ordering constraints](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-prm-ordering-constraints) dictate the ordering of instructions within a packet. - [Alignment constraints](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-prm-alignment-constraints) dictate the placement of packets in memory. ### Packet execution semantics Packets are defined to have parallel execution semantics. The following defines the execution behavior of a packet: - Instructions in the packet read their source registers in parallel. - Instructions in the packet execute. - Instructions in the packet write their destination registers in parallel. For example, consider the following packet: { R2 = R3; R3 = R2; } Copy to clipboard In the first phase, registers R3 and R2 are read from the register file. After execution, R2 is written with the old value of R3 and R3 is written with the old value of R2. The result of this packet is the swap of the values of R2 and R3. Note [Dual stores](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#dual-stores), [Dual jumps](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#dual-jumps), [New-value stores](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#new-value-stores), [New-value compare jumps](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#new-value-compare-jumps), and [Dot-new predicates](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#dot-new-predicates) have non-parallel execution semantics. ### Sequencing semantics Packets of any length can freely mix in code. A packet is an atomic unit: in essence, a single large instruction. From the program perspective, a packet either executes to completion or not at all; it never partially executes. For example, if a packet causes a memory exception, Hexagon establishes the exception point before the packet. A packet containing multiple load/store instructions can require service from the external system. For instance, consider a packet that performs two load operations that both miss in the cache. The packet requires the memory system to supply the data: - From the memory system perspective, the two resulting load requests are processed serially. - From the program perspective, however, both load operations must complete before the packet can complete. Thus, the packet is atomic from the program perspective. Packets have a single PC address, which is the address of the start of the packet. Branch instructions cannot branch into the middle of a packet. Architecturally, packets execute to completion—including updating all registers and memory—before the next packet begins. As a result, application programs are not exposed to any pipeline artifacts. ### Resource constraints A packet cannot use more hardware resources than are physically available on the processor. For instance, the Hexagon processor has only two load units; so a packet with three load instructions is invalid. The behavior of such a packet is undefined. The assembler automatically rejects packets that oversubscribe the hardware resources. The processor supports up to four parallel instructions. The instructions execute in four parallel pipelines, which are referred to as slots. The four slots are named Slot 0, Slot 1, Slot 2, and Slot 3. Note The endloopN instructions ([loop end](https://docs.qualcomm.com/doc/80-N2040-60/topic/program-flow.html#v79-prm-loop-end)) do not use any slots. Each instruction belongs to specific [instruction classes](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-prm-instruction-classes). For example, jumps belong to instruction class J and loads belong to instruction class LD. The class of an instruction determines the slot in which the instruction can execute. [Packet grouping combinations](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-fig-packet-grouping-combinations) shows which instruction classes can be assigned to each of the four slots. **Figure 3-2 Packet grouping combinations** ### Grouping constraints A few restrictions determine what constitutes a valid packet. The assembler ensures that packets follow valid grouping rules. If a packet executes that violates a grouping rule, the behavior is undefined. The following rules must be followed: - Dot-new conditional instructions ([dot-new predicates](https://docs.qualcomm.com/doc/80-N2040-60/topic/conditional-execution.html#v79-prm-dot-new-predicates)) must be grouped in a packet with an instruction that generates dot-new predicates. - ST-class instructions can be placed in Slot 1. In this case, Slot 0 normally must contain a second ST-class instruction ([dual stores](https://docs.qualcomm.com/doc/80-N2040-60/topic/memory.html#v79-prm-dual-stores)). - J-class instructions can be placed in Slots 2 or 3. However, only certain combinations of program flow instructions (J or JR) can be grouped in a packet ([dual jumps](https://docs.qualcomm.com/doc/80-N2040-60/topic/program-flow.html#v79-prm-dual-jumps)). Otherwise, at most one program flow instruction is allowed in a packet. Some Jump and compare-Jump instructions can execute on slots 0 or 1, excluding calls, such as the following: - Instructions of the form “Pd=cmp.xx(); if(Pd.new)jump:hint<target>” - Instructions of the form “If(Pd[.new]) jump[:hint] <target>” - The “jump<target>”” instruction - JR-class instructions can be placed in Slot 2. However, when encoded in a duplex jumpr R31 instruction can be placed in Slot 0 ([duplexes](https://docs.qualcomm.com/doc/80-N2040-60/topic/instruction-encoding.html#v79-prm-duplexes)). - Restrictions limit the instructions that can appear in a packet at the setup or end of a hardware loop ([pipelined hardware loops](https://docs.qualcomm.com/doc/80-N2040-60/topic/program-flow.html#v79-prm-pipelined-hardware-loops)). - A transfer to USR cannot be grouped with a floating point instruction ([user status register](https://docs.qualcomm.com/doc/80-N2040-60/topic/registers.html#v79-prm-user-status-register)). - The SYSTEM-class instructions include prefetch, cache operations, bus operations, load locked, and store conditional instructions ([cache memory](https://docs.qualcomm.com/doc/80-N2040-60/topic/memory.html#v79-prm-cache-memory)). These instructions have the following grouping rules: - The brkpt, trap, pause, icinva, isync, and syncht instructions are solo instructions. They must not be grouped with other instructions in a packet. - The memw\_locked, memd\_locked, l2fetch, and trace instructions must execute on Slot 0. They must be grouped only with ALU32 or (non-FP) XTYPE instructions. - The dccleana, dcinva, dccleaninva, and dczeroa instructions must execute on Slot 0. Slot 1 must be empty or an ALU32 instruction. ### Dependency constraints Instructions in a packet cannot write to the same destination register. The assembler automatically flags such packets as invalid. If the processor executes a packet with two writes to the same general register, the processor raises an error exception. If the processor executes a packet that performs multiple writes to the same predicate or control register, the behavior is undefined. Three special cases exist for this rule: - Conditional writes are only allowed to target the same destination register when at most one of the writes is performed ([dependency constraints](https://docs.qualcomm.com/doc/80-N2040-60/topic/conditional-execution.html#v79-prm-conditional-dependency-constraints)). - The overflow flag in the status register has defined behavior when multiple instructions write to it ([user status register](https://docs.qualcomm.com/doc/80-N2040-60/topic/registers.html#v79-prm-user-status-register)). Do not group instructions that write to the entire user status register (for example, USR = R2) in a packet with any instruction that writes to a bit in the user status register. - Multiple compare instructions may target the same predicate register to perform a logical AND of the results ([auto-and predicates](https://docs.qualcomm.com/doc/80-N2040-60/topic/conditional-execution.html#v79-prm-auto-and-predicates)). ### Ordering constraints In assembly code, instructions can appear in a packet in any order except for [dual jumps](https://docs.qualcomm.com/doc/80-N2040-60/topic/program-flow.html#v79-prm-dual-jumps). The assembler automatically encodes instructions in the packet in the proper order. In the binary encoding of a packet, the instructions must be ordered from Slot 3 down to Slot 0. If the packet contains fewer than four instructions, any unused slot is skipped—a NOP is unnecessary as the hardware handles the proper spacing of the instructions. In memory, instructions in a packet must appear in strictly decreasing slot order. Additionally, if an instruction can go in a higher-numbered slot, and that slot is empty, it must move into the higher- numbered slot. For example, if a packet contains three instructions and slot 1 is not used, encode the instructions in the packet as follows: - Slot 3 instruction at the lowest address - Slot 2 instruction follows the Slot 3 instruction - Slot 0 instructions at the last (highest) address If a packet contains a single load or store instruction, that instruction must go in Slot 0, which is the highest address. As an example, a packet that contains both LD and ALU32 instructions must be ordered so the LD is in Slot 0 and the ALU32 in another slot. ### Alignment constraints Packets have the following constraints on their placement or alignment in memory: - Packets must be word-aligned (32-bit). If the processor executes an improperly aligned packet, it raises an error exception ([exceptions](https://docs.qualcomm.com/doc/80-N2040-60/topic/program-flow.html#v79-prm-program-flow-exceptions)). - Packets should not wrap the address space. If address wraparound occurs, the processor behavior is undefined. No other core-based restrictions exist for code placement or alignment. If the processor branches to a packet that crosses a 16-byte address boundary, the resulting instruction fetch stalls for one cycle. Packets that are jump targets or loop body entries can be explicitly aligned to ensure that this stall does not occur ([branches to and from packets](https://docs.qualcomm.com/doc/80-N2040-60/topic/program-flow.html#v79-prm-branches-to-and-from-packets)). ## Instruction intrinsics To support efficient coding of the time-critical sections of a program (without resorting to assembly language), the C compilers support intrinsics that directly express Hexagon processor instructions from within C code. For example: int main() { long long v1 = 0xFFFF0000FFFF0000LL; long long v2 = 0x0000FFFF0000FFFFLL; long long result; // Find the minimum for each half-word in a 64-bit vector result = Q6_P_vminh_PP(v1,v2); } Copy to clipboard Intrinsics are defined for most of the Hexagon processor instructions. ## Compound instructions The Hexagon processor supports compound instructions, which encode pairs of common operations in a single instruction. For example, each of the following is a single compound instruction: dealloc_return // Deallocate frame and return R2 &= and(R1, R0) // And and and R7 = add(R4, sub(#15, R3)) // Subtract and add R3 = sub(#20, asl(R3, #16)) // Shift and subtract R5 = add(R2, mpyi(#8, R4)) // Multiply and add { // Compare and jump P0 = cmp.eq (R2, R5) if (P0.new) jump:nt target } { // Register transfer and jump R2 = #15 jump target } Copy to clipboard Compound instructions reduce code size and improve code performance. Note Compound instructions (except for X-and-jump as shown here) have distinct assembly syntax from the instructions they are composed of. ## Duplex instructions To reduce code size, the Hexagon processor supports duplex instructions, which encode pairs of common instructions in a 32-bit instruction container. Unlike [compound instructions](https://docs.qualcomm.com/doc/80-N2040-60/topic/instructions.html#v79-prm-compound-instructions), duplex instructions do not have distinct syntax - in assembly code they appear identical to the instructions they are composed of. The assembler is responsible for recognizing when a pair of instructions can be encoded as a single duplex rather than a pair of regular instruction words. To fit two instructions into a single 32-bit word, [duplexes](https://docs.qualcomm.com/doc/80-N2040-60/topic/instruction-encoding.html#v79-prm-duplexes) are limited to a subset of the most common instructions (load, store, branch, ALU), and the most common register operands. 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