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# Introduction The Qualcomm Hexagon™ processor is a general-purpose digital signal processor designed for high performance and low power. ## Hexagon V79 processor architecture ### Memory The Hexagon processor features a unified byte-addressable memory. This memory has a single 32-bit virtual address space, which holds both instructions and data. It operates in little endian mode. The load/store architecture supports a complete set of addressing modes for both compiler code generation and DSP application programming. #### Cache memory Memory accesses are cached or uncached. Separate L1 instruction and data caches exist for program code and data. A unified L2 cache is partly or wholly configured as tightly coupled memory (TCM). #### Virtual memory Memory is addressed virtually, with virtual-to-physical translation handled by system software. Virtual memory supports the implementation of memory management and memory protection in a hardware-independent manner. ### Registers The Hexagon processor has two sets of registers: [General registers](https://docs.qualcomm.com/doc/80-N2040-60/topic/registers.html#v79-prm-general-registers) and [Control registers](https://docs.qualcomm.com/doc/80-N2040-60/topic/registers.html#v79-prm-control-registers). The general registers include thirty-two 32-bit registers (named R0 through R31), which are accessed either as single registers or as aligned 64-bit register pairs. The general registers contain all data, including pointer, scalar, vector, and accumulator data. The control registers include special-purpose registers such as program counter, status register, loop registers, and so on. ### Instruction sequencer The instruction sequencer processes packets of one to four instructions in each cycle. If a packet contains more than one instruction, the instructions execute in parallel. The instruction combinations allowed in a packet are limited to the instruction types that can execute in parallel in the four execution units (shown in [Hexagon V79 processor architecture](https://docs.qualcomm.com/doc/80-N2040-60/topic/introduction.html#fig-v79-processor-architecture)). **Hexagon V79 processor architecture** ### Execution units The two execution units (X units) are identical. Each includes a 64-bit shifter and a vector multiply/accumulate unit with four 16 x 16 multipliers to support both scalar and vector instructions. These units also perform 32-bit and 64-bit ALU instructions, as well as jump and loop instructions. Note Each execution unit supports floating-point instructions. ### Load/store units The two load/store units can operate on bytes (8-bit), halfwords (16-bit), words (32- bit), or double words (64-bit). To increase the number of instruction combinations allowed in packets, the load units also support 32-bit ALU instructions. ## Instruction set For the Hexagon processor to achieve large amounts of work per cycle, the instruction set has the following properties: - Static grouping (VLIW) architecture - Static fusing of simple dependent instructions - Extensive compound instructions - A large set of SIMD and application-specific instructions To support efficient compilation, the instruction set is orthogonal with respect to registers, addressing modes, and load/store access size. ### Addressing modes The Hexagon processor supports the following memory addressing modes: - 32-bit absolute - 32-bit absolute-assign - Absolute with register offset - Global pointer relative - Indirect - Indirect with offset - Indirect with register offset - Indirect with auto-increment (immediate or register) - Circular with auto-increment (immediate or register) - Bit-reversed with auto-increment register For example: R2 = memw(##myvariable) R2 = memw(R3=##myvariable) R2 = memw(R4<<#3+##myvariable) R2 = memw(GP+#200) R2 = memw(R1) R2 = memw(R3+#100) R2 = memw(R3+R4<<#2) R2 = memw(R3++#4) R2 = memw(R0++M1) R0 = memw(R2++#8:circ(M0)) R0 = memw(R2++I:circ(M0)) R2 = memw(R0++M1:brev) Copy to clipboard Auto-increment with register addressing uses one of the two dedicated address-modify registers M0 and M1 (which are part of the control registers). ### Program flow The Hexagon processor supports zero-overhead hardware loops. For example: loop0(start,#3) // loop 3 times start: { R0 = mpyi(R0,R0) } :endloop0 Copy to clipboard The loop instructions support loop nesting, with few restrictions on their use. Software branches may use a predicated branch mechanism. Explicit compare instructions generate a predicate bit, which conditional branch instructions then test. For example: P1 = cmp.eq(R2, R3) if (P1) jump end if (!P1) call function Copy to clipboard Jumps and subroutine calls are conditional or unconditional, and support both PC-relative and register indirect addressing modes. For example: jump end // PC-relative jumpr R1 // register indirect call function callr R2 Copy to clipboard The subroutine call instructions store the return address in register R31. Subroutine returns are performed using a jump indirect instruction through this register. For example: jumpr R31 // Subroutine return Copy to clipboard Two program flow instructions can be grouped into one packet. ### Instruction pipeline Pipeline restrictions do not constrain instruction scheduling. The hardware resolves pipeline hazards. Last Published: Jan 16, 2025 [Next Topic Revision history](https://docs.qualcomm.com/bundle/publicresource/80-N2040-60/topics/revision.md)