# HVX ISA quick reference ## [Histogram](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-histogram) - vhist - vhist(Qv4) ## [Weighted Histogram](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-weighted-histogram) - vwhist256 - vwhist256(Qv4) - vwhist256:sat - vwhist256(Qv4):sat - vwhist128 - vwhist128(Qv4) - vwhist128(#u1) - vwhist128(Qv4,#u1) ## [Predicate operations](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-predicate-operations) - Qd4.h=vshuffe(Qs4.w,Qt4.w) - Qd4.b=vshuffe(Qs4.h,Qt4.h) - Qd4=or(Qs4,Qt4) - Qd4=and(Qs4,Qt4) - Qd4=xor(Qs4,Qt4) - Qd4=or(Qs4,!Qt4) - Qd4=and(Qs4,!Qt4) ## [Combine](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-combine) - if (Ps) Vdd=vcombine(Vu,Vv) - if (!Ps) Vdd=vcombine(Vu,Vv) - Vdd=vcombine(Vu,Vv) ## [In-lane shuffle](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-in-lane-shuffle) - Vdd.h=vshuffoe(Vu.h,Vv.h) - Vdd.b=vshuffoe(Vu.b,Vv.b) ## [Swap](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-swap) - Vdd=vswap(Qt4,Vu,Vv) ## [Sign/Zero extension](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-sign-zero-extension) - Vdd.uh=vzxt(Vu.ub) - Vdd.h=vsxt(Vu.b) - Vdd.uw=vzxt(Vu.uh) - Vdd.w=vsxt(Vu.h) ## [Arithmetic](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-arithmetic) - Vdd.b=vadd(Vuu.b,Vvv.b) - Vdd.b=vsub(Vuu.b,Vvv.b) - Vdd.h=vadd(Vuu.h,Vvv.h) - Vdd.h=vsub(Vuu.h,Vvv.h) - Vdd.w=vadd(Vuu.w,Vvv.w) - Vdd.w=vsub(Vuu.w,Vvv.w) - Vdd.ub=vadd(Vuu.ub,Vvv.ub):sat - Vdd.ub=vsub(Vuu.ub,Vvv.ub):sat - Vdd.uh=vadd(Vuu.uh,Vvv.uh):sat - Vdd.uh=vsub(Vuu.uh,Vvv.uh):sat - Vdd.uw=vadd(Vuu.uw,Vvv.uw):sat - Vdd.uw=vsub(Vuu.uw,Vvv.uw):sat - Vdd.b=vadd(Vuu.b,Vvv.b):sat - Vdd.b=vsub(Vuu.b,Vvv.b):sat - Vdd.h=vadd(Vuu.h,Vvv.h):sat - Vdd.h=vsub(Vuu.h,Vvv.h):sat - Vdd.w=vadd(Vuu.w,Vvv.w):sat - Vdd.w=vsub(Vuu.w,Vvv.w):sat - Vdd.uw=vadd(Vuu.w,Vvv.w):sat - Vdd.uw=vsub(Vuu.w,Vvv.w):sat ## [Predicate operations](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-predicate-operations) - Qd4=not(Qs4) ## [Byte-conditinal vector assign](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-byte-conditinal-vector-assign) - Vd=vand(Qv4,Vu) - Vd=vand(!Qv4,Vu) ## [Min/max](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-min-max) - Vd.sf=vmax(Vu.sf,Vv.sf) - Vd.sf=vmin(Vu.sf,Vv.sf) - Vd.hf=vmax(Vu.hf,Vv.hf) - Vd.hf=vmin(Vu.hf,Vv.hf) - Vd.b=vmax(Vu.b,Vv.b) - Vd.b=vmin(Vu.b,Vv.b) - Vd.ub=vmax(Vu.ub,Vv.ub) - Vd.ub=vmin(Vu.ub,Vv.ub) - Vd.uh=vmax(Vu.uh,Vv.uh) - Vd.uh=vmin(Vu.uh,Vv.uh) - Vd.h=vmax(Vu.h,Vv.h) - Vd.h=vmin(Vu.h,Vv.h) - Vd.w=vmax(Vu.w,Vv.w) - Vd.w=vmin(Vu.w,Vv.w) - Vd.uw=vmax(Vu.uw,Vv.uw) - Vd.uw=vmin(Vu.uw,Vv.uw) ## [Absolute value](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-absolute-value) - Vd.b=vabs(Vu.b) - Vd.b=vabs(Vu.b):sat - Vd.h=vabs(Vu.h) - Vd.h=vabs(Vu.h):sat - Vd.w=vabs(Vu.w) - Vd.w=vabs(Vu.w):sat - Vd.ub=vabs(Vu.b) - Vd.uh=vabs(Vu.h) - Vd.uw=vabs(Vu.w) ## [Arithmetic](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-arithmetic) - Vd.b=vadd(Vu.b,Vv.b) - Vd.b=vsub(Vu.b,Vv.b) - Vd.h=vadd(Vu.h,Vv.h) - Vd.h=vsub(Vu.h,Vv.h) - Vd.w=vadd(Vu.w,Vv.w) - Vd.w=vsub(Vu.w,Vv.w) - Vd.ub=vadd(Vu.ub,Vv.ub):sat - Vd.ub=vsub(Vu.ub,Vv.ub):sat - Vd.uh=vadd(Vu.uh,Vv.uh):sat - Vd.uh=vsub(Vu.uh,Vv.uh):sat - Vd.uw=vadd(Vu.uw,Vv.uw):sat - Vd.uw=vsub(Vu.uw,Vv.uw):sat - Vd.b=vadd(Vu.b,Vv.b):sat - Vd.b=vsub(Vu.b,Vv.b):sat - Vd.h=vadd(Vu.h,Vv.h):sat - Vd.h=vsub(Vu.h,Vv.h):sat - Vd.w=vadd(Vu.w,Vv.w):sat - Vd.w=vsub(Vu.w,Vv.w):sat - Vd.uh=vadd(Vu.h,Vv.h):sat - Vd.uh=vsub(Vu.h,Vv.h):sat - Vd.ub=vadd(Vu.ub,Vv.b):sat - Vd.ub=vsub(Vu.ub,Vv.b):sat ## [Arithmetic with carry bit](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-arithmetic-with-carry-bit) - Vd.w=vadd(Vu.w,Vv.w,Qs4):carry:sat - Vd.w=vadd(Vu.w,Vv.w,Qx4):carry - Vd.w=vsub(Vu.w,Vv.w,Qx4):carry - Vd.w,Qe4=vadd(Vu.w,Vv.w):carry - Vd.w,Qe4=vsub(Vu.w,Vv.w):carry ## [Logical operations](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-logical-operations) - Vd=vand(Vu,Vv) - Vd=vor(Vu,Vv) - Vd=vxor(Vu,Vv) - Vd=vnot(Vu) ## [Copy](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-copy) - if (Ps) Vd=Vu - if (!Ps) Vd=Vu - Vd=Vu ## [Temporary Assignment](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-temporary-assignment) - Vdd.tmp=vcombine(Vu,Vv) - Vd.tmp=Vu ## [Average](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-average) - Vd.ub=vavg(Vu.ub,Vv.ub) - Vd.ub=vavg(Vu.ub,Vv.ub):rnd - Vd.uh=vavg(Vu.uh,Vv.uh) - Vd.uh=vavg(Vu.uh,Vv.uh):rnd - Vd.uw=vavg(Vu.uw,Vv.uw) - Vd.uw=vavg(Vu.uw,Vv.uw):rnd - Vd.b=vavg(Vu.b,Vv.b) - Vd.b=vavg(Vu.b,Vv.b):rnd - Vd.b=vnavg(Vu.b,Vv.b) - Vd.h=vavg(Vu.h,Vv.h) - Vd.h=vavg(Vu.h,Vv.h):rnd - Vd.h=vnavg(Vu.h,Vv.h) - Vd.w=vavg(Vu.w,Vv.w) - Vd.w=vavg(Vu.w,Vv.w):rnd - Vd.w=vnavg(Vu.w,Vv.w) - Vd.h=vnavg(Vu.uh,Vv.uh) - Vd.w=vnavg(Vu.uw,Vv.uw) - Vd.b=vnavg(Vu.ub,Vv.ub) ## [Compare vectors](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-compare-vectors) - Qd4=vcmp.gt(Vu.w,Vv.w) - Qx4&=vcmp.gt(Vu.w,Vv.w) - Qx4|=vcmp.gt(Vu.w,Vv.w) - Qx4^=vcmp.gt(Vu.w,Vv.w) - Qd4=vcmp.eq(Vu.w,Vv.w) - Qx4&=vcmp.eq(Vu.w,Vv.w) - Qx4|=vcmp.eq(Vu.w,Vv.w) - Qx4^=vcmp.eq(Vu.w,Vv.w) - Qd4=vcmp.gt(Vu.h,Vv.h) - Qx4&=vcmp.gt(Vu.h,Vv.h) - Qx4|=vcmp.gt(Vu.h,Vv.h) - Qx4^=vcmp.gt(Vu.h,Vv.h) - Qd4=vcmp.eq(Vu.h,Vv.h) - Qx4&=vcmp.eq(Vu.h,Vv.h) - Qx4|=vcmp.eq(Vu.h,Vv.h) - Qx4^=vcmp.eq(Vu.h,Vv.h) - Qd4=vcmp.gt(Vu.b,Vv.b) - Qx4&=vcmp.gt(Vu.b,Vv.b) - Qx4|=vcmp.gt(Vu.b,Vv.b) - Qx4^=vcmp.gt(Vu.b,Vv.b) - Qd4=vcmp.eq(Vu.b,Vv.b) - Qx4&=vcmp.eq(Vu.b,Vv.b) - Qx4|=vcmp.eq(Vu.b,Vv.b) - Qx4^=vcmp.eq(Vu.b,Vv.b) - Qd4=vcmp.gt(Vu.uw,Vv.uw) - Qx4&=vcmp.gt(Vu.uw,Vv.uw) - Qx4|=vcmp.gt(Vu.uw,Vv.uw) - Qx4^=vcmp.gt(Vu.uw,Vv.uw) - Qd4=vcmp.gt(Vu.uh,Vv.uh) - Qx4&=vcmp.gt(Vu.uh,Vv.uh) - Qx4|=vcmp.gt(Vu.uh,Vv.uh) - Qx4^=vcmp.gt(Vu.uh,Vv.uh) - Qd4=vcmp.gt(Vu.ub,Vv.ub) - Qx4&=vcmp.gt(Vu.ub,Vv.ub) - Qx4|=vcmp.gt(Vu.ub,Vv.ub) - Qx4^=vcmp.gt(Vu.ub,Vv.ub) - Qd4=vcmp.eq(Vu.uw,Vv.uw) - Qx4&=vcmp.eq(Vu.uw,Vv.uw) - Qx4|=vcmp.eq(Vu.uw,Vv.uw) - Qx4^=vcmp.eq(Vu.uw,Vv.uw) - Qd4=vcmp.eq(Vu.uh,Vv.uh) - Qx4&=vcmp.eq(Vu.uh,Vv.uh) - Qx4|=vcmp.eq(Vu.uh,Vv.uh) - Qx4^=vcmp.eq(Vu.uh,Vv.uh) - Qd4=vcmp.eq(Vu.ub,Vv.ub) - Qx4&=vcmp.eq(Vu.ub,Vv.ub) - Qx4|=vcmp.eq(Vu.ub,Vv.ub) - Qx4^=vcmp.eq(Vu.ub,Vv.ub) - Qx4&=vcmp.eq(Vu.sf,Vv.sf) - Qx4^=vcmp.eq(Vu.sf,Vv.sf) - Qx4|=vcmp.eq(Vu.sf,Vv.sf) - Qd4=vcmp.eq(Vu.sf,Vv.sf) - Qx4&=vcmp.eq(Vu.hf,Vv.hf) - Qx4^=vcmp.eq(Vu.hf,Vv.hf) - Qx4|=vcmp.eq(Vu.hf,Vv.hf) - Qd4=vcmp.eq(Vu.hf,Vv.hf) - Qx4&=vcmp.gt(Vu.sf,Vv.sf) - Qx4^=vcmp.gt(Vu.sf,Vv.sf) - Qx4|=vcmp.gt(Vu.sf,Vv.sf) - Qd4=vcmp.gt(Vu.sf,Vv.sf) - Qx4&=vcmp.gt(Vu.hf,Vv.hf) - Qx4^=vcmp.gt(Vu.hf,Vv.hf) - Qx4|=vcmp.gt(Vu.hf,Vv.hf) - Qd4=vcmp.gt(Vu.hf,Vv.hf) - Qx4&=vcmp.gt(Vu.bf,Vv.bf) - Qx4^=vcmp.gt(Vu.bf,Vv.bf) - Qx4|=vcmp.gt(Vu.bf,Vv.bf) - Qd4=vcmp.gt(Vu.bf,Vv.bf) ## [Conditional accumulate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-conditional-accumulate) - if (Qv4) Vx.b+=Vu.b - if (Qv4) Vx.b-=Vu.b - if (!Qv4) Vx.b+=Vu.b - if (!Qv4) Vx.b-=Vu.b - if (Qv4) Vx.h+=Vu.h - if (Qv4) Vx.h-=Vu.h - if (!Qv4) Vx.h+=Vu.h - if (!Qv4) Vx.h-=Vu.h - if (Qv4) Vx.w+=Vu.w - if (Qv4) Vx.w-=Vu.w - if (!Qv4) Vx.w+=Vu.w - if (!Qv4) Vx.w-=Vu.w ## [Mux select](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-mux-select) - Vd=vmux(Qt4,Vu,Vv) ## [Saturation](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-saturation) - Vd.w=vsatdw(Vu.w,Vv.w) - Vd.ub=vsat(Vu.h,Vv.h) - Vd.h=vsat(Vu.w,Vv.w) - Vd.uh=vsat(Vu.uw,Vv.uw) ## [In-lane shuffle](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-in-lane-shuffle) - Vd.b=vshuffe(Vu.b,Vv.b) - Vd.b=vshuffo(Vu.b,Vv.b) - Vd.h=vshuffe(Vu.h,Vv.h) - Vd.h=vshuffo(Vu.h,Vv.h) ## [Clear vector register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-clear-vector-register) - Vd=#0 - Vdd=#0 ## [Extract vector element](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-extract-vector-element) - Rd=vextract(Vu,Rs) - Rd.w=vextract(Vu,Rs) ## [Vector gather](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-vector-gather) - vtmp.h=vgather(Rt,Mu,Vvv.w).h - if (Qs4) vtmp.h=vgather(Rt,Mu,Vvv.w).h ## [Vector gather](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-vector-gather) - vtmp.w=vgather(Rt,Mu,Vv.w).w - vtmp.h=vgather(Rt,Mu,Vv.h).h - if (Qs4) vtmp.w=vgather(Rt,Mu,Vv.w).w - if (Qs4) vtmp.h=vgather(Rt,Mu,Vv.h).h ## [Load - aligned](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-load-aligned) - Vd=vmem(Rx++#s3) - Vd=vmem(Rt+#s4) - Vd=vmem(Rx++Mu) - if (Pv) Vd=vmem(Rx++#s3) - if (Pv) Vd=vmem(Rt+#s4) - if (Pv) Vd=vmem(Rx++Mu) - if (!Pv) Vd=vmem(Rx++#s3) - if (!Pv) Vd=vmem(Rt+#s4) - if (!Pv) Vd=vmem(Rx++Mu) - Vd=vmem(Rt) - if (Pv) Vd=vmem(Rt) - if (!Pv) Vd=vmem(Rt) - Vd=vmem(Rx++#s3):nt - Vd=vmem(Rt+#s4):nt - Vd=vmem(Rx++Mu):nt - if (Pv) Vd=vmem(Rx++#s3):nt - if (Pv) Vd=vmem(Rt+#s4):nt - if (Pv) Vd=vmem(Rx++Mu):nt - if (!Pv) Vd=vmem(Rx++#s3):nt - if (!Pv) Vd=vmem(Rt+#s4):nt - if (!Pv) Vd=vmem(Rx++Mu):nt - Vd=vmem(Rt):nt - if (Pv) Vd=vmem(Rt):nt - if (!Pv) Vd=vmem(Rt):nt ## [Load - immediate use](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-load-immediate-use) - Vd.cur=vmem(Rx++#s3) - Vd.cur=vmem(Rt+#s4) - Vd.cur=vmem(Rx++Mu) - if (Pv) Vd.cur=vmem(Rx++#s3) - if (Pv) Vd.cur=vmem(Rt+#s4) - if (Pv) Vd.cur=vmem(Rx++Mu) - if (!Pv) Vd.cur=vmem(Rx++#s3) - if (!Pv) Vd.cur=vmem(Rt+#s4) - if (!Pv) Vd.cur=vmem(Rx++Mu) - if (Pv) Vd.cur=vmem(Rt) - if (!Pv) Vd.cur=vmem(Rt) - Vd.cur=vmem(Rx++#s3):nt - Vd.cur=vmem(Rt+#s4):nt - Vd.cur=vmem(Rx++Mu):nt - if (Pv) Vd.cur=vmem(Rx++#s3):nt - if (Pv) Vd.cur=vmem(Rt+#s4):nt - if (Pv) Vd.cur=vmem(Rx++Mu):nt - if (!Pv) Vd.cur=vmem(Rx++#s3):nt - if (!Pv) Vd.cur=vmem(Rt+#s4):nt - if (!Pv) Vd.cur=vmem(Rx++Mu):nt - if (Pv) Vd.cur=vmem(Rt):nt - if (!Pv) Vd.cur=vmem(Rt):nt ## [Load - temporary immediate use](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-load-temporary-immediate-use) - Vd.tmp=vmem(Rx++#s3) - Vd.tmp=vmem(Rt+#s4) - Vd.tmp=vmem(Rx++Mu) - if (Pv) Vd.tmp=vmem(Rx++#s3) - if (Pv) Vd.tmp=vmem(Rt+#s4) - if (Pv) Vd.tmp=vmem(Rx++Mu) - if (!Pv) Vd.tmp=vmem(Rx++#s3) - if (!Pv) Vd.tmp=vmem(Rt+#s4) - if (!Pv) Vd.tmp=vmem(Rx++Mu) - if (Pv) Vd.tmp=vmem(Rt) - if (!Pv) Vd.tmp=vmem(Rt) - Vd.tmp=vmem(Rx++#s3):nt - Vd.tmp=vmem(Rt+#s4):nt - Vd.tmp=vmem(Rx++Mu):nt - if (Pv) Vd.tmp=vmem(Rx++#s3):nt - if (Pv) Vd.tmp=vmem(Rt+#s4):nt - if (Pv) Vd.tmp=vmem(Rx++Mu):nt - if (!Pv) Vd.tmp=vmem(Rx++#s3):nt - if (!Pv) Vd.tmp=vmem(Rt+#s4):nt - if (!Pv) Vd.tmp=vmem(Rx++Mu):nt - if (Pv) Vd.tmp=vmem(Rt):nt - if (!Pv) Vd.tmp=vmem(Rt):nt ## [Load - unaligned](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-load-unaligned) - Vd=vmemu(Rx++#s3) - Vd=vmemu(Rt+#s4) - Vd=vmemu(Rx++Mu) - Vd=vmemu(Rt) ## [3x3 Multiply for 2x2 Tile](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-3x3-multiply-for-2x2-tile) - Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):v - Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):h - Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):v - Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):h ## [Arithmetic widening](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-arithmetic-widening) - Vdd.h=vadd(Vu.ub,Vv.ub) - Vdd.h=vsub(Vu.ub,Vv.ub) - Vdd.w=vadd(Vu.h,Vv.h) - Vdd.w=vsub(Vu.h,Vv.h) - Vdd.w=vadd(Vu.uh,Vv.uh) - Vdd.w=vsub(Vu.uh,Vv.uh) - Vxx.w+=vadd(Vu.h,Vv.h) - Vxx.w+=vadd(Vu.uh,Vv.uh) - Vxx.h+=vadd(Vu.ub,Vv.ub) ## [Multiply with 2-wide reduction](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-with-2-wide-reduction) - Vdd.h=vdmpy(Vuu.ub, Rt.b) - Vxx.h+=vdmpy(Vuu.ub, Rt.b) - Vdd.w=vdmpy(Vuu.h,Rt.b) - Vxx.w+=vdmpy(Vuu.h,Rt.b) - Vx.w+=vdmpy(Vu.h,Vv.h):sat - Vd.w=vdmpy(Vuu.h,Rt.h):sat - Vx.w+=vdmpy(Vuu.h,Rt.h):sat - Vd.w=vdmpy(Vuu.h,Rt.uh,#1):sat - Vx.w+=vdmpy(Vuu.h,Rt.uh,#1):sat ## [Lookup table for piecewise from 64-bit scalar](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-lookup-table-for-piecewise-from-64-bit-scalar) - Vd.h=vlut4(Vu.uh,Rtt.h) ## [Multiply with piecewise add/sub](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-with-piecewise-add-sub) - Vx.h=vmpa(Vx.h,Vu.h,Rtt.h):sat - Vx.h=vmpa(Vx.h,Vu.uh,Rtt.uh):sat - Vx.h=vmps(Vx.h,Vu.uh,Rtt.uh):sat - Vx.uh=vmpa(Vx.uh,Vu.uh,Rtt.uh) - Vx.h=vmpa(Vx.h,Vu.uh,Rtt.uh) - Vx.h=vmps(Vx.h,Vu.uh,Rtt.uh) ## [Multiply-add double resource](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-add-double-resource) - Vdd.h=vmpa(Vuu.ub,Vvv.b) - Vdd.h=vmpa(Vuu.ub,Vvv.ub) - Vdd.h=vmpa(Vuu.ub,Rt.b) - Vxx.h+=vmpa(Vuu.ub,Rt.b) - Vdd.h=vmpa(Vuu.ub,Rt.ub) - Vxx.h+=vmpa(Vuu.ub,Rt.ub) - Vdd.w=vmpa(Vuu.h,Rt.b) - Vxx.w+=vmpa(Vuu.h,Rt.b) - Vdd.w=vmpa(Vuu.uh,Rt.b) - Vxx.w+=vmpa(Vuu.uh,Rt.b) - Vxx.w=vmpa(Vxx.h,Vu.uh,Rt.w) - Vxx.uw=vmpa(Vxx.uh,Vu.uh,Rt.w) ## [Multiply double resource vector by scalar](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-double-resource-vector-by-scalar) - Vdd.w=vmpy(Vu.h,Rt.uh) - Vxx.w+=vmpy(Vu.h,Rt.uh) - Vdd.uh=vmpy(Vu.ub,Rt.ub) - Vxx.uh+=vmpy(Vu.ub,Rt.ub) - Vdd.h=vmpy(Vu.ub,Rt.b) - Vxx.h+=vmpy(Vu.ub,Rt.b) - Vdd.w=vmpy(Vu.h,Rt.h) - Vxx.w+=vmpy(Vu.h,Rt.h) - Vxx.w+=vmpy(Vu.h,Rt.h):sat - Vdd.uw=vmpy(Vu.uh,Rt.uh) - Vxx.uw+=vmpy(Vu.uh,Rt.uh) ## [Multiply double resource vector by vector](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-double-resource-vector-by-vector) - Vdd.h=vmpy(Vu.b,Vv.b) - Vxx.h+=vmpy(Vu.b,Vv.b) - Vdd.uh=vmpy(Vu.ub,Vv.ub) - Vxx.uh+=vmpy(Vu.ub,Vv.ub) - Vdd.h=vmpy(Vu.ub,Vv.b) - Vxx.h+=vmpy(Vu.ub,Vv.b) - Vdd.w=vmpy(Vu.h,Vv.h) - Vxx.w+=vmpy(Vu.h,Vv.h) - Vdd.uw=vmpy(Vu.uh,Vv.uh) - Vxx.uw+=vmpy(Vu.uh,Vv.uh) - Vdd.w=vmpy(Vu.h,Vv.uh) - Vxx.w+=vmpy(Vu.h,Vv.uh) ## [Integer multiply - vector by vector](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-integer-multiply-vector-by-vector) - Vd.h=vmpyi(Vu.h,Vv.h) - Vx.h+=vmpyi(Vu.h,Vv.h) ## [Integer Multiply (32x16)](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-integer-multiply-32x16) - Vd.w=vmpyie(Vu.w,Vv.uh) - Vd.w=vmpyio(Vu.w,Vv.h) - Vx.w+=vmpyie(Vu.w,Vv.h) - Vx.w+=vmpyie(Vu.w,Vv.uh) ## [Integer multiply accumulate even/odd](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-integer-multiply-accumulate-even-odd) - Vd.w=vmpyi(Vu.w,Rt.h) - Vx.w+=vmpyi(Vu.w,Rt.h) ## [HVX floating point multiply - half-precision](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-hvx-floating-point-multiply-half-precision) - Vd.qf16=vmpy(Vu.qf16,Vv.qf16) - Vd.qf16=vmpy(Vu.hf,Vv.hf) - Vd.qf16=vmpy(Vu.qf16,Vv.hf) - Vd.qf16=vmpy(Vu.qf16,Rt.hf) - Vd.qf16=vmpy(Vu.hf,Rt.hf) ## [HVX floating point multiply - single-precision](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-hvx-floating-point-multiply-single-precision) - Vd.qf32=vmpy(Vu.qf32,Vv.qf32) - Vd.qf32=vmpy(Vu.sf,Vv.sf) - Vd.qf32=vmpy(Vu.sf,Rt.sf) ## [Multiply (32x16)](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-32x16) - Vd.w=vmpye(Vu.w,Vv.uh) - Vd.w=vmpyo(Vu.w,Vv.h):<<1:sat - Vd.w=vmpyo(Vu.w,Vv.h):<<1:rnd:sat - Vd.w=vmpyo(Vu.w,Vv.uh) - Vx.w+=vmpyo(Vu.w,Vv.uh) - Vd.w=vmpye(Vu.w,Vv.uh):rnd - Vd.w=vmpyo(Vu.w,Vv.uh):rnd - Vx.w+=vmpyo(Vu.w,Vv.uh):rnd - Vdd=vmpye(Vu.w,Vv.uh) - Vxx+=vmpyo(Vu.w,Vv.h) - Vx.w+=vmpyo(Vu.w,Vv.h):<<1:sat:shift - Vx.w+=vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift ## [Multiply bytes with 4-wide reduction - vector by scalar](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-bytes-with-4-wide-reduction-vector-by-scalar) - Vdd.uw=vrmpy(Vuu.ub,Rt.ub,#u1) - Vxx.uw+=vrmpy(Vuu.ub,Rt.ub,#u1) - Vdd.w=vrmpy(Vuu.ub,Rt.b,#u1) - Vxx.w+=vrmpy(Vuu.ub,Rt.b,#u1) ## [Multiply by byte with accumulate and 4-wide reduction - vector by vector](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-by-byte-with-accumulate-and-4-wide-reduction-vector-by-vector) - Vx.uw+=vrmpy(Vu.ub,Vv.ub) - Vx.w+=vrmpy(Vu.b,Vv.b) - Vx.w+=vrmpy(Vu.ub,Vv.b) ## [Multiply with 3-wide reduction](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-with-3-wide-reduction) - Vdd.h=vtmpy(Vuu.b,Rt.b) - Vxx.h+=vtmpy(Vuu.b,Rt.b) - Vdd.h=vtmpy(Vuu.ub,Rt.b) - Vxx.h+=vtmpy(Vuu.ub,Rt.b) - Vdd.w=vtmpy(Vuu.h,Rt.b) - Vxx.w+=vtmpy(Vuu.h,Rt.b) ## [HVX floating point multiply - widening](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-hvx-floating-point-multiply-widening) - Vdd.qf32=vmpy(Vu.qf16,Vv.qf16) - Vdd.qf32=vmpy(Vu.hf,Vv.hf) - Vdd.qf32=vmpy(Vu.qf16,Vv.hf) ## [Sum of reduction of absolute differences halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-sum-of-reduction-of-absolute-differences-halfwords) - Vdd.uw=vdsad(Vuu.uh,Rt.uh) - Vxx.uw+=vdsad(Vuu.uh,Rt.uh) ## [Sum of absolute differences byte](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-sum-of-absolute-differences-byte) - Vdd.uw=vrsad(Vuu.ub,Rt.ub,#u1) - Vxx.uw+=vrsad(Vuu.ub,Rt.ub,#u1) ## [Multiply with 2-wide reduction](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-with-2-wide-reduction) - Vd.w=vdmpy(Vu.h,Vv.h):sat - Vd.w=vdmpy(Vu.h,Rt.h):sat - Vx.w+=vdmpy(Vu.h,Rt.h):sat - Vd.w=vdmpy(Vu.h,Rt.uh):sat - Vx.w+=vdmpy(Vu.h,Rt.uh):sat ## [Multiply by byte with 2-wide reduction](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-by-byte-with-2-wide-reduction) - Vd.h=vdmpy(Vu.ub, Rt.b) - Vx.h+=vdmpy(Vu.ub, Rt.b) - Vd.w=vdmpy(Vu.h,Rt.b) - Vx.w+=vdmpy(Vu.h,Rt.b) ## [Read and set extended bits of vector](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-read-and-set-extended-bits-of-vector) - Vx|=vgetqfext(Vu.x,Rt) - Vd=vgetqfext(Vu.x,Rt) - Vd.x=vsetqfext(Vu,Rt) ## [Multiply vector by scalar](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-vector-by-scalar) - Vd.h=vmpy(Vu.h,Rt.h):<<1:sat - Vd.h=vmpy(Vu.h,Rt.h):<<1:rnd:sat - Vd.uh=vmpy(Vu.uh,Rt.uh) - Vd.uh=vmpy(Vu.uh,Rt.uh):rnd - Vd.h=vmpy(Vu.h,Rt.uh) - Vd.h=vmpy(Vu.h,Rt.uh):rnd ## [Multiply vector by vector](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-vector-by-vector) - Vd.h=vmpy(Vu.h,Vv.h):<<1:rnd:sat - Vd.uh=vmpy(Vu.uh,Vv.uh):>>16 - Vd.uh=vmpy(Vu.uh,Vv.uh):rnd - Vd.h=vmpy(Vu.h,Vv.uh) - Vd.h=vmpy(Vu.h,Vv.uh):rnd - Vd.uh=vmpy(Vu.uh,Vv.uh) ## [Multiply half of the elements (16x16)](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-half-of-the-elements-16x16) - Vd.w=vmpyieo(Vu.h,Vv.h) ## [Integer multiply by byte](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-integer-multiply-by-byte) - Vd.h=vmpyi(Vu.h,Rt.b) - Vx.h+=vmpyi(Vu.h,Rt.b) - Vd.w=vmpyi(Vu.w,Rt.b) - Vx.w+=vmpyi(Vu.w,Rt.b) - Vd.w=vmpyi(Vu.w,Rt.ub) - Vx.w+=vmpyi(Vu.w,Rt.ub) ## [Multiply half of the elements with scalar (16 x 16)](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-half-of-the-elements-with-scalar-16-x-16) - Vd.uw=vmpye(Vu.uh,Rt.uh) - Vx.uw+=vmpye(Vu.uh,Rt.uh) ## [Multiply bytes with 4-wide reduction - vector by scalar](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-bytes-with-4-wide-reduction-vector-by-scalar) - Vd.uw=vrmpy(Vu.ub,Rt.ub) - Vx.uw+=vrmpy(Vu.ub,Rt.ub) - Vd.w=vrmpy(Vu.ub,Rt.b) - Vx.w+=vrmpy(Vu.ub,Rt.b) ## [Multiply by byte with 4-wide reduction - vector by vector](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-multiply-by-byte-with-4-wide-reduction-vector-by-vector) - Vd.uw=vrmpy(Vu.ub,Vv.ub) - Vd.w=vrmpy(Vu.b,Vv.b) - Vd.w=vrmpy(Vu.ub,Vv.b) ## [Splat from scalar](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-splat-from-scalar) - Vd=vsplat(Rt) - Vd.h=vsplat(Rt) - Vd.b=vsplat(Rt) ## [Vector to predicate transfer](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-vector-to-predicate-transfer) - Qd4=vand(Vu,Rt) - Qx4|=vand(Vu,Rt) ## [Predicate to vector transfer](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-predicate-to-vector-transfer) - Vd=vand(Qu4,Rt) - Vx|=vand(Qu4,Rt) - Vd=vand(!Qu4,Rt) - Vx|=vand(!Qu4,Rt) ## [Absolute value of difference](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-absolute-value-of-difference) - Vd.ub=vabsdiff(Vu.ub,Vv.ub) - Vd.uh=vabsdiff(Vu.uh,Vv.uh) - Vd.uh=vabsdiff(Vu.h,Vv.h) - Vd.uw=vabsdiff(Vu.w,Vv.w) - Vd.uw=vabsdiff(Vu.uw,Vv.uw) ## [Insert element](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-insert-element) - Vx.w=vinsert(Rt) ## [Byte alignment](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-byte-alignment) - Vd=valign(Vu,Vv,Rt) - Vd=vlalign(Vu,Vv,Rt) - Vd=valign(Vu,Vv,#u3) - Vd=vlalign(Vu,Vv,#u3) - Vd=valign4(Vu,Vv,Rt) - Vd=vror(Vu,Rt) ## [General permute network](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-general-permute-network) - Vd=vdelta(Vu,Vv) - Vd=vrdelta(Vu,Vv) ## [Shuffle - Deal](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-shuffle-deal) - Vd.h=vdeal(Vu.h) - Vd.b=vdeal(Vu.b) - Vd.b=vdeale(Vu.b,Vv.b) - Vd.h=vshuff(Vu.h) - Vd.b=vshuff(Vu.b) ## [Pack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-pack) - Vd.b=vpacke(Vu.h,Vv.h) - Vd.h=vpacke(Vu.w,Vv.w) - Vd.b=vpacko(Vu.h,Vv.h) - Vd.h=vpacko(Vu.w,Vv.w) - Vd.ub=vpack(Vu.h,Vv.h):sat - Vd.b=vpack(Vu.h,Vv.h):sat - Vd.uh=vpack(Vu.w,Vv.w):sat - Vd.h=vpack(Vu.w,Vv.w):sat ## [Set predicate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-set-predicate) - Qd4=vsetq(Rt) - Qd4=vsetq2(Rt) ## [Vector in-lane lookup table](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-vector-in-lane-lookup-table) - Vd.b=vlut32(Vu.b,Vv.b,Rt) - Vd.b=vlut32(Vu.b,Vv.b,#u3) - Vd.b=vlut32(Vu.b,Vv.b,Rt):nomatch ## [Vector ASR overlay](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-vector-asr-overlay) - Vxx.w=vasrinto(Vu.w,Vv.w) ## [Vector shuffle and deal cross-lane](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-vector-shuffle-and-deal-cross-lane) - vtrans2x2(Vy,Vx,Rt) - vshuff(Vy,Vx,Rt) - Vdd=vshuff(Vu,Vv,Rt) - vdeal(Vy,Vx,Rt) - Vdd=vdeal(Vu,Vv,Rt) ## [Vector in-lane lookup table](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-vector-in-lane-lookup-table) - Vx.b|=vlut32(Vu.b,Vv.b,Rt) - Vdd.h=vlut16(Vu.b,Vv.h,Rt) - Vxx.h|=vlut16(Vu.b,Vv.h,Rt) - Vx.b|=vlut32(Vu.b,Vv.b,#u3) - Vdd.h=vlut16(Vu.b,Vv.h,#u3) - Vxx.h|=vlut16(Vu.b,Vv.h,#u3) - Vdd.h=vlut16(Vu.b,Vv.h,Rt):nomatch ## [Unpack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-unpack) - Vdd.uh=vunpack(Vu.ub) - Vdd.h=vunpack(Vu.b) - Vdd.uw=vunpack(Vu.uh) - Vdd.w=vunpack(Vu.h) - Vxx.h|=vunpacko(Vu.b) - Vxx.w|=vunpacko(Vu.h) ## [Vector scatter](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-vector-scatter) - vscatter(Rt,Mu,Vvv.w).h=Vw32 - if (Qs4) vscatter(Rt,Mu,Vvv.w).h=Vw32 - vscatter(Rt,Mu,Vvv.w).h+=Vw32 - vscatter(Rt,Mu,Vvv.w)=Vw32.h - vscatter(Rt,Mu,Vvv.w)+=Vw32.h - if (Qs4) vscatter(Rt,Mu,Vvv.w)=Vw32.h ## [Vector scatter](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-vector-scatter) - vscatter(Rt,Mu,Vv.w).w=Vw32 - vscatter(Rt,Mu,Vv.h).h=Vw32 - vscatter(Rt,Mu,Vv.w).w+=Vw32 - vscatter(Rt,Mu,Vv.h).h+=Vw32 - if (Qs4) vscatter(Rt,Mu,Vv.w).w=Vw32 - if (Qs4) vscatter(Rt,Mu,Vv.h).h=Vw32 - vscatter(Rt,Mu,Vv.w)=Vw32.w - vscatter(Rt,Mu,Vv.h)=Vw32.h - vscatter(Rt,Mu,Vv.w)+=Vw32.w - vscatter(Rt,Mu,Vv.h)+=Vw32.h - if (Qs4) vscatter(Rt,Mu,Vv.w)=Vw32.w - if (Qs4) vscatter(Rt,Mu,Vv.h)=Vw32.h ## [Narrowing Shift](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-narrowing-shift) - Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat - Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat - Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat - Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat - Vd.h=vasr(Vu.w,Vv.w,Rt) - Vd.h=vasr(Vu.w,Vv.w,Rt):sat - Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat - Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat - Vd.uh=vasr(Vu.w,Vv.w,Rt):sat - Vd.ub=vasr(Vu.h,Vv.h,Rt):sat - Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat - Vd.b=vasr(Vu.h,Vv.h,Rt):sat - Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat ## [Compute contiguous offsets for valid positions](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-compute-contiguous-offsets-for-valid-positions) - Vd.b=prefixsum(Qv4) - Vd.h=prefixsum(Qv4) - Vd.w=prefixsum(Qv4) ## [HVX floating point absolute value](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-hvx-floating-point-absolute-value) - Vd.qf32=vabs(Vu.sf) - Vd.qf32=vabs(Vu.qf32) - Vd.qf16=vabs(Vu.hf) - Vd.qf16=vabs(Vu.qf16) ## [HVX floating point negate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-hvx-floating-point-negate) - Vd.qf32=vneg(Vu.sf) - Vd.qf32=vneg(Vu.qf32) - Vd.qf16=vneg(Vu.hf) - Vd.qf16=vneg(Vu.qf16) ## [HVX floating point add and subtract - half-precision](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-hvx-floating-point-add-and-subtract-half-precision) - Vd.qf16=vadd(Vu.qf16,Vv.qf16) - Vd.qf16=vadd(Vu.hf,Vv.hf) - Vd.qf16=vadd(Vu.qf16,Vv.hf) - Vd.qf16=vsub(Vu.qf16,Vv.qf16) - Vd.qf16=vsub(Vu.hf,Vv.hf) - Vd.qf16=vsub(Vu.qf16,Vv.hf) - Vd.qf16=vsub(Vu.hf,Vv.qf16) ## [HVX floating point add and subtract - single-precision](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-hvx-floating-point-add-and-subtract-single-precision) - Vd.qf32=vadd(Vu.qf32,Vv.qf32) - Vd.qf32=vadd(Vu.sf,Vv.sf) - Vd.qf32=vadd(Vu.qf32,Vv.sf) - Vd.qf32=vsub(Vu.qf32,Vv.qf32) - Vd.qf32=vsub(Vu.sf,Vv.sf) - Vd.qf32=vsub(Vu.qf32,Vv.sf) - Vd.qf32=vsub(Vu.sf,Vv.qf32) ## [Shift and add](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-shift-and-add) - Vx.w+=vasl(Vu.w,Rt) - Vx.w+=vasr(Vu.w,Rt) - Vx.h+=vasl(Vu.h,Rt) - Vx.h+=vasr(Vu.h,Rt) ## [Shift](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-shift) - Vd.w=vasr(Vu.w,Rt) - Vd.w=vasl(Vu.w,Rt) - Vd.uw=vlsr(Vu.uw,Rt) - Vd.w=vasr(Vu.w,Vv.w) - Vd.w=vasl(Vu.w,Vv.w) - Vd.w=vlsr(Vu.w,Vv.w) - Vd.h=vasr(Vu.h,Rt) - Vd.h=vasl(Vu.h,Rt) - Vd.uh=vlsr(Vu.uh,Rt) - Vd.h=vasr(Vu.h,Vv.h) - Vd.h=vasl(Vu.h,Vv.h) - Vd.h=vlsr(Vu.h,Vv.h) - Vd.ub=vlsr(Vu.ub,Rt) ## [Narrowing Shift by Vector](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-narrowing-shift-by-vector) - Vd.uh=vasr(Vuu.w,Vv.uh):sat - Vd.uh=vasr(Vuu.w,Vv.uh):rnd:sat - Vd.ub=vasr(Vuu.uh,Vv.ub):sat - Vd.ub=vasr(Vuu.uh,Vv.ub):rnd:sat ## [Convert IEEE floating point to integer](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-convert-ieee-floating-point-to-integer) - Vd.w=Vu.sf - Vd.h=Vu.hf - Vd.h=Vu.hf:rnd ## [Convert HVX floating point to IEEE floating-point](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-convert-hvx-floating-point-to-ieee-floating-point) - Vd.sf=Vu.qf32 - Vd.hf=Vu.qf16 - Vd.hf=Vuu.qf32 - Vd.bf=Vuu.qf32 - Vd.f8=Vu.qf16 ## [Convert integer to IEEE floating point](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-convert-integer-to-ieee-floating-point) - Vd.sf=Vu.w - Vd.hf=Vu.h ## [Convert to HVX floating point](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-convert-to-hvx-floating-point) - Vd.qf32=Vu.sf - Vd.qf32=Vu.qf32 - Vd.qf16=Vu.hf - Vd.qf16=Vu.qf16 ## [Convert to double HVX floating point](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-convert-to-double-hvx-floating-point) - Vdd.qf16=Vu.f8 ## [Extract exponent](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-extract-exponent) - Vd.w=vilog2(Vu.qf32) - Vd.w=vilog2(Vu.qf16) - Vd.w=vilog2(Vu.sf) - Vd.w=vilog2(Vu.hf) ## [Merge vector with extended bits](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-merge-vector-with-extended-bits) - Vd=vmerge(Vu.x,Vv.w) ## [Round to next smaller element size](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-round-to-next-smaller-element-size) - Vd.h=vround(Vu.w,Vv.w):sat - Vd.uh=vround(Vu.w,Vv.w):sat - Vd.uh=vround(Vu.uw,Vv.uw):sat - Vd.b=vround(Vu.h,Vv.h):sat - Vd.ub=vround(Vu.h,Vv.h):sat - Vd.ub=vround(Vu.uh,Vv.uh):sat ## [Vector rotate right word](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-vector-rotate-right-word) - Vd.uw=vrotr(Vu.uw,Vv.uw) ## [Bit counting](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-bit-counting) - Vd.uw=vcl0(Vu.uw) - Vd.uh=vcl0(Vu.uh) - Vd.w=vnormamt(Vu.w) - Vd.h=vnormamt(Vu.h) - Vd.w=vadd(vclb(Vu.w),Vv.w) - Vd.h=vadd(vclb(Vu.h),Vv.h) - Vd.h=vpopcount(Vu.h) ## [Store - byte-enabled aligned](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-store-byte-enabled-aligned) - if (Qv4) vmem(Rx++#s3)=Vs - if (Qv4) vmem(Rt+#s4)=Vs - if (Qv4) vmem(Rx++Mu)=Vs - if (!Qv4) vmem(Rx++#s3)=Vs - if (!Qv4) vmem(Rt+#s4)=Vs - if (!Qv4) vmem(Rx++Mu)=Vs - if (Qv4) vmem(Rt)=Vs - if (!Qv4) vmem(Rt)=Vs - if (Qv4) vmem(Rx++#s3):nt=Vs - if (Qv4) vmem(Rt+#s4):nt=Vs - if (Qv4) vmem(Rx++Mu):nt=Vs - if (!Qv4) vmem(Rx++#s3):nt=Vs - if (!Qv4) vmem(Rt+#s4):nt=Vs - if (!Qv4) vmem(Rx++Mu):nt=Vs - if (Qv4) vmem(Rt):nt=Vs - if (!Qv4) vmem(Rt):nt=Vs ## [Store - new](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-store-new) - vmem(Rx++#s3)=Os8.new - vmem(Rt+#s4)=Os8.new - vmem(Rx++Mu)=Os8.new - if (Pv) vmem(Rx++#s3)=Os8.new - if (Pv) vmem(Rt+#s4)=Os8.new - if (Pv) vmem(Rx++Mu)=Os8.new - if (!Pv) vmem(Rx++#s3)=Os8.new - if (!Pv) vmem(Rt+#s4)=Os8.new - if (!Pv) vmem(Rx++Mu)=Os8.new - vmem(Rt)=Os8.new - vmem(Rx++#s3):nt=Os8.new - vmem(Rt+#s4):nt=Os8.new - vmem(Rx++Mu):nt=Os8.new - if (Pv) vmem(Rx++#s3):nt=Os8.new - if (Pv) vmem(Rt+#s4):nt=Os8.new - if (Pv) vmem(Rx++Mu):nt=Os8.new - if (!Pv) vmem(Rx++#s3):nt=Os8.new - if (!Pv) vmem(Rt+#s4):nt=Os8.new - if (!Pv) vmem(Rx++Mu):nt=Os8.new - vmem(Rt):nt=Os8.new ## [Store - aligned](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-store-aligned) - vmem(Rx++#s3)=Vs - vmem(Rt+#s4)=Vs - vmem(Rx++Mu)=Vs - if (Pv) vmem(Rx++#s3)=Vs - if (Pv) vmem(Rt+#s4)=Vs - if (Pv) vmem(Rx++Mu)=Vs - if (!Pv) vmem(Rx++#s3)=Vs - if (!Pv) vmem(Rt+#s4)=Vs - if (!Pv) vmem(Rx++Mu)=Vs - vmem(Rt)=Vs - if (Pv) vmem(Rt)=Vs - if (!Pv) vmem(Rt)=Vs - vmem(Rx++#s3):nt=Vs - vmem(Rt+#s4):nt=Vs - vmem(Rx++Mu):nt=Vs - if (Pv) vmem(Rx++#s3):nt=Vs - if (Pv) vmem(Rt+#s4):nt=Vs - if (Pv) vmem(Rx++Mu):nt=Vs - if (!Pv) vmem(Rx++#s3):nt=Vs - if (!Pv) vmem(Rt+#s4):nt=Vs - if (!Pv) vmem(Rx++Mu):nt=Vs - vmem(Rt):nt=Vs - if (Pv) vmem(Rt):nt=Vs - if (!Pv) vmem(Rt):nt=Vs ## [Store - unaligned](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.html#v85-hvx-store-unaligned) - if (Pv) vmemu(Rt)=Vs - if (!Pv) vmemu(Rt)=Vs - vmemu(Rx++#s3)=Vs - vmemu(Rt+#s4)=Vs - vmemu(Rx++Mu)=Vs - if (Pv) vmemu(Rx++#s3)=Vs - if (Pv) vmemu(Rt+#s4)=Vs - if (Pv) vmemu(Rx++Mu)=Vs - if (!Pv) vmemu(Rx++#s3)=Vs - if (!Pv) vmemu(Rt+#s4)=Vs - if (!Pv) vmemu(Rx++Mu)=Vs - vmemu(Rt)=Vs Last Published: Oct 06, 2026 [Previous Topic HVX PMU events](https://docs.qualcomm.com/bundle/publicresource/80-N3040-23/topics/80-n2040-72_v85_hvx_prm_src_hvx-pmu-events.md) [Next Topic HVX instruction set](https://docs.qualcomm.com/bundle/publicresource/80-N3040-23/topics/80-n2040-72_v85_hvx_prm_src_hvx-instruction-set.md)