# Build procedure The build procedure for standalone Hexagon processor applications is identical to the build procedure for standard Linux applications. The procedure supports user configuration of the following runtime system properties: - Stack and heap - Memory management - Caches - ISDB - TCM This document does not describe the following runtime environment properties for standalone applications: - Default IMASK and other register values - Permissions for non-fixed TLB entries (such as rwx for each 1 MB segment) Note These properties are currently not user-configurable and are subject to change in future tools releases. ## Runtime system configuration The runtime system for standalone Hexagon processor applications is configurable to support various hardware and software configurations. The program start address is set with the linker option, `--section-start`. For example: hexagon-clang -Xlinker --section-start -Xlinker .start=address hello.c Copy to clipboard The `-Xlinker` compiler option is used to specify that the following argument is passed to the linker as a command option. ## L1 and L2 cache attributes Set L1 and L2 cache attributes at runtime by calling the library function, `add_translation()` (See Section 3.2.1). ## Parameters The runtime system is configured primarily by passing various parameters to the linker on the compiler command line. In the following example, three parameters (`STACK_SIZE`, `HEAP_SIZE`, and `STACK_START`) are passed to specify the application stack and heap: hexagon-clang -Wl,--defsym,STACK_SIZE=0x10000 -Wl,--defsym, HEAP_SIZE=0x10000 -Wl,--defsym, STACK_START=global_end+HEAP_SIZE+STACK_SIZE hello.c Copy to clipboard The `-Wl` compiler option specifies that the following two arguments are passed to the linker as a single option. For example, the first `-Wl` option in the example above specifies the following linker option: --defsym STACK_SIZE=0x10000 Copy to clipboard `-Xlinker` can also be used to pass parameters to the linker. However, in this case it is less efficient than `-Wl` because it can pass only one symbol at a time. If you are linking an application directly (for example, by using the hexagon-link command), these parameters can be set directly using the `--defsym` linker option. The following table lists the parameters defined for configuring the runtime system. - The default parameter values are consistent with developing a standalone application that runs on the Hexagon processor simulator. - The mode-controlling parameters use nonstandard values. Specifically, the value 1 indicates that a mode or feature is disabled (rather than enabled). | Parameter | Description | Category | | --- | --- | --- | | `STACK_START` | Base address of the program stack.


Default = (end of heap) + (stack size) | Application | | `STACK_SIZE` | Maximum stack size.


Default = 1 MB | Application | | `HEAP_START` | Base address of the program heap.


Default = End of the global data area | Application | | `HEAP_SIZE` | Heap size.


Default = 64 MB | Application | | `PRE_INIT` | Address of the function that is called before any initialization is performed (if defined). | Application | | `POST_EXIT` | Address of the function that is called after the program finishes executing, with no simulator or RTOS present (if defined). | Application | | `ANGEL_SUPPORT` | Specifies whether support for Angel semi-hosting is enabled.


Angel support is valid only if ISDB is secure and in trusted mode (by setting `ISDB_SECURE_FLAG` and `ISDB_TRUSTED_FLAG`). | Application | | `ENABLE_DMT` | Specifies whether dynamic multi-threading is enabled.


Valid only for processor version V5 or greater. | Multi-threading | | `EVENT_VECTOR_BASE` | Event vector table base address (used to set EVB register) | Events | | `I_CACHE_ENABLE` | Specifies whether the instruction cache is enabled.
| Cache | | `I_CACHE_HW_PREFETCH` | Specifies whether hardware instruction cache prefetching is enabled.
| Cache | | `D_CACHE_ENABLE` | Specifies whether the data cache is enabled.
| Cache | | `D_CACHE_HW_PREFETCH` | Specifies whether the hardware data cache is enabled.
| Cache | | `L2_CACHE_SIZE` | Size of the L2 cache.
| Cache | | `L2_PARITY` | >
>
> Specifies whether L2 parity is enabled.

| Cache | | `L2_WB` | Specifies whether L2 write back is enabled.
| Cache | | `TCM_BASE_ADDR` | Base address of the TCM memory. This address is processor dependent.


Valid only if L2/TCM partitioning enabled. | Cache | | `ENABLE_TRANSLATION` | Specifies whether MMU page table translation is enabled.


The MMU handles virtual-to-physical address translation. | TLB | | `TLB_MAP_TABLE_PTR` | Address of table of the default TLB entries. This address is used to load the TLB entry on a TLB miss.


Valid only if default TLB miss handler used. | TLB | | `ISDB_SECURE_FLAG` | Specifies whether ISDB is secure.
| Debugging | | `ISDB_TRUSTED_FLAG` | Specifies whether ISDB is trusted.
| Debugging | | `ISDB_DEBUG_FLAG` | Specifies whether ISDB debugging is enabled.
| Debugging | | `CORE_DUMP_BASE` | Base address of the core dump (if defined; otherwise use the default location). | Debugging | | `ENABLE_PCYCLE` | Specifies whether auto-incrementing of the PCYCLE register is enabled.
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