Halfword absolute value intrinsics
Ld16.uh=abs(Lu16.h)	HLX_Vector Q6_Luh_abs_Lh(HLX_Vector Lu)
Ld16.h=abs(Lu16.h):sat	HLX_Vector Q6_Lh_abs_Lh_sat(HLX_Vector Lu)

# HLX instruction set The instructions are listed alphabetically within instruction categories. The following information is provided for each instruction: - A brief description of the instruction - A high-level functional description with supported syntax and behavior - Instruction class and slot information for grouping instructions in packets - Notes on miscellaneous issues - C intrinsic functions that provide access to the instruction - Instruction encoding ## Instruction symbols [Instruction syntax symbols](https://docs.qualcomm.com/doc/80-N3040-23/topic/hlx-instruction-set.html#v85-tbl-hlx-instruction-syntax-symbols) lists the symbols used to specify instruction syntax. | **Symbol** | **Example** | **Meaning** | | --- | --- | --- | | = | Ld16.uh=abs(Lu16.h) | Assignment of RHS to LHS | | { … } | { Ld16.tmp=mem(Rs); Lx16.h=add(Lu16.h,Lv16.h); } | Group of parallel instructions in a packet | | # | Ld16.h=#s5 | Immediate constant value | | 0x | Rs = #0xd9000005 | Hexadecimal number | | .tmp | Ld16.tmp=mem(Rs) | Temporary load result for use by another instruction in the
same packet | | .new | mem(Rs)=Ku16.new | Store a newly generated HLX register value from the same packet | | :sat | Ld16.h=add(Lu16.h,Lv16.h):sat | Perform optional saturation | | :rnd | Ld16.h=avg(Lu16.h,Lv16.h):rnd | Perform optional rounding | | :mask | Ld16.h=lut4(Lu16.uh,Rtt.h):mask | Apply the instruction-specific mask behavior | | :>>1 | Ldd16.w=lut4(Lu16.uh,Rtt.uh):>>1 | Apply the instruction-specific right shift behavior | | :neg | Ldd16.w=lut4(Lu16.uh,Rtt.uh):>>1:neg | Apply the instruction-specific negation behavior | The generated ISA tables use the register, predicate, modifier, and immediate operand symbols listed below. Instruction operand symbols | **Symbol** | **Example** | **Meaning** | | --- | --- | --- | | Ld16 | Ld16.h=Lu16.h | Destination HLX single register | | Lu16, Lv16 | Ld16.h=add(Lu16.h,Lv16.h) | Source HLX single registers | | Lx16 | Lx16.h=mux(Lx16.h,Lu16.h,Lv16.h) | HLX single accumulator register used as both source and
destination | | Ldd16 | Ldd16.w=add(Lu16.uh,Lv16.uh) | Destination HLX register pair | | Luu16, Lvv16 | Ldd16.w=add(Luu16.w,Lvv16.w) | Source HLX register pairs | | Lxx16 | Lxx16.w+=mpy(Lu16.h,Lv16.h) | HLX register-pair accumulator used as both source and
destination | | Ku16, Kt16 | mem(Rs)=Ku16.new | New-value HLX store source encoded in the store instruction | | Rs | Ld16.tmp=mem(Rs) | Scalar source register used to form a memory address | | Rt | Ld16.h=Rt.h | Scalar source register | | Rtt | Ld16.h=lut4(Lu16.uh,Rtt.h) | Scalar register pair source | | Pv | if (Pv) mem(Rs)=Ku16.new | Scalar predicate source controlling conditional execution | | #sN | Ld16.h=#s5 | Signed N-bit immediate value | | #uN | Ld16.uh=#u5 | Unsigned N-bit immediate value | ## Element suffixes [Element suffixes](https://docs.qualcomm.com/doc/80-N3040-23/topic/hlx-instruction-set.html#v85-tbl-hlx-element-suffixes) lists the suffixes used on HLX register operands. HLX element suffixes | **Suffix** | **Example** | **Meaning** | | --- | --- | --- | | .b | Ld16.b=packhi(Lu16.h,Lv16.h) | Byte elements | | .h | Ld16.h=add(Lu16.h,Lv16.h) | Signed halfword elements | | .uh | Ld16.uh=add(Lu16.uh,Lv16.uh):sat | Unsigned halfword elements | | .w | Ldd16.w=add(Luu16.w,Lvv16.w) | Signed word elements | | .uw | Ldd16.uw=avg(Luu16.uw,Lvv16.uw) | Unsigned word elements | ## Instruction behavior symbols The instruction behavior is specified using a C-like language. [Instruction behavior symbols](https://docs.qualcomm.com/doc/80-N3040-23/topic/hlx-instruction-set.html#v85-tbl-hlx-instruction-behavior-symbols) lists symbols not defined in C that are used in the generated behavior descriptions. Instruction behavior symbols | **Symbol** | **Example** | **Meaning** | | --- | --- | --- | | HLX\_ELEMENTS | for (i = 0; i < HLX\_ELEMENTS; i++) | Number of elements processed by the instruction behavior. In V85, HLX only supports 1024 elements. | | HLX\_MEM\_ALIGN\_MASK | ADDR = EA & HLX\_MEM\_ALIGN\_MASK | Address mask used to align HLX memory accesses | | sat\_N | sat\_16(value) | Saturate a value to a signed N-bit result | | usat\_N | usat\_16(value) | Saturate a value to an unsigned N-bit result | | sxt\_X\_to\_Y | sxt\_16\_to\_32(value) | Sign-extend a value from X bits to Y bits | | zxt\_X\_to\_Y | zxt\_16\_to\_32(value) | Zero-extend a value from X bits to Y bits | | LNUM.new | `*(EA&HLX_MEM_ALIGN_MASK) = LNUM.new` | Newly generated HLX register value selected by the store
instruction encoding | ## Temporary loads and new stores HLX memory instructions operate on VTCM and align accesses to the HLX register length. The generated ISA tables describe the load forms in [Load - tmp](https://docs.qualcomm.com/doc/80-N3040-23/topic/hlx-instruction-set.html#v85-hlx-load-tmp) and the store forms in [Store - new](https://docs.qualcomm.com/doc/80-N3040-23/topic/hlx-instruction-set.html#v85-hlx-store-new). Temporary loads use the `.tmp` suffix. A temporary load makes the loaded value available to another HLX instruction in the same packet without writing the destination register file entry. New stores use the `.new` suffix. A new store writes a value produced by another HLX instruction in the same packet. The store instruction uses the `Ku16` or `Kt16` field to identify the new-value producer. ## HLX instruction set architecture ### ALUCOMMON #### Halfword absolute value Calculates the absolute value of halfword elements. Halfword absolute value instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.uh=abs(Lu16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = abs(LuV.h[i]);
}
Copy to clipboard | | Ld16.h=abs(Lu16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = sat_16(abs(LuV.h[i]));
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)** #### Halfword and word add/subtract - Perform arithmetic add and subtract using a word element and halfword element of two L registers. - Supports unsigned and signed values. Halfword and word add/subtract instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.w=add(Luu16.w,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w + sxt_16_to_32(LvV.h[i]);
}
Copy to clipboard | | Ldd16.w=add(Luu16.w,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w + zxt_16_to_32(LvV.uh[i]);
}
Copy to clipboard | | Ldd16.w=sub(Luu16.w,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w - sxt_16_to_32(LvV.h[i]);
}
Copy to clipboard | | Ldd16.w=sub(Luu16.w,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w - zxt_16_to_32(LvV.uh[i]);
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)**

Intrinsics

Halfword and word add/subtract intrinsics
Ldd16.w=add(Luu16.w,Lv16.h)	HLX_VectorPair Q6_LWw_add_LWwLh(HLX_VectorPair Luu, HLX_Vector Lv)
Ldd16.w=add(Luu16.w,Lv16.uh)	HLX_VectorPair Q6_LWw_add_LWwLuh(HLX_VectorPair Luu, HLX_Vector Lv)
Ldd16.w=sub(Luu16.w,Lv16.h)	HLX_VectorPair Q6_LWw_sub_LWwLh(HLX_VectorPair Luu, HLX_Vector Lv)
Ldd16.w=sub(Luu16.w,Lv16.uh)	HLX_VectorPair Q6_LWw_sub_LWwLuh(HLX_VectorPair Luu, HLX_Vector Lv)

#### Halfword widening add/subtract - Performs arithmetic add and subtract using the halfword elements of two L registers. The resulting value is a word element. - Supports unsigned and signed values. Halfword widening add/subtract instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.w=add(Lu16.uh,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = zxt_16_to_32(LuV.uh[i]) + zxt_16_to_32(LvV.uh[i]);
}
Copy to clipboard | | Ldd16.w=sub(Lu16.uh,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = zxt_16_to_32(LuV.uh[i]) - zxt_16_to_32(LvV.uh[i]);
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)**

Intrinsics

Halfword widening add/subtract intrinsics
Ldd16.w=add(Lu16.uh,Lv16.uh)	HLX_VectorPair Q6_LWw_add_LuhLuh(HLX_Vector Lu, HLX_Vector Lv)
Ldd16.w=sub(Lu16.uh,Lv16.uh)	HLX_VectorPair Q6_LWw_sub_LuhLuh(HLX_Vector Lu, HLX_Vector Lv)

#### Halfword add/subtract Performs arithmetic add and subtract using the halfword elements of two L registers. Supports unsigned and signed values. Optionally saturates. Halfword add/subtract instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.h=add(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = LuV.h[i] + LvV.h[i];
}
Copy to clipboard | | Ld16.h=add(Lu16.h,Lv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = sat_16(LuV.h[i]+LvV.h[i]);
}
Copy to clipboard | | Ld16.uh=add(Lu16.uh,Lv16.uh):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = usat_16(LuV.uh[i]+LvV.uh[i]);
}
Copy to clipboard | | Ld16.uh=add(Lu16.h,Lv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = usat_16(LuV.h[i]+LvV.h[i]);
}
Copy to clipboard | | Ld16.h=sub(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = LuV.h[i] - LvV.h[i];
}
Copy to clipboard | | Ld16.h=sub(Lu16.h,Lv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = sat_16(LuV.h[i]-LvV.h[i]);
}
Copy to clipboard | | Ld16.uh=sub(Lu16.uh,Lv16.uh):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = usat_16(LuV.uh[i]-LvV.uh[i]);
}
Copy to clipboard | | Ld16.uh=sub(Lu16.h,Lv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = usat_16(LuV.h[i]-LvV.h[i]);
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)**

Intrinsics

Halfword add/subtract intrinsics
Ld16.h=add(Lu16.h,Lv16.h)	HLX_Vector Q6_Lh_add_LhLh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.h=add(Lu16.h,Lv16.h):sat	HLX_Vector Q6_Lh_add_LhLh_sat(HLX_Vector Lu, HLX_Vector Lv)
Ld16.uh=add(Lu16.uh,Lv16.uh):sat	HLX_Vector Q6_Luh_add_LuhLuh_sat(HLX_Vector Lu, HLX_Vector Lv)
Ld16.uh=add(Lu16.h,Lv16.h):sat	HLX_Vector Q6_Luh_add_LhLh_sat(HLX_Vector Lu, HLX_Vector Lv)
Ld16.h=sub(Lu16.h,Lv16.h)	HLX_Vector Q6_Lh_sub_LhLh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.h=sub(Lu16.h,Lv16.h):sat	HLX_Vector Q6_Lh_sub_LhLh_sat(HLX_Vector Lu, HLX_Vector Lv)
Ld16.uh=sub(Lu16.uh,Lv16.uh):sat	HLX_Vector Q6_Luh_sub_LuhLuh_sat(HLX_Vector Lu, HLX_Vector Lv)
Ld16.uh=sub(Lu16.h,Lv16.h):sat	HLX_Vector Q6_Luh_sub_LhLh_sat(HLX_Vector Lu, HLX_Vector Lv)

Assign intrinsics
Ld16.h=Lu16.h	HLX_Vector Q6_Lh_equals_Lh(HLX_Vector Lu)
Ldd16.w=Luu16.w	HLX_VectorPair Q6_LWw_equals_LWw(HLX_VectorPair Luu)

#### Assign Copy an L register to a L register. Assign instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.h=Lu16.h | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=LuV.uh[i];
}
Copy to clipboard | | Ldd16.w=Luu16.w | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w=LuuV.l[i].w;
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)** #### Halfword compare - Compares two halfword element registers for halfword greater than (gt). - If the result is true for an element, HLX sets the corresponding destination register element to 0xFFFF. If false, 0. Halfword compare instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.h=cmp.gt(Lu16.uh, Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (LuV.uh[i] > LvV.uh[i]) ? 0xFFFF : 0x0;
}
Copy to clipboard | | Ld16.h=cmp.gt(Lu16.h, Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (LuV.h[i] > LvV.h[i]) ? 0xFFFF : 0x0;
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)**

Intrinsics

Halfword compare intrinsics
Ld16.h=cmp.gt(Lu16.uh, Lv16.uh)	HLX_Vector Q6_Lh_cmp_gt_LuhLuh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.h=cmp.gt(Lu16.h, Lv16.h)	HLX_Vector Q6_Lh_cmp_gt_LhLh(HLX_Vector Lu, HLX_Vector Lv)

Halfword to word convert intrinsics
Ldd16.uw=zxt(Lu16.uh)	HLX_VectorPair Q6_LWuw_zxt_Luh(HLX_Vector Lu)
Ldd16.w=sxt(Lu16.h)	HLX_VectorPair Q6_LWw_sxt_Lh(HLX_Vector Lu)

#### Halfword to word convert Convert from halfword to word either by zero-extending (zxt) or sign-extending (sxt). Halfword to word convert instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.uw=zxt(Lu16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = zxt_16_to_32(LuV.uh[i]);
}
Copy to clipboard | | Ldd16.w=sxt(Lu16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = sxt_16_to_32(LuV.h[i]);
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)** #### Logical operations Performs bitwise logical operations on halfword elements. andn/orn perform a bitwise not on the Lv16 input. Logical operations instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16=and(Lu16,Lv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = LuV.uh[i] & LvV.uh[i];
}
Copy to clipboard | | Ld16=or(Lu16,Lv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = LuV.uh[i] | LvV.uh[i];
}
Copy to clipboard | | Ld16=xor(Lu16,Lv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = LuV.uh[i] ^ LvV.uh[i];
}
Copy to clipboard | | Ld16=not(Lu16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = ~LuV.uh[i];
}
Copy to clipboard | | Ld16=andn(Lu16,Lv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = LuV.uh[i] & ~LvV.uh[i];
}
Copy to clipboard | | Ld16=orn(Lu16,Lv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = LuV.uh[i] | ~LvV.uh[i];
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)**

Intrinsics

Logical operations intrinsics
Ld16=and(Lu16,Lv16)	HLX_Vector Q6_L_and_LL(HLX_Vector Lu, HLX_Vector Lv)
Ld16=or(Lu16,Lv16)	HLX_Vector Q6_L_or_LL(HLX_Vector Lu, HLX_Vector Lv)
Ld16=xor(Lu16,Lv16)	HLX_Vector Q6_L_xor_LL(HLX_Vector Lu, HLX_Vector Lv)
Ld16=not(Lu16)	HLX_Vector Q6_L_not_L(HLX_Vector Lu)
Ld16=andn(Lu16,Lv16)	HLX_Vector Q6_L_andn_LL(HLX_Vector Lu, HLX_Vector Lv)
Ld16=orn(Lu16,Lv16)	HLX_Vector Q6_L_orn_LL(HLX_Vector Lu, HLX_Vector Lv)

#### Halfword min/max Compares the halfword elements and returns the maximum or minimum. The instructions place the result in the same position as the inputs. Halfword min/max instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.uh=max(Lu16.uh,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = (LuV.uh[i] > LvV.uh[i]) ? LuV.uh[i] : LvV.uh[i];
}
Copy to clipboard | | Ld16.uh=min(Lu16.uh,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = (LuV.uh[i] < LvV.uh[i]) ? LuV.uh[i] : LvV.uh[i];
}
Copy to clipboard | | Ld16.h=max(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (LuV.h[i] > LvV.h[i]) ? LuV.h[i] : LvV.h[i];
}
Copy to clipboard | | Ld16.h=min(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (LuV.h[i] < LvV.h[i]) ? LuV.h[i] : LvV.h[i];
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)**

Intrinsics

Halfword min/max intrinsics
Ld16.uh=max(Lu16.uh,Lv16.uh)	HLX_Vector Q6_Luh_max_LuhLuh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.uh=min(Lu16.uh,Lv16.uh)	HLX_Vector Q6_Luh_min_LuhLuh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.h=max(Lu16.h,Lv16.h)	HLX_Vector Q6_Lh_max_LhLh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.h=min(Lu16.h,Lv16.h)	HLX_Vector Q6_Lh_min_LhLh(HLX_Vector Lu, HLX_Vector Lv)

Mux select intrinsics
Lx16.h=mux(Lx16.h,Lu16.h,Lv16.h)	HLX_Vector Q6_Lh_mux_LhLhLh(HLX_Vector Lx, HLX_Vector Lu, HLX_Vector Lv)

#### Mux select HLX mux select Mux select instructions | **Syntax** | **Behavior** | | --- | --- | | Lx16.h=mux(Lx16.h,Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxV.h[i] = (LvV.h[i] < 0) ? LuV.h[i] : LxV.h[i];
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)** #### Splat value Assigns a value to each element of an L register Splat value instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.h=Rt.h | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i]=Rt.h[0];
}
Copy to clipboard | | Ld16.h=#s5 | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i]=s;
}
Copy to clipboard | | Ld16.uh=#u5 | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=u;
}
Copy to clipboard | | Ldd16.w=Rt.w | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w=Rt;
}
Copy to clipboard | **Class: ALUCOMMON (slots 2,3)**

Intrinsics

Splat value intrinsics
Ld16.h=Rt.h	HLX_Vector Q6_Lh_equals_Rh(Word32 Rt)
Ld16.h=#s5	HLX_Vector Q6_Lh_equals_Is(Word32 Is5)
Ld16.uh=#u5	HLX_Vector Q6_Luh_equals_I(Word32 Iu5)
Ldd16.w=Rt.w	HLX_VectorPair Q6_LWw_equals_Rw(Word32 Rt)

### EXTENDEDALU #### Absolute value of difference Calculates the absolute value of the difference between the corresponding elements in the L registers. Absolute value of difference instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.uh=absdiff(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = abs(LuV.h[i] - LvV.h[i]);
}
Copy to clipboard | | Ld16.uh=absdiff(Lu16.uh,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = (LuV.uh[i] > LvV.uh[i]) ? (LuV.uh[i] - LvV.uh[i]) : (LvV.uh[i] - LuV.uh[i]);
}
Copy to clipboard | | Ldd16.uw=absdiff(Luu16.w,Lvv16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = ABS(sxt_32_to_64(LuuV.l[i].w) - sxt_32_to_64(LvvV.l[i].w));
}
Copy to clipboard | | Ldd16.uw=absdiff(Luu16.uw,Lvv16.uw) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = (LuuV.l[i].uw > LvvV.l[i].uw) ? (LuuV.l[i].uw - LvvV.l[i].uw) : (LvvV.l[i].uw - LuuV.l[i].uw);
}
Copy to clipboard | **Class: EXTENDEDALU (slots 2)**

Intrinsics

Absolute value of difference intrinsics
Ld16.uh=absdiff(Lu16.h,Lv16.h)	HLX_Vector Q6_Luh_absdiff_LhLh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.uh=absdiff(Lu16.uh,Lv16.uh)	HLX_Vector Q6_Luh_absdiff_LuhLuh(HLX_Vector Lu, HLX_Vector Lv)
Ldd16.uw=absdiff(Luu16.w,Lvv16.w)	HLX_VectorPair Q6_LWuw_absdiff_LWwLWw(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uw=absdiff(Luu16.uw,Lvv16.uw)	HLX_VectorPair Q6_LWuw_absdiff_LWuwLWuw(HLX_VectorPair Luu, HLX_VectorPair Lvv)

#### Average Computes the averages of each corresponding element in the L registers. The round option adds 0x0001 to each result before shifting. This operation does not overflow. In the case that a summation (before right shift by 1) causes an overflow of 32 bits, the value shifted in is the most-significant carry out. Average instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.h=avg(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (LuV.h[i]+LvV.h[i])/2;
}
Copy to clipboard | | Ld16.h=avg(Lu16.h,Lv16.h):rnd | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (LuV.h[i]+LvV.h[i]+1)/2;
}
Copy to clipboard | | Ldd16.w=avg(Luu16.w,Lvv16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuuV.l[i].w+LvvV.l[i].w)/2;
}
Copy to clipboard | | Ldd16.w=avg(Luu16.w,Lvv16.w):rnd | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuuV.l[i].w+LvvV.l[i].w+1)/2;
}
Copy to clipboard | | Ld16.uh=avg(Lu16.uh,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = (LuV.uh[i]+LvV.uh[i])/2;
}
Copy to clipboard | | Ld16.uh=avg(Lu16.uh,Lv16.uh):rnd | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = (LuV.uh[i]+LvV.uh[i]+1)/2;
}
Copy to clipboard | | Ldd16.uw=avg(Luu16.uw,Lvv16.uw) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = (LuuV.l[i].uw+LvvV.l[i].uw)/2;
}
Copy to clipboard | | Ldd16.uw=avg(Luu16.uw,Lvv16.uw):rnd | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = (LuuV.l[i].uw+LvvV.l[i].uw+1)/2;
}
Copy to clipboard | **Class: EXTENDEDALU (slots 2)**

Intrinsics

Average intrinsics
Ld16.h=avg(Lu16.h,Lv16.h)	HLX_Vector Q6_Lh_avg_LhLh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.h=avg(Lu16.h,Lv16.h):rnd	HLX_Vector Q6_Lh_avg_LhLh_rnd(HLX_Vector Lu, HLX_Vector Lv)
Ldd16.w=avg(Luu16.w,Lvv16.w)	HLX_VectorPair Q6_LWw_avg_LWwLWw(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.w=avg(Luu16.w,Lvv16.w):rnd	HLX_VectorPair Q6_LWw_avg_LWwLWw_rnd(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ld16.uh=avg(Lu16.uh,Lv16.uh)	HLX_Vector Q6_Luh_avg_LuhLuh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.uh=avg(Lu16.uh,Lv16.uh):rnd	HLX_Vector Q6_Luh_avg_LuhLuh_rnd(HLX_Vector Lu, HLX_Vector Lv)
Ldd16.uw=avg(Luu16.uw,Lvv16.uw)	HLX_VectorPair Q6_LWuw_avg_LWuwLWuw(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uw=avg(Luu16.uw,Lvv16.uw):rnd	HLX_VectorPair Q6_LWuw_avg_LWuwLWuw_rnd(HLX_VectorPair Luu, HLX_VectorPair Lvv)

#### Byte converts Byte to halfword converts and halfword to byte converts. The halfword to byte converts select the high or low byte of a halfword and pack the bytes into a single 16-bit register. The byte to halfword converts unpack the two bytes into either the high byte or low byte of two halfword registers. Byte converts instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.b=packhi(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.b[2*i+1] = LuV.b[2*i+1];
LdV.b[2*i] = LvV.b[2*i+1];
}
Copy to clipboard | | Ld16.b=packlo(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.b[2*i+1] = LuV.b[2*i];
LdV.b[2*i] = LvV.b[2*i];
}
Copy to clipboard | | Ldd16.h=unpackhi(Lu16.b) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].b[3] = LuV.b[2*i+1];
LddV.l[i].b[1] = LuV.b[2*i];
}
Copy to clipboard | | Ldd16.h=unpacklo(Lu16.b) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].b[2] = LuV.b[2*i+1];
LddV.l[i].b[0] = LuV.b[2*i];
}
Copy to clipboard | **Class: EXTENDEDALU (slots 2)**

Intrinsics

Byte converts intrinsics
Ld16.b=packhi(Lu16.h,Lv16.h)	HLX_Vector Q6_Lb_packhi_LhLh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.b=packlo(Lu16.h,Lv16.h)	HLX_Vector Q6_Lb_packlo_LhLh(HLX_Vector Lu, HLX_Vector Lv)
Ldd16.h=unpackhi(Lu16.b)	HLX_VectorPair Q6_LWh_unpackhi_Lb(HLX_Vector Lu)
Ldd16.h=unpacklo(Lu16.b)	HLX_VectorPair Q6_LWh_unpacklo_Lb(HLX_Vector Lu)

#### Bit counting The count leading bits instructions count the number of consecutive zeros or consecutive ones starting with the most significant bit then adds/subs the secondary input operand. Bit counting instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.h=sub(ilog2(Lu16.h),#u4) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = bit_width(LuV.h[i] ^ -(LuV.h[i] < 0)) - 1 - u;
}
Copy to clipboard | | Ld16.h=sub(ilog2(Lu16.uh),#u4) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = bit_width(LuV.uh[i]) - 1 - u;
}
Copy to clipboard | | Ld16.h=sub(ilog2(Luu16.w),#u5) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = bit_width(LuuV.l[i].w ^ -(LuuV.l[i].w < 0)) - 1 - u;
}
Copy to clipboard | | Ld16.h=sub(ilog2(Luu16.uw),#u5) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = bit_width(LuuV.l[i].uw) - 1 - u;
}
Copy to clipboard | **Class: EXTENDEDALU (slots 2)**

Intrinsics

Bit counting intrinsics
Ld16.h=sub(ilog2(Lu16.h),#u4)	HLX_Vector Q6_Lh_sub_ilog2_LhI(HLX_Vector Lu, Word32 Iu4)
Ld16.h=sub(ilog2(Lu16.uh),#u4)	HLX_Vector Q6_Lh_sub_ilog2_LuhI(HLX_Vector Lu, Word32 Iu4)
Ld16.h=sub(ilog2(Luu16.w),#u5)	HLX_Vector Q6_Lh_sub_ilog2_LWwI(HLX_VectorPair Luu, Word32 Iu5)
Ld16.h=sub(ilog2(Luu16.uw),#u5)	HLX_Vector Q6_Lh_sub_ilog2_LWuwI(HLX_VectorPair Luu, Word32 Iu5)

#### Lookup table HLX lookup table Lookup table instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.h=lut4(Lu16.uh,Rtt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i]= Rtt.h[((LuV.uh[i]>>14)&0x3)];
}
Copy to clipboard | | Ldd16.w=lut4(Lu16.uh,Rtt.uh):>>1 | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = Rtt.uh[((LuV.uh[i]>>14)&0x3)].s32<<15;
}
Copy to clipboard | | Ldd16.w=lut4(Lu16.uh,Rtt.uh):>>1:neg | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (Rtt.uh[((LuV.uh[i]>>14)&0x3)].u32 - (1<<16))<<15;
}
Copy to clipboard | | Ld16.h=lut4(Lu16.uh,Rtt.h):mask | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (Rtt.h[((LuV.uh[i]>>14)&0x3)] & ((LuV.uh[i] & 0x3FFF) == 0 ? 0xFFFF : 0));
}
Copy to clipboard | **Class: EXTENDEDALU (slots 2)**

Intrinsics

Lookup table intrinsics
Ld16.h=lut4(Lu16.uh,Rtt.h)	HLX_Vector Q6_Lh_lut4_LuhPh(HLX_Vector Lu, Word64 Rtt)
Ldd16.w=lut4(Lu16.uh,Rtt.uh):>>1	HLX_VectorPair Q6_LWw_lut4_LuhPuh_rs1(HLX_Vector Lu, Word64 Rtt)
Ldd16.w=lut4(Lu16.uh,Rtt.uh):>>1:neg	HLX_VectorPair Q6_LWw_lut4_LuhPuh_rs1_neg(HLX_Vector Lu, Word64 Rtt)
Ld16.h=lut4(Lu16.uh,Rtt.h):mask	HLX_Vector Q6_Lh_lut4_LuhPh_mask(HLX_Vector Lu, Word64 Rtt)

#### Negative average Computes the negative average of each corresponding element in the L registers. The round option adds 0x0001 to each result before shifting. Negative average instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.h=navg(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (LuV.h[i]-LvV.h[i])/2;
}
Copy to clipboard | | Ldd16.w=navg(Luu16.w,Lvv16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuuV.l[i].w-LvvV.l[i].w)/2;
}
Copy to clipboard | | Ld16.h=navg(Lu16.uh,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (LuV.uh[i]-LvV.uh[i])/2;
}
Copy to clipboard | | Ldd16.w=navg(Luu16.uw,Lvv16.uw) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuuV.l[i].uw-LvvV.l[i].uw)/2;
}
Copy to clipboard | **Class: EXTENDEDALU (slots 2)**

Intrinsics

Negative average intrinsics
Ld16.h=navg(Lu16.h,Lv16.h)	HLX_Vector Q6_Lh_navg_LhLh(HLX_Vector Lu, HLX_Vector Lv)
Ldd16.w=navg(Luu16.w,Lvv16.w)	HLX_VectorPair Q6_LWw_navg_LWwLWw(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ld16.h=navg(Lu16.uh,Lv16.uh)	HLX_Vector Q6_Lh_navg_LuhLuh(HLX_Vector Lu, HLX_Vector Lv)
Ldd16.w=navg(Luu16.uw,Lvv16.uw)	HLX_VectorPair Q6_LWw_navg_LWuwLWuw(HLX_VectorPair Luu, HLX_VectorPair Lvv)

Load - tmp intrinsics
Ld16.tmp=mem(Rs)	HLX_Vector Q6_L_tmp_mem_A(void* BaseAddress)

### LOAD #### Load - tmp The load instructions loads data from VTCM to HLX registers. The instructions align memory accesses to 2048 bytes (~0x7FF), where HLX ignores the 11 least-significant bits (LSB) of the computed effective address (EA) and do not cause any exceptions if 11 LSB bits are non-zero. Load - tmp instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.tmp=mem(Rs) | EA=Rs;
ADDR = EA & HLX_MEM_ALIGN_MASK;
for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = *(ADDR+i);
}
Copy to clipboard | | if (Pv) Ld16.tmp=mem(Rs) | EA=Rs;
if(Pv[0]){
ADDR = EA & HLX_MEM_ALIGN_MASK;
for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i] = *(ADDR+i);
}
} else {
NOP;
}
Copy to clipboard | **Class: LOAD (slots 1)** ### MPY #### Multiply-add with high or low HLX multiply-adds with high or low halfword of word value Multiply-add with high or low instructions | **Syntax** | **Behavior** | | --- | --- | | Lxx16.uw=add(mpy(Lu16.uh,Rt.uh),lo(Lxx16).uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].uw = (LuV.uh[i] * Rt.uh[0]) + LxxV.l[i].uh[0];
}
Copy to clipboard | | Lxx16.uw=add(mpy(Lu16.uh,Lv16.uh),lo(Lxx16).uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].uw = (LuV.uh[i] * LvV.uh[i]) + LxxV.l[i].uh[0];
}
Copy to clipboard | | Lxx16.w=add(mpy(Lu16.h,Rt.uh),lo(Lxx16).uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w = (LuV.h[i] * Rt.uh[0]) + LxxV.l[i].uh[0];
}
Copy to clipboard | | Lxx16.w=add(mpy(Lu16.h,Lv16.uh),lo(Lxx16).uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w = (LuV.h[i] * LvV.uh[i]) + LxxV.l[i].uh[0];
}
Copy to clipboard | | Lxx16.uw=add(mpy(Lu16.uh,Rt.uh),hi(Lxx16).uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].uw = (LuV.uh[i] * Rt.uh[0]) + LxxV.l[i].uh[1];
}
Copy to clipboard | | Lxx16.uw=add(mpy(Lu16.uh,Lv16.uh),hi(Lxx16).uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].uw = (LuV.uh[i] * LvV.uh[i]) + LxxV.l[i].uh[1];
}
Copy to clipboard | | Lxx16.uw=add(mpy(Lu16.h,Rt.uh),hi(Lxx16).uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].uw = (LuV.h[i] * Rt.uh[0]) + LxxV.l[i].uh[1];
}
Copy to clipboard | | Lxx16.uw=add(mpy(Lu16.h,Lv16.uh),hi(Lxx16).uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].uw = (LuV.h[i] * LvV.uh[i]) + LxxV.l[i].uh[1];
}
Copy to clipboard | | Lxx16.uw=add(mpy(Lu16.uh,hi(Lxx16).uh),Rt.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].uw = Rt.w[0] + (LxxV.l[i].uh[1] * LuV.h[i]);
}
Copy to clipboard | | Lxx16.uw=add(mpy(Lu16.uh,hi(Lxx16).uh),Lvv16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].uw = LvvV.l[i].w + (LxxV.l[i].uh[1] * LuV.h[i]);
}
Copy to clipboard | | Lxx16.w=add(mpy(Lu16.uh,hi(Lxx16).h),Rt.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w = Rt.w[0] + (LxxV.l[i].h[1] * LuV.uh[i]);
}
Copy to clipboard | | Lxx16.w=add(mpy(Lu16.uh,hi(Lxx16).h),Lvv16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w = LvvV.l[i].w + (LxxV.l[i].h[1] * LuV.uh[i]);
}
Copy to clipboard | **Class: MPY (slots 3)**

Intrinsics

Multiply-add with high or low intrinsics
Lxx16.uw=add(mpy(Lu16.uh,Rt.uh),lo(Lxx16).uh)	HLX_VectorPair Q6_LWuw_add_mpy_lo_LuhRuhLWuh(HLX_Vector Lu, Word32 Rt, HLX_VectorPair Lxx)
Lxx16.uw=add(mpy(Lu16.uh,Lv16.uh),lo(Lxx16).uh)	HLX_VectorPair Q6_LWuw_add_mpy_lo_LuhLuhLWuh(HLX_Vector Lu, HLX_Vector Lv, HLX_VectorPair Lxx)
Lxx16.w=add(mpy(Lu16.h,Rt.uh),lo(Lxx16).uh)	HLX_VectorPair Q6_LWw_add_mpy_lo_LhRuhLWuh(HLX_Vector Lu, Word32 Rt, HLX_VectorPair Lxx)
Lxx16.w=add(mpy(Lu16.h,Lv16.uh),lo(Lxx16).uh)	HLX_VectorPair Q6_LWw_add_mpy_lo_LhLuhLWuh(HLX_Vector Lu, HLX_Vector Lv, HLX_VectorPair Lxx)
Lxx16.uw=add(mpy(Lu16.uh,Rt.uh),hi(Lxx16).uh)	HLX_VectorPair Q6_LWuw_add_mpy_hi_LuhRuhLWuh(HLX_Vector Lu, Word32 Rt, HLX_VectorPair Lxx)
Lxx16.uw=add(mpy(Lu16.uh,Lv16.uh),hi(Lxx16).uh)	HLX_VectorPair Q6_LWuw_add_mpy_hi_LuhLuhLWuh(HLX_Vector Lu, HLX_Vector Lv, HLX_VectorPair Lxx)
Lxx16.uw=add(mpy(Lu16.h,Rt.uh),hi(Lxx16).uh)	HLX_VectorPair Q6_LWuw_add_mpy_hi_LhRuhLWuh(HLX_Vector Lu, Word32 Rt, HLX_VectorPair Lxx)
Lxx16.uw=add(mpy(Lu16.h,Lv16.uh),hi(Lxx16).uh)	HLX_VectorPair Q6_LWuw_add_mpy_hi_LhLuhLWuh(HLX_Vector Lu, HLX_Vector Lv, HLX_VectorPair Lxx)
Lxx16.uw=add(mpy(Lu16.uh,hi(Lxx16).uh),Rt.w)	HLX_VectorPair Q6_LWuw_add_mpy_hi_LuhLWuhRw(HLX_Vector Lu, HLX_VectorPair Lxx, Word32 Rt)
Lxx16.uw=add(mpy(Lu16.uh,hi(Lxx16).uh),Lvv16.w)	HLX_VectorPair Q6_LWuw_add_mpy_hi_LuhLWuhLWw(HLX_Vector Lu, HLX_VectorPair Lxx, HLX_VectorPair Lvv)
Lxx16.w=add(mpy(Lu16.uh,hi(Lxx16).h),Rt.w)	HLX_VectorPair Q6_LWw_add_mpy_hi_LuhLWhRw(HLX_Vector Lu, HLX_VectorPair Lxx, Word32 Rt)
Lxx16.w=add(mpy(Lu16.uh,hi(Lxx16).h),Lvv16.w)	HLX_VectorPair Q6_LWw_add_mpy_hi_LuhLWhLWw(HLX_Vector Lu, HLX_VectorPair Lxx, HLX_VectorPair Lvv)

#### Multiply-add HLX multiply and add instructions Multiply-add instructions | **Syntax** | **Behavior** | | --- | --- | | Lxx16.w+=mpy(Lu16.uh,Rt.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w += (LuV.uh[i] * Rt.uh[0]);
}
Copy to clipboard | | Lxx16.w+=mpy(Lu16.uh,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w += (LuV.uh[i] * LvV.uh[i]);
}
Copy to clipboard | | Lxx16.w+=mpy(Lu16.h,Rt.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w = LxxV.l[i].w + (LuV.h[i] * Rt.uh[0]);
}
Copy to clipboard | | Lxx16.w+=mpy(Lu16.h,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w = LxxV.l[i].w + (LuV.h[i] * LvV.uh[i]);
}
Copy to clipboard | | Lxx16.w+=mpy(Lu16.h,Rt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w = LxxV.l[i].w + (LuV.h[i] * Rt.h[0]);
}
Copy to clipboard | | Lxx16.w+=mpy(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w = LxxV.l[i].w + (LuV.h[i] * LvV.h[i]);
}
Copy to clipboard | **Class: MPY (slots 3)**

Intrinsics

Multiply-add intrinsics
Lxx16.w+=mpy(Lu16.uh,Rt.uh)	HLX_VectorPair Q6_LWw_mpyacc_LuhRuh(HLX_VectorPair Lxx, HLX_Vector Lu, Word32 Rt)
Lxx16.w+=mpy(Lu16.uh,Lv16.uh)	HLX_VectorPair Q6_LWw_mpyacc_LuhLuh(HLX_VectorPair Lxx, HLX_Vector Lu, HLX_Vector Lv)
Lxx16.w+=mpy(Lu16.h,Rt.uh)	HLX_VectorPair Q6_LWw_mpyacc_LhRuh(HLX_VectorPair Lxx, HLX_Vector Lu, Word32 Rt)
Lxx16.w+=mpy(Lu16.h,Lv16.uh)	HLX_VectorPair Q6_LWw_mpyacc_LhLuh(HLX_VectorPair Lxx, HLX_Vector Lu, HLX_Vector Lv)
Lxx16.w+=mpy(Lu16.h,Rt.h)	HLX_VectorPair Q6_LWw_mpyacc_LhRh(HLX_VectorPair Lxx, HLX_Vector Lu, Word32 Rt)
Lxx16.w+=mpy(Lu16.h,Lv16.h)	HLX_VectorPair Q6_LWw_mpyacc_LhLh(HLX_VectorPair Lxx, HLX_Vector Lu, HLX_Vector Lv)

#### Halfword to word multiply HLX halfword to word widening multiply. Halfword to word multiply instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.uw=mpy(Lu16.uh,Rt.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = (LuV.uh[i] * Rt.uh[0]);
}
Copy to clipboard | | Ldd16.uw=mpy(Lu16.uh,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = (LuV.uh[i] * LvV.uh[i]);
}
Copy to clipboard | | Ldd16.w=mpy(Lu16.h,Rt.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuV.h[i] * Rt.uh[0]);
}
Copy to clipboard | | Ldd16.w=mpy(Lu16.h,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuV.h[i] * LvV.uh[i]);
}
Copy to clipboard | | Ldd16.w=mpy(Lu16.h,Rt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuV.h[i] * Rt.h[0]);
}
Copy to clipboard | | Ldd16.w=mpy(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuV.h[i] * LvV.h[i]);
}
Copy to clipboard | **Class: MPY (slots 3)**

Intrinsics

Halfword to word multiply intrinsics
Ldd16.uw=mpy(Lu16.uh,Rt.uh)	HLX_VectorPair Q6_LWuw_mpy_LuhRuh(HLX_Vector Lu, Word32 Rt)
Ldd16.uw=mpy(Lu16.uh,Lv16.uh)	HLX_VectorPair Q6_LWuw_mpy_LuhLuh(HLX_Vector Lu, HLX_Vector Lv)
Ldd16.w=mpy(Lu16.h,Rt.uh)	HLX_VectorPair Q6_LWw_mpy_LhRuh(HLX_Vector Lu, Word32 Rt)
Ldd16.w=mpy(Lu16.h,Lv16.uh)	HLX_VectorPair Q6_LWw_mpy_LhLuh(HLX_Vector Lu, HLX_Vector Lv)
Ldd16.w=mpy(Lu16.h,Rt.h)	HLX_VectorPair Q6_LWw_mpy_LhRh(HLX_Vector Lu, Word32 Rt)
Ldd16.w=mpy(Lu16.h,Lv16.h)	HLX_VectorPair Q6_LWw_mpy_LhLh(HLX_Vector Lu, HLX_Vector Lv)

### PAIREDALU #### Paired and word absolute value Calculates the absolute value of a word or paired halfword elements. Paired and word absolute value instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.uw=abs(Luu16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = abs(LuuV.l[i].w);
}
Copy to clipboard | | Ldd16.w=abs(Luu16.w):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = sat_32(abs(LuuV.l[i].w));
}
Copy to clipboard | | Ldd16.uh=abs(Luu16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uh[0] = abs(LuuV.l[i].h[0]);
LddV.l[i].uh[1] = abs(LuuV.l[i].h[1]);
}
Copy to clipboard | | Ldd16.h=abs(Luu16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].h[0] = sat_16(abs(LuuV.l[i].h[0]));
LddV.l[i].h[1] = sat_16(abs(LuuV.l[i].h[1]));
}
Copy to clipboard | **Class: PAIREDALU (slots 2)**

Intrinsics

Paired and word absolute value intrinsics
Ldd16.uw=abs(Luu16.w)	HLX_VectorPair Q6_LWuw_abs_LWw(HLX_VectorPair Luu)
Ldd16.w=abs(Luu16.w):sat	HLX_VectorPair Q6_LWw_abs_LWw_sat(HLX_VectorPair Luu)
Ldd16.uh=abs(Luu16.h)	HLX_VectorPair Q6_LWuh_abs_LWh(HLX_VectorPair Luu)
Ldd16.h=abs(Luu16.h):sat	HLX_VectorPair Q6_LWh_abs_LWh_sat(HLX_VectorPair Luu)

#### Paired halfword add/subtract Performs arithmetic add and subtract using the word elements of two L registers pairs. Supports unsigned and signed values. Optionally saturates. Paired halfword add/subtract instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.h=add(Luu16.h,Lvv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].h[0] = LuuV.l[i].h[0] + LvvV.l[i].h[0];
LddV.l[i].h[1] = LuuV.l[i].h[1] + LvvV.l[i].h[1];
}
Copy to clipboard | | Ldd16.h=add(Luu16.h,Lvv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].h[0] = sat_16(LuuV.l[i].h[0]+LvvV.l[i].h[0]);
LddV.l[i].h[1] = sat_16(LuuV.l[i].h[1]+LvvV.l[i].h[1]);
}
Copy to clipboard | | Ldd16.uh=add(Luu16.uh,Lvv16.uh):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uh[0] = usat_16(LuuV.l[i].uh[0]+LvvV.l[i].uh[0]);
LddV.l[i].uh[1] = usat_16(LuuV.l[i].uh[1]+LvvV.l[i].uh[1]);
}
Copy to clipboard | | Ldd16.uh=add(Luu16.h,Lvv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uh[0] = usat_16(LuuV.l[i].h[0]+LvvV.l[i].h[0]);
LddV.l[i].uh[1] = usat_16(LuuV.l[i].h[1]+LvvV.l[i].h[1]);
}
Copy to clipboard | | Ldd16.h=sub(Luu16.h,Lvv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].h[0] = LuuV.l[i].h[0] - LvvV.l[i].h[0];
LddV.l[i].h[1] = LuuV.l[i].h[1] - LvvV.l[i].h[1];
}
Copy to clipboard | | Ldd16.h=sub(Luu16.h,Lvv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].h[0] = sat_16(LuuV.l[i].h[0]-LvvV.l[i].h[0]);
LddV.l[i].h[1] = sat_16(LuuV.l[i].h[1]-LvvV.l[i].h[1]);
}
Copy to clipboard | | Ldd16.uh=sub(Luu16.uh,Lvv16.uh):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uh[0] = usat_16(LuuV.l[i].uh[0]-LvvV.l[i].uh[0]);
LddV.l[i].uh[1] = usat_16(LuuV.l[i].uh[1]-LvvV.l[i].uh[1]);
}
Copy to clipboard | | Ldd16.uh=sub(Luu16.h,Lvv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uh[0] = usat_16(LuuV.l[i].h[0]-LvvV.l[i].h[0]);
LddV.l[i].uh[1] = usat_16(LuuV.l[i].h[1]-LvvV.l[i].h[1]);
}
Copy to clipboard | **Class: PAIREDALU (slots 2)**

Intrinsics

Paired halfword add/subtract intrinsics
Ldd16.h=add(Luu16.h,Lvv16.h)	HLX_VectorPair Q6_LWh_add_LWhLWh(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.h=add(Luu16.h,Lvv16.h):sat	HLX_VectorPair Q6_LWh_add_LWhLWh_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uh=add(Luu16.uh,Lvv16.uh):sat	HLX_VectorPair Q6_LWuh_add_LWuhLWuh_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uh=add(Luu16.h,Lvv16.h):sat	HLX_VectorPair Q6_LWuh_add_LWhLWh_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.h=sub(Luu16.h,Lvv16.h)	HLX_VectorPair Q6_LWh_sub_LWhLWh(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.h=sub(Luu16.h,Lvv16.h):sat	HLX_VectorPair Q6_LWh_sub_LWhLWh_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uh=sub(Luu16.uh,Lvv16.uh):sat	HLX_VectorPair Q6_LWuh_sub_LWuhLWuh_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uh=sub(Luu16.h,Lvv16.h):sat	HLX_VectorPair Q6_LWuh_sub_LWhLWh_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)

#### Word add/subtract Performs arithmetic add and subtract using the word elements of two L registers. Supports unsigned and signed values. Optionally saturates. Word add/subtract instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.w=add(Luu16.w,Lvv16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w + LvvV.l[i].w;
}
Copy to clipboard | | Ldd16.w=add(Luu16.w,Lvv16.w):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = sat_32(LuuV.l[i].w+LvvV.l[i].w);
}
Copy to clipboard | | Ldd16.uw=add(Luu16.uw,Lvv16.uw):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = usat_32(LuuV.l[i].uw+LvvV.l[i].uw);
}
Copy to clipboard | | Ldd16.uw=add(Luu16.w,Lvv16.w):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = usat_32(LuuV.l[i].w+LvvV.l[i].w);
}
Copy to clipboard | | Ldd16.w=sub(Luu16.w,Lvv16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w - LvvV.l[i].w;
}
Copy to clipboard | | Ldd16.w=sub(Luu16.w,Lvv16.w):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = sat_32(LuuV.l[i].w-LvvV.l[i].w);
}
Copy to clipboard | | Ldd16.uw=sub(Luu16.uw,Lvv16.uw):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = usat_32(LuuV.l[i].uw-LvvV.l[i].uw);
}
Copy to clipboard | | Ldd16.uw=sub(Luu16.w,Lvv16.w):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = usat_32(LuuV.l[i].w-LvvV.l[i].w);
}
Copy to clipboard | **Class: PAIREDALU (slots 2)**

Intrinsics

Word add/subtract intrinsics
Ldd16.w=add(Luu16.w,Lvv16.w)	HLX_VectorPair Q6_LWw_add_LWwLWw(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.w=add(Luu16.w,Lvv16.w):sat	HLX_VectorPair Q6_LWw_add_LWwLWw_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uw=add(Luu16.uw,Lvv16.uw):sat	HLX_VectorPair Q6_LWuw_add_LWuwLWuw_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uw=add(Luu16.w,Lvv16.w):sat	HLX_VectorPair Q6_LWuw_add_LWwLWw_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.w=sub(Luu16.w,Lvv16.w)	HLX_VectorPair Q6_LWw_sub_LWwLWw(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.w=sub(Luu16.w,Lvv16.w):sat	HLX_VectorPair Q6_LWw_sub_LWwLWw_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uw=sub(Luu16.uw,Lvv16.uw):sat	HLX_VectorPair Q6_LWuw_sub_LWuwLWuw_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uw=sub(Luu16.w,Lvv16.w):sat	HLX_VectorPair Q6_LWuw_sub_LWwLWw_sat(HLX_VectorPair Luu, HLX_VectorPair Lvv)

#### Word logical operations Performs bitwise logical operations on word elements. andn/orn perform a bitwise not on the Lvv16 input. Word logical operations instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16=and(Luu16,Lvv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w & LvvV.l[i].w;
}
Copy to clipboard | | Ldd16=or(Luu16,Lvv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w | LvvV.l[i].w;
}
Copy to clipboard | | Ldd16=xor(Luu16,Lvv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w ^ LvvV.l[i].w;
}
Copy to clipboard | | Ldd16=andn(Luu16,Lvv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w & ~LvvV.l[i].w;
}
Copy to clipboard | | Ldd16=orn(Luu16,Lvv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = LuuV.l[i].w | ~LvvV.l[i].w;
}
Copy to clipboard | | Ldd16=not(Luu16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw=~LuuV.l[i].uw;
}
Copy to clipboard | **Class: PAIREDALU (slots 2)**

Intrinsics

Word logical operations intrinsics
Ldd16=and(Luu16,Lvv16)	HLX_VectorPair Q6_LW_and_LWLW(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16=or(Luu16,Lvv16)	HLX_VectorPair Q6_LW_or_LWLW(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16=xor(Luu16,Lvv16)	HLX_VectorPair Q6_LW_xor_LWLW(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16=andn(Luu16,Lvv16)	HLX_VectorPair Q6_LW_andn_LWLW(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16=orn(Luu16,Lvv16)	HLX_VectorPair Q6_LW_orn_LWLW(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16=not(Luu16)	HLX_VectorPair Q6_LW_not_LW(HLX_VectorPair Luu)

#### Paired halfword logical compare - Compares a pair of two halfword element registers for halfword greater than (gt). - If the result is true for an element, HLX sets the corresponding destination register element to 0xFFFF. If false, 0. Paired halfword logical compare instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.h=cmp.gt(Luu16.h, Lvv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].h[0] = (LuuV.l[i].h[0] > LvvV.l[i].h[0]) ? 0xFFFF : 0x0;
LddV.l[i].h[1] = (LuuV.l[i].h[1] > LvvV.l[i].h[1]) ? 0xFFFF : 0x0;
}
Copy to clipboard | | Ldd16.h=cmp.gt(Luu16.uh, Lvv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].h[0] = (LuuV.l[i].uh[0] > LvvV.l[i].uh[0]) ? 0xFFFF : 0x0;
LddV.l[i].h[1] = (LuuV.l[i].uh[1] > LvvV.l[i].uh[1]) ? 0xFFFF : 0x0;
}
Copy to clipboard | **Class: PAIREDALU (slots 2)**

Intrinsics

Paired halfword logical compare intrinsics
Ldd16.h=cmp.gt(Luu16.h, Lvv16.h)	HLX_VectorPair Q6_LWh_cmp_gt_LWhLWh(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.h=cmp.gt(Luu16.uh, Lvv16.uh)	HLX_VectorPair Q6_LWh_cmp_gt_LWuhLWuh(HLX_VectorPair Luu, HLX_VectorPair Lvv)

#### Word compare - Compares two halfword element registers for word greater than (gt). - If the result is true for an element, HLX sets the corresponding destination register element to 0xFFFFFFFF. If false, 0. Word compare instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.w=cmp.gt(Luu16.w, Lvv16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuuV.l[i].w > LvvV.l[i].w) ? 0xFFFFFFFF : 0x0;
}
Copy to clipboard | | Ldd16.w=cmp.gt(Luu16.uw, Lvv16.uw) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuuV.l[i].uw > LvvV.l[i].uw) ? 0xFFFFFFFF : 0x0;
}
Copy to clipboard | **Class: PAIREDALU (slots 2)**

Intrinsics

Word compare intrinsics
Ldd16.w=cmp.gt(Luu16.w, Lvv16.w)	HLX_VectorPair Q6_LWw_cmp_gt_LWwLWw(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.w=cmp.gt(Luu16.uw, Lvv16.uw)	HLX_VectorPair Q6_LWw_cmp_gt_LWuwLWuw(HLX_VectorPair Luu, HLX_VectorPair Lvv)

#### Combine Combine two halfword element registers into a 32-bit value. Lu16 is the high halfword and Lv16 is the low halfword. Combine instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16=combine(Lu16,Lv16) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].h[1] = LuV.h[i];
LddV.l[i].h[0] = LvV.h[i];
}
Copy to clipboard | **Class: PAIREDALU (slots 2)** #### Word min/max Compares the word elements and returns the maximum or minimum value per element. The instructions place the result in the same position as the inputs. Word min/max instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.w=min(Luu16.w,Lvv16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuuV.l[i].w < LvvV.l[i].w) ? LuuV.l[i].w : LvvV.l[i].w;
}
Copy to clipboard | | Ldd16.uw=min(Luu16.uw,Lvv16.uw) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = (LuuV.l[i].uw < LvvV.l[i].uw) ? LuuV.l[i].uw : LvvV.l[i].uw;
}
Copy to clipboard | | Ldd16.w=max(Luu16.w,Lvv16.w) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w = (LuuV.l[i].w > LvvV.l[i].w) ? LuuV.l[i].w : LvvV.l[i].w;
}
Copy to clipboard | | Ldd16.uw=max(Luu16.uw,Lvv16.uw) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw = (LuuV.l[i].uw > LvvV.l[i].uw) ? LuuV.l[i].uw : LvvV.l[i].uw;
}
Copy to clipboard | **Class: PAIREDALU (slots 2)**

Intrinsics

Word min/max intrinsics
Ldd16.w=min(Luu16.w,Lvv16.w)	HLX_VectorPair Q6_LWw_min_LWwLWw(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uw=min(Luu16.uw,Lvv16.uw)	HLX_VectorPair Q6_LWuw_min_LWuwLWuw(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.w=max(Luu16.w,Lvv16.w)	HLX_VectorPair Q6_LWw_max_LWwLWw(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uw=max(Luu16.uw,Lvv16.uw)	HLX_VectorPair Q6_LWuw_max_LWuwLWuw(HLX_VectorPair Luu, HLX_VectorPair Lvv)

#### Paired halfword min/max Compares the halfword elements in the paired L registers and returns the maximum or minimum value. The instructions place the result in the same position as the inputs. Paired halfword min/max instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.h=min(Luu16.h,Lvv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].h[0] = (LuuV.l[i].h[0] < LvvV.l[i].h[0]) ? LuuV.l[i].h[0] : LvvV.l[i].h[0];
LddV.l[i].h[1] = (LuuV.l[i].h[1] < LvvV.l[i].h[1]) ? LuuV.l[i].h[1] : LvvV.l[i].h[1];
}
Copy to clipboard | | Ldd16.uh=min(Luu16.uh,Lvv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uh[0] = (LuuV.l[i].uh[0] < LvvV.l[i].uh[0]) ? LuuV.l[i].uh[0] : LvvV.l[i].uh[0];
LddV.l[i].uh[1] = (LuuV.l[i].uh[1] < LvvV.l[i].uh[1]) ? LuuV.l[i].uh[1] : LvvV.l[i].uh[1];
}
Copy to clipboard | | Ldd16.h=max(Luu16.h,Lvv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].h[0] = (LuuV.l[i].h[0] > LvvV.l[i].h[0]) ? LuuV.l[i].h[0] : LvvV.l[i].h[0];
LddV.l[i].h[1] = (LuuV.l[i].h[1] > LvvV.l[i].h[1]) ? LuuV.l[i].h[1] : LvvV.l[i].h[1];
}
Copy to clipboard | | Ldd16.uh=max(Luu16.uh,Lvv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uh[0] = (LuuV.l[i].uh[0] > LvvV.l[i].uh[0]) ? LuuV.l[i].uh[0] : LvvV.l[i].uh[0];
LddV.l[i].uh[1] = (LuuV.l[i].uh[1] > LvvV.l[i].uh[1]) ? LuuV.l[i].uh[1] : LvvV.l[i].uh[1];
}
Copy to clipboard | **Class: PAIREDALU (slots 2)**

Intrinsics

Paired halfword min/max intrinsics
Ldd16.h=min(Luu16.h,Lvv16.h)	HLX_VectorPair Q6_LWh_min_LWhLWh(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uh=min(Luu16.uh,Lvv16.uh)	HLX_VectorPair Q6_LWuh_min_LWuhLWuh(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.h=max(Luu16.h,Lvv16.h)	HLX_VectorPair Q6_LWh_max_LWhLWh(HLX_VectorPair Luu, HLX_VectorPair Lvv)
Ldd16.uh=max(Luu16.uh,Lvv16.uh)	HLX_VectorPair Q6_LWuh_max_LWuhLWuh(HLX_VectorPair Luu, HLX_VectorPair Lvv)

### SHIFT #### Halfword bidirectional shift HLX halfword bidirecitonal shift instructions. Positive shift amounts shift to the right, negative shift amounts shift to the left. Halfword bidirectional shift instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.uh=shr(Lu16.uh,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=(LvV.h[i] <= 0) ? LuV.uh[i]<<(-LvV.h[i]) : (LuV.uh[i]>>LvV.h[i]);
}
Copy to clipboard | | Ld16.uh=shr(Lu16.uh,Rt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=(Rt.h[0] <= 0) ? LuV.uh[i]<<(-Rt.h[0]) : (LuV.uh[i]>>Rt.h[0]);
}
Copy to clipboard | | Ld16.h=shr(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i]=(LvV.h[i] <= 0) ? LuV.h[i]<<(-LvV.h[i]) : (LuV.h[i]>>LvV.h[i]);
}
Copy to clipboard | | Ld16.h=shr(Lu16.h,Rt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i]=(Rt.h[0] <= 0) ? LuV.h[i]<<(-Rt.h[0]) : (LuV.h[i]>>Rt.h[0]);
}
Copy to clipboard | **Class: SHIFT (slots 2)**

Intrinsics

Halfword bidirectional shift intrinsics
Ld16.uh=shr(Lu16.uh,Lv16.h)	HLX_Vector Q6_Luh_shr_LuhLh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.uh=shr(Lu16.uh,Rt.h)	HLX_Vector Q6_Luh_shr_LuhRh(HLX_Vector Lu, Word32 Rt)
Ld16.h=shr(Lu16.h,Lv16.h)	HLX_Vector Q6_Lh_shr_LhLh(HLX_Vector Lu, HLX_Vector Lv)
Ld16.h=shr(Lu16.h,Rt.h)	HLX_Vector Q6_Lh_shr_LhRh(HLX_Vector Lu, Word32 Rt)

#### Word to halfword narrowing bidirectional shift HLX word to halfword bidirecitonal shift instructions. Positive shift amounts shift to the right, negative shift amounts shift to the left. Word to halfword narrowing bidirectional shift instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.h=shr(Luu16.w,Lv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i]=sat_16((LvV.h[i] <= 0) ? LuuV.l[i].w<<(-LvV.h[i]) : (LuuV.l[i].w>>LvV.h[i]));
}
Copy to clipboard | | Ld16.h=shr(Luu16.w,Lv16.h):rnd:sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i]=sat_16((LvV.h[i] <= 0) ? LuuV.l[i].w<<(-LvV.h[i]) : (LuuV.l[i].w>>LvV.h[i]));
}
Copy to clipboard | | Ld16.h=shr(Luu16.w,Rt.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i]=sat_16((Rt.h[0] <= 0) ? LuuV.l[i].w<<(-Rt.h[0]) : (LuuV.l[i].w>>Rt.h[0]));
}
Copy to clipboard | | Ld16.h=shr(Luu16.w,Rt.h):rnd:sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i]=sat_16((Rt.h[0] <= 0) ? LuuV.l[i].w<<(-Rt.h[0]) : (LuuV.l[i].w>>Rt.h[0]));
}
Copy to clipboard | | Ld16.uh=shr(Luu16.uw,Lv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=usat_16((LvV.h[i] <= 0) ? LuuV.l[i].uw<<(-LvV.h[i]) : (LuuV.l[i].uw>>LvV.h[i]));
}
Copy to clipboard | | Ld16.uh=shr(Luu16.uw,Lv16.h):rnd:sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=usat_16((LvV.h[i] <= 0) ? LuuV.l[i].uw<<(-LvV.h[i]) : (LuuV.l[i].uw>>LvV.h[i]));
}
Copy to clipboard | | Ld16.uh=shr(Luu16.uw,Rt.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=usat_16((Rt.h[0] <= 0) ? LuuV.l[i].uw<<(-Rt.h[0]) : (LuuV.l[i].uw>>Rt.h[0]));
}
Copy to clipboard | | Ld16.uh=shr(Luu16.uw,Rt.h):rnd:sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=usat_16((Rt.h[0] <= 0) ? LuuV.l[i].uw<<(-Rt.h[0]) : (LuuV.l[i].uw>>Rt.h[0]));
}
Copy to clipboard | | Ld16.uh=shr(Luu16.w,Lv16.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=usat_16((LvV.h[i] <= 0) ? LuuV.l[i].w<<(-LvV.h[i]) : (LuuV.l[i].w>>LvV.h[i]));
}
Copy to clipboard | | Ld16.uh=shr(Luu16.w,Lv16.h):rnd:sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=usat_16((LvV.h[i] <= 0) ? LuuV.l[i].w<<(-LvV.h[i]) : (LuuV.l[i].w>>LvV.h[i]));
}
Copy to clipboard | | Ld16.uh=shr(Luu16.w,Rt.h):sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=usat_16((Rt.h[0] <= 0) ? LuuV.l[i].w<<(-Rt.h[0]) : (LuuV.l[i].w>>Rt.h[0]));
}
Copy to clipboard | | Ld16.uh=shr(Luu16.w,Rt.h):rnd:sat | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.uh[i]=usat_16((Rt.h[0] <= 0) ? LuuV.l[i].w<<(-Rt.h[0]) : (LuuV.l[i].w>>Rt.h[0]));
}
Copy to clipboard | **Class: SHIFT (slots 2)**

Intrinsics

Word to halfword narrowing bidirectional shift intrinsics
Ld16.h=shr(Luu16.w,Lv16.h):sat	HLX_Vector Q6_Lh_shr_LWwLh_sat(HLX_VectorPair Luu, HLX_Vector Lv)
Ld16.h=shr(Luu16.w,Lv16.h):rnd:sat	HLX_Vector Q6_Lh_shr_LWwLh_rnd_sat(HLX_VectorPair Luu, HLX_Vector Lv)
Ld16.h=shr(Luu16.w,Rt.h):sat	HLX_Vector Q6_Lh_shr_LWwRh_sat(HLX_VectorPair Luu, Word32 Rt)
Ld16.h=shr(Luu16.w,Rt.h):rnd:sat	HLX_Vector Q6_Lh_shr_LWwRh_rnd_sat(HLX_VectorPair Luu, Word32 Rt)
Ld16.uh=shr(Luu16.uw,Lv16.h):sat	HLX_Vector Q6_Luh_shr_LWuwLh_sat(HLX_VectorPair Luu, HLX_Vector Lv)
Ld16.uh=shr(Luu16.uw,Lv16.h):rnd:sat	HLX_Vector Q6_Luh_shr_LWuwLh_rnd_sat(HLX_VectorPair Luu, HLX_Vector Lv)
Ld16.uh=shr(Luu16.uw,Rt.h):sat	HLX_Vector Q6_Luh_shr_LWuwRh_sat(HLX_VectorPair Luu, Word32 Rt)
Ld16.uh=shr(Luu16.uw,Rt.h):rnd:sat	HLX_Vector Q6_Luh_shr_LWuwRh_rnd_sat(HLX_VectorPair Luu, Word32 Rt)
Ld16.uh=shr(Luu16.w,Lv16.h):sat	HLX_Vector Q6_Luh_shr_LWwLh_sat(HLX_VectorPair Luu, HLX_Vector Lv)
Ld16.uh=shr(Luu16.w,Lv16.h):rnd:sat	HLX_Vector Q6_Luh_shr_LWwLh_rnd_sat(HLX_VectorPair Luu, HLX_Vector Lv)
Ld16.uh=shr(Luu16.w,Rt.h):sat	HLX_Vector Q6_Luh_shr_LWwRh_sat(HLX_VectorPair Luu, Word32 Rt)
Ld16.uh=shr(Luu16.w,Rt.h):rnd:sat	HLX_Vector Q6_Luh_shr_LWwRh_rnd_sat(HLX_VectorPair Luu, Word32 Rt)

#### Word bidirectional shift HLX word bidirecitonal shift instructions. Positive shift amounts shift to the right, negative shift amounts shift to the left. Word bidirectional shift instructions | **Syntax** | **Behavior** | | --- | --- | | Ldd16.uw=shr(Luu16.uw,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw=(LvV.h[i] <= 0) ? LuuV.l[i].uw<<(-LvV.h[i]) : (LuuV.l[i].uw>>LvV.h[i]);
}
Copy to clipboard | | Ldd16.uw=shr(Luu16.uw,Rt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].uw=(Rt.h[0] <= 0) ? LuuV.l[i].uw<<(-Rt.h[0]) : (LuuV.l[i].uw>>Rt.h[0]);
}
Copy to clipboard | | Ldd16.w=shr(Luu16.w,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w=(LvV.h[i] <= 0) ? LuuV.l[i].w<<(-LvV.h[i]) : (LuuV.l[i].w>>LvV.h[i]);
}
Copy to clipboard | | Ldd16.w=shr(Luu16.w,Rt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LddV.l[i].w=(Rt.h[0] <= 0) ? LuuV.l[i].w<<(-Rt.h[0]) : (LuuV.l[i].w>>Rt.h[0]);
}
Copy to clipboard | **Class: SHIFT (slots 2)**

Intrinsics

Word bidirectional shift intrinsics
Ldd16.uw=shr(Luu16.uw,Lv16.h)	HLX_VectorPair Q6_LWuw_shr_LWuwLh(HLX_VectorPair Luu, HLX_Vector Lv)
Ldd16.uw=shr(Luu16.uw,Rt.h)	HLX_VectorPair Q6_LWuw_shr_LWuwRh(HLX_VectorPair Luu, Word32 Rt)
Ldd16.w=shr(Luu16.w,Lv16.h)	HLX_VectorPair Q6_LWw_shr_LWwLh(HLX_VectorPair Luu, HLX_Vector Lv)
Ldd16.w=shr(Luu16.w,Rt.h)	HLX_VectorPair Q6_LWw_shr_LWwRh(HLX_VectorPair Luu, Word32 Rt)

#### Word to halfword narrowing right shift HLX word to halfword right shift instructions. Word to halfword narrowing right shift instructions | **Syntax** | **Behavior** | | --- | --- | | Ld16.h=shr(Luu16.w,Lv16.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (LuuV.l[i].w >> (LvV.uh[i] & 15)).h[0];
}
Copy to clipboard | | Ld16.h=shr(Luu16.w,Rt.uh) | for (i = 0; i < HLX_ELEMENTS; i++) {
LdV.h[i] = (LuuV.l[i].w >> (Rt.uh[0] & 15)).h[0];
}
Copy to clipboard | **Class: SHIFT (slots 2)**

Intrinsics

Word to halfword narrowing right shift intrinsics
Ld16.h=shr(Luu16.w,Lv16.uh)	HLX_Vector Q6_Lh_shr_LWwLuh(HLX_VectorPair Luu, HLX_Vector Lv)
Ld16.h=shr(Luu16.w,Rt.uh)	HLX_Vector Q6_Lh_shr_LWwRuh(HLX_VectorPair Luu, Word32 Rt)

#### Halfword bidirectional shift add HLX halfword bidirecitonal shift and add instructions. Positive shift amounts shift to the right, negative shift amounts shift to the left. Halfword bidirectional shift add instructions | **Syntax** | **Behavior** | | --- | --- | | Lx16.h+=shr(Lu16.uh,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxV.h[i]+=(LvV.h[i] <= 0) ? LuV.uh[i]<<(-LvV.h[i]) : (LuV.uh[i]>>LvV.h[i]);
}
Copy to clipboard | | Lx16.h+=shr(Lu16.uh,Rt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxV.h[i]+=(Rt <= 0) ? LuV.uh[i]<<(-Rt) : (LuV.uh[i]>>Rt);
}
Copy to clipboard | | Lx16.h+=shr(Lu16.h,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxV.h[i]+=(LvV.h[i] <= 0) ? LuV.h[i]<<(-LvV.h[i]) : (LuV.h[i]>>LvV.h[i]);
}
Copy to clipboard | | Lx16.h+=shr(Lu16.h,Rt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxV.h[i]+=(Rt <= 0) ? LuV.h[i]<<(-Rt) : (LuV.h[i]>>Rt);
}
Copy to clipboard | **Class: SHIFT (slots 2)**

Intrinsics

Halfword bidirectional shift add intrinsics
Lx16.h+=shr(Lu16.uh,Lv16.h)	HLX_Vector Q6_Lh_shracc_LuhLh(HLX_Vector Lx, HLX_Vector Lu, HLX_Vector Lv)
Lx16.h+=shr(Lu16.uh,Rt.h)	HLX_Vector Q6_Lh_shracc_LuhRh(HLX_Vector Lx, HLX_Vector Lu, Word32 Rt)
Lx16.h+=shr(Lu16.h,Lv16.h)	HLX_Vector Q6_Lh_shracc_LhLh(HLX_Vector Lx, HLX_Vector Lu, HLX_Vector Lv)
Lx16.h+=shr(Lu16.h,Rt.h)	HLX_Vector Q6_Lh_shracc_LhRh(HLX_Vector Lx, HLX_Vector Lu, Word32 Rt)

#### Word bidirectional shift add HLX word bidirecitonal shift and add instructions. Positive shift amounts shift to the right, negative shift amounts shift to the left. Word bidirectional shift add instructions | **Syntax** | **Behavior** | | --- | --- | | Lxx16.w+=shr(Luu16.uw,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w+=(LvV.h[i] <= 0) ? LuuV.l[i].uw<<(-LvV.h[i]) : (LuuV.l[i].uw>>LvV.h[i]);
}
Copy to clipboard | | Lxx16.w+=shr(Luu16.uw,Rt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w+=(Rt <= 0) ? LuuV.l[i].uw<<(-Rt) : (LuuV.l[i].uw>>Rt);
}
Copy to clipboard | | Lxx16.w+=shr(Luu16.w,Lv16.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w+=(LvV.h[i] <= 0) ? LuuV.l[i].w<<(-LvV.h[i]) : (LuuV.l[i].w>>LvV.h[i]);
}
Copy to clipboard | | Lxx16.w+=shr(Luu16.w,Rt.h) | for (i = 0; i < HLX_ELEMENTS; i++) {
LxxV.l[i].w+=(Rt <= 0) ? LuuV.l[i].w<<(-Rt) : (LuuV.l[i].w>>Rt);
}
Copy to clipboard | **Class: SHIFT (slots 2)**

Intrinsics

Word bidirectional shift add intrinsics
Lxx16.w+=shr(Luu16.uw,Lv16.h)	HLX_VectorPair Q6_LWw_shracc_LWuwLh(HLX_VectorPair Lxx, HLX_VectorPair Luu, HLX_Vector Lv)
Lxx16.w+=shr(Luu16.uw,Rt.h)	HLX_VectorPair Q6_LWw_shracc_LWuwRh(HLX_VectorPair Lxx, HLX_VectorPair Luu, Word32 Rt)
Lxx16.w+=shr(Luu16.w,Lv16.h)	HLX_VectorPair Q6_LWw_shracc_LWwLh(HLX_VectorPair Lxx, HLX_VectorPair Luu, HLX_Vector Lv)
Lxx16.w+=shr(Luu16.w,Rt.h)	HLX_VectorPair Q6_LWw_shracc_LWwRh(HLX_VectorPair Lxx, HLX_VectorPair Luu, Word32 Rt)

### STORE #### Store - new The store instructions store data from the HLX registers to VTCM. The instructions align memory accesses to 2048 bytes (~0x7FF), where HLX ignores the 11 least-significant bits (LSB) of the computed effective address (EA) and do not cause any exceptions if 11 LSB bits are non-zero. The :above and :below instructions allow for partial stores. The instructions use the 11 LSBs to specify to the hardware which bytes in the 2048-byte crouton to write. ‘:above’ signifies that HLX only writes the bytes at or above the address in Rs. For example, is Rs = #0xd9000005, HLX will only write the L register bytes at and above byte 5 (Lu16[5:2047]). ‘:below’ signifies that HLX only writes the bytes below the address in Rs. For example, is Rs = #0xd9000005, HLX will only write the L register bytes below byte 5 (Lu16[0:4]). Store - new instructions | **Syntax** | **Behavior** | | --- | --- | | mem(Rs)=Ku16.new | EA=Rs;
*(EA&HLX_MEM_ALIGN_MASK) = LNUM.new;
Copy to clipboard | | if (Pv) mem(Rs)=Ku16.new | EA=Rs;
if(Pv[0]){
*(EA&HLX_MEM_ALIGN_MASK) = LNUM.new} else {
NOP;
}
Copy to clipboard | **Class: STORE (slots 0)** Last Published: Oct 06, 2026 [Previous Topic HLX memory access](https://docs.qualcomm.com/bundle/publicresource/80-N3040-23/topics/hlx.md) [Next Topic HLX PMU events](https://docs.qualcomm.com/bundle/publicresource/80-N3040-23/topics/hlx-pmu-events.md)

Syntax	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Ld16.uh=abs(Lu16.h)	1	1	1	0	0	1	0	1	0	0	0	-	-	0	0	1	P	P	1	0	1	0	u	u	u	u	1	d	d	d	d	0
Ld16.h=abs(Lu16.h):sat	1	1	1	0	0	1	0	1	0	0	0	-	-	0	0	1	P	P	1	0	1	0	u	u	u	u	1	d	d	d	d	1

Syntax	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Ldd16.w=add(Lu16.uh,Lv16.uh)	1	1	1	0	0	1	0	1	0	0	1	v	v	v	v	-	P	P	1	0	1	0	u	u	u	u	0	d	d	d	d	0
Ldd16.w=sub(Lu16.uh,Lv16.uh)	1	1	1	0	0	1	0	1	0	0	1	v	v	v	v	-	P	P	1	0	1	0	u	u	u	u	0	d	d	d	d	1

Syntax	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Ld16.h=Lu16.h	1	1	1	0	0	1	0	1	0	0	0	-	-	-	-	-	P	P	1	1	1	0	u	u	u	u	1	d	d	d	d	0
Ldd16.w=Luu16.w	1	1	1	0	0	1	0	1	0	0	0	-	-	-	-	-	P	P	1	1	1	0	u	u	u	u	1	d	d	d	d	1

Syntax	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Ld16.h=cmp.gt(Lu16.uh, Lv16.uh)	1	1	1	0	0	1	0	1	0	0	0	v	v	v	v	-	P	P	1	0	0	0	u	u	u	u	1	d	d	d	d	0
Ld16.h=cmp.gt(Lu16.h, Lv16.h)	1	1	1	0	0	1	0	1	0	0	0	v	v	v	v	-	P	P	1	0	0	0	u	u	u	u	0	d	d	d	d	1

Syntax	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Ldd16.uw=zxt(Lu16.uh)	1	1	1	0	0	1	0	1	0	0	0	-	-	0	0	1	P	P	1	0	1	0	u	u	u	u	0	d	d	d	d	0
Ldd16.w=sxt(Lu16.h)	1	1	1	0	0	1	0	1	0	0	0	-	-	0	0	1	P	P	1	0	1	0	u	u	u	u	0	d	d	d	d	1

Syntax	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Ld16.tmp=mem(Rs)	1	0	0	1	1	0	0	0	-	-	-	s	s	s	s	s	P	P	-	1	0	-	-	-	-	0	0	0	d	d	d	d
if (Pv) Ld16.tmp=mem(Rs)	1	0	0	1	1	0	0	0	-	-	-	s	s	s	s	s	P	P	-	1	0	v	v	-	-	1	0	0	d	d	d	d

Syntax	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
mem(Rs)=Ku16.new	1	0	1	0	0	1	0	0	1	-	-	s	s	s	s	s	P	P	0	0	0	-	-	-	-	0	0	0	u	u	u	u
if (Pv) mem(Rs)=Ku16.new	1	0	1	0	0	1	0	0	1	-	-	s	s	s	s	s	P	P	0	0	0	v	v	-	-	1	0	0	u	u	u	u