# HLX PMU events

The Hexagon processor architecture defines a performance monitor unit
(PMU) to provide on target performance tracking.

The PMU allows for easy collection of aggregate performance data like
cache performance and instructions per packet. This data is valuable
for system planning and architecture purposes because it drives
performance and power statistical models.

Core PMU events are described in the Hexagon Programmer’s Reference
Manual.

The [HLX PMU events](https://docs.qualcomm.com/doc/80-N3040-23/topic/hlx-pmu-events.html#tbl-v85-hlx-processor-event-symbols) document the HLX events.

hlx v85 processor event symbols

| **Event** | **Symbol** | **Definition** | **Maskable** |
| --- | --- | --- | --- |
| 0x19a | HLXFIFO\_OCCUPIED | HLX FIFO not empty or not waiting for packet issue slot; HLX FIFO issued a packet or stalled. Total stalls = HLXFIFO\_ACC\_ORDER + HLXFIFO\_LD\_OUTSTANDING + HLXFIFO\_ST\_FULL + HLXFIFO\_VOLTAGE\_UNDER + HLXFIFO\_POWER\_OVER. Issues =  HLXFIFO\_PKT. HLXFIFO\_OCCUPIED = Total stalls + Issues. | Maskable |
| 0x19b | HLXFIFO\_WARMUP | HLX FIFO warmup stall. This warmup stall event occurs in parallel with any of the HLX FIFO stall events during the time between any EMPTY event and the next forward progress/issue event. Middle of execution stalls = Total stalls - Warmup stalls. This warmup-induced stall can be thought of as an extension of EMPTY. | Maskable |
| 0x19c | HLXFIFO\_EMPTY | HLX FIFO empty while HLX clock is on | Maskable |
| 0x19d | HLXFIFO\_WAIT | HLX FIFO stalled because packet issue slot is not available | Maskable |
| 0x19e | HLXFIFO\_LD\_OUTSTANDING | HLX FIFO stalled because load data is not ready | Maskable |
| 0x19f | HLXFIFO\_ST\_FULL | HLX FIFO stalled because store buffer entry is not available | Maskable |
| 0x1a0 | HLXFIFO\_VOLTAGE\_UNDER | HLX FIFO stalled because digital voltage model would exceed undershoot threshold | Maskable |
| 0x1a1 | HLXFIFO\_POWER\_OVER | HLX FIFO stalled because  sustained power exceeds budget | Maskable |
| 0x1a2 | HLXFIFO\_PKT | HLX FIFO issued a HLX packet | Maskable |
| 0x1ad | HLXFIFO\_ACC\_ORDER | HLX FIFO stalled because Lx/Lxx (Accumulator) register is not produced in the previous cycle. This stall can potentially be removed by ensuring the Lx/Lxx registers are written by the previous packet. Refer to  Section 3.6.1 Avoiding  Accumulator Stalls in HLX spec for details | Maskable |
| 0x1ae | HLXSLOT\_EMPTY | Number of slots without HLX instructions in a packet with at least one HLX instruction . Predicated false HLX instructions are not considered HLX instructions and will  increment the count. | Maskable |
| 0x1af | HLXSLOT\_ALU | Instruction from HLX COMMONALU group executed. Refer to  Section 3.2.1 HLX Groupings  in HLX spec | Maskable |
| 0x1b0 | HLXSLOT\_SHIFT | Instruction from HLX SHIFT, EXTENDEDALU or PAIREDALU group executed. Refer to  Section 3.2.1 HLX Groupings  in HLX spec | Maskable |
| 0x1b1 | HLXSLOT\_MPY | Instruction from HLX MULTIPLY group executed. Refer to  Section 3.2.1 HLX Groupings  in HLX spec | Maskable |
| 0x1b2 | HLXSLOT\_LD | Instruction from HLX LOAD group executed. Refer to  Section 3.2.1 HLX Groupings  in HLX spec | Maskable |
| 0x1b3 | HLXSLOT\_ST | Instruction from HLX STORE group executed. Refer to  Section 3.2.1 HLX Groupings  in HLX spec | Maskable |
| 0x1b4 | HLXREG\_LREAD | Number of HLX (L) registers consumed; where the temporary variants (.new) are not counted. Lx/Lxx registers are included in this counti. Refer to  Section 3.3.2 New Stores in HLX spec for details on temporary variant .new | Maskable |
| 0x1b5 | HLXREG\_LWRITE | Number of HLX (L) registers written; where the temporary variants (.tmp) are not counted. Refer to  Section 3.3.1 Temporary Loads in HLX spec for details on temporary variant .tmp | Maskable |
| 0x1b6 | HLX\_CORE\_VFIFO\_FULL\_STALL | Number of cycles during which a hardware thread was stalled because the LX FIFO was full. | Maskable |
| 0x1bc | HLXFIFO\_PKT\_PARTIAL | packet is being executed in multi-pumping mode: first pump has been issued, waiting for the remaining pump(s) to complete execution of the same packet | Maskable |

Last Published: Oct 06, 2026

[Previous Topic
Store - new](https://docs.qualcomm.com/bundle/publicresource/80-N3040-23/topics/hlx-instruction-set.md) [Next Topic
HLX ISA quick reference](https://docs.qualcomm.com/bundle/publicresource/80-N3040-23/topics/hlx-quick-reference.md)