# Introduction
This document describes the Qualcomm® Hexagon™ eLement-wise eXtensions (HLX) instruction set architecture. These extensions are implemented in an optional coprocessor. This document assumes that the reader is familiar with the Hexagon architecture. For a full description of the architecture, refer to the Qualcomm Hexagon Programmer’s Reference Manual.
## SIMD coprocessor
The HLX coprocessor extends the Hexagon instruction set architecture by implementing single instruction multiple data (SIMD) instructions that includes HLX registers and HLX compute elements. The HLX registers are wider than HVX registers which enables higher SIMD throughput. As a result, the baseline Hexagon architecture is extended to enable high-performance computer vision, image processing, or other workloads that can map to SIMD parallel processing.
The HLX instructions use HLX compute resources in a very long instruction word (VLIW) packet. HLX instructions can also use scalar source operands from the core.
## HLX features
HLX adds general element-wise large SIMD capability to the Hexagon ISA. HLX instructions execute on HLX registers and multiple HLX instructions execute in parallel.
### HLX registers
Each HLX register is a 2KB SIMD register. HLX partitions each register into 32-bit, 16-bit, or 8-bit elements depending on the instruction.
**Overview of HLX registers**
#### HLX 16-bit element registers
HLX has a set of 16 single registers. Single registers represent a SIMD register of 1024 16-bit elements.
**Example of 16-bit HLX registers**
#### HLX 32-bit element registers
Register pairs represent a SIMD register of 1024 32-bit elements. The register pair instructions access a consecutive pair of registers and treat the pair as a single 32-bit value. A HLX register pair using the .w/.uw syntax indicates the instruction performs on word elements. The vector register pair interleaves each halfword element into a single word element demonstrated in the image below:
**Example of 32-bit HLX registers**
HLX only allows consecutive pairs starting from 0, such as L1:0, L3:2, …, L15:14.
HLX does not allow using consecutive pairs starting from 1, such as L2:1, L4:3, etc.
#### HLX 32-bit register pair ordering
HLX only permits a 32-bit register pair with odd:even ordering. The left to right order of the register pair syntax dictates the upper halfword and the lower halfword of the word value respectively.
`L:`
In the example below, L7 contains the high halfword of the result and L6 contains the low halfword of the word result.
{
L7:6.uw = add(L1.uh,L2.uh)
}
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#### Paired halfword operations
Some HLX register pair instructions allow operations on halfword elements of the HLX register pair. A HLX register pair using the .h/.uh syntax indicates the instruction performs on halfword elements instead of word elements. For example:
{
L1:0.h=add(L3:2.h,L5:4.h)
}
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The instruction will operate on the halfword elements of each register in the pair:
for (i = 0; i < 1024; i++) {
L1.h = L3.h + L5.h;
L0.h = L2.h + L4.h;
}
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### HLX context
A HLX context consists of a HLX register file and the ability to execute instructions using this state. The HLX hardware thread dynamically attach to a HLX context and enables the thread to execute HLX instructions. The number of HLX context is implementation dependent.
When multiple hardware threads use the same HLX resource, the behavior is undefined.
The scalar core contains any number of hardware threads greater or equal to the number of HLX contexts. The operating system assigns the scalar hardware thread to the HLX context.
A hardware thread can attach to an HLX context in addition to other coprocessor contexts.
**HLX context**
### HLX exceptions
The hardware throws a PRECISE\_CAUSE\_NO\_COPROC3\_ENABLE exception (Cause code = 0x19) if a hardware thread executes a HLX instruction when the hardware has no HLX coprocessor.
### HLX memory access
The HLX memory instructions accesses memory by forming addresses using the Hexagon general registers. The memory access size of HLX memory instructions is the HLX register length. HLX restricts memory accesses to only VTCM pages.
# Memory
The Hexagon unified byte addressable memory has a single 32-bit virtual address space. All addresses go through the memory management unit (MMU) for address translation and protection. Element ordering is little-endian with the lowest byte in the least-significant position.
## Alignment
All HLX memory operations are aligned. An unaligned pointer does not cause a memory fault or exception because memory operations ignore the least-significant bits of the address.
mem(R0) = L1.new // Store to R0 & ~(0x7FF)
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## VTCM
HLX uses local memory called vector tightly coupled memory (VTCM) for all memory operations.
## Ordering
The HLX coprocessor follows total store ordering for coherency.
HLX orders memory operations by executing load operations before store operations.
When HLX and another coprocessor execute on the same hardware thread or different hardware threads, memory synchronization is handled automatically by the hardware.
# HLX instructions
HLX instructions process HLX register data in SIMD fashion. HLX performs the operation on each register lane in parallel. For example, the following instruction performs an unsigned shift operation over each halfword:
L2.uh=shr(L3.uh,R4.h)
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This instruction right shifts the unsigned halfwords in L3 by the corresponding value in R4 and stores the result in L2.
## Element types
HLX specifies the element types for instructions as:
- .uh for unsigned halfword
- .h for signed halfword
- .uw for unsigned word
- .w for signed word
Halfword element types are only associated with single registers and word element types are only associated with register pairs.
For operations with mixed element sizes, each operand with the 16-bit element size uses a single HLX register and each operand with the 32-bit element size uses a register pair. For example:
L5:4.w=add(L3:2.w,L0.uh)
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This instruction adds the unsigned word constructed from L3 and L2 with the unsigned halfword of L0 and stores 32-bit result in L5:4, where L5 receives the 16 most significant bits and L4 receives the 16 least significant bits.
## HLX packet rules
Each HLX instruction consumes a single resource. HLX provides the following resources for HLX instruction execution:
- Store
- Load
- Shift
- Multiply
Each resource is associated with a slot:
- Slot 0 - Store
- Slot 1 - Load
- Slot 2 - Shift
- Slot 3 - Multiply
An instruction packet can contain up to four instructions in addition to an end loop. The HLX instructions inside the packet must be in a slot associated with the instruction’s resource. The assembler should check and flag invalid packet combinations. When an invalid packet executes, the behavior is undefined.
HLX allows HLX instructions and other scalar or other coprocessor instructions in the same packet.
HLX instructions only use a single resources. However, HLX allows certain instruction groups to execute on different slots.
### HLX groupings
The HLX ISA defines the group associated with the HLX instruction [here](https://docs.qualcomm.com/doc/80-N3040-23/topic/hlx-instruction-set.html#hlxisa).
The table below signifies the slots the group can execute on.
Resource that each instruction group consumes
| | **Store resource** | **Load resource** | **Shift resource** | **Multiply resource** |
| --- | --- | --- | --- | --- |
| STORE | Yes | | | |
| LOAD | | Yes | | |
| SHIFT | | | Yes | |
| EXTENDEDALU | | | Yes | |
| PAIREDALU | | | Yes | |
| MULTIPLY | | | | Yes |
| COMMONALU | | | Yes | Yes |
## HLX memory instructions
HLX memory instructions move data between the HLX registers and VTCM memory. HLX memory operations only support indirect addressing. HLX only supports temporary loads and new stores.
### Temporary loads
Temporary loads allow immediate use of load data within the same packet. A temporary load instruction does not write the load data to the register and another instruction must use the data in the same packet. Hexagon assembly language expresses HLX temporary loads by appending the suffix .tmp to the destination register.
Example of temporary load instructions
{
L1.uh = max(L1.uh,L0.uh) // Use loaded data in L0 as source
L0.tmp = mem(r4) // Data loaded into a tmp
}
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### New stores
HLX store instructions only store a newly generated value from a HLX register in the same packet. Hexagon assembly language expresses HLX new stores by appending the suffix .new to the source register.
Example of new store instructions
{
L2.uh = max(L1.uh,L1.uh)
mem(R0) = L2.new // Store L2 that was generated in the current packet
}
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#### HLX zero store
If a .new store has no producer, HLX stores 2KB of zeros to the address.
Example of zero initialization store
{
mem(R0) = L2.new // Store zeros to address at R0
}
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By default, hexagon-clang will not allow this type of packet. To enable this option, use the following hexagon-clang option:
-mllvm -disable-hlx-nv-checks
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#### HLX tmp load and new store
A packet is invalid if it has a tmp load and new store without any other operations. The new store does not use the tmp loaded value.
Example of invalid packet with tmp load and new store
{
L2.tmp = mem(R0)
mem(R0) = L2.new
}
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If a new store needs a value from a tmp load, the packet must have an additional instruction that consumes the tmp load.
The following packet loads the data to a temporary register, does an add operation, then stores the new add result to memory.
Example of load tmp and new store with add operation
{
L2.tmp = mem(R0)
L1.h = add(L2.h,L2.h)
mem(R0) = L1.new
}
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## HLX shift instructions
HLX shift instructions are default right bidirectional shifts. This means that positive shift amounts shift right and negative shift amounts shift left.
If the shift amount is greater than the element bit width, the
instruction overshifts the bits and the result is 0.
Example of bidirectional shifts
{
L2 = #5
}
{
L0.uh=shr(L1.uh,L2.h) // Shifts right by 5
}
{
L2 = #-5
}
{
L0.uh=shr(L1.uh,L2.h) // Shifts left by 5
}
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## 64-bit scalar register inputs
A packet with an instruction that uses a 64-bit Rt register must not pair another instruction that uses a Rt source or immediate source. Otherwise, the 64-bit register instruction will only extract data from the lower 32 bits of the scalar register.
Example of proper 64-bit scalar register consumption
{
L0.h=lut4(L1.uh,R1:0.h) // Lut4 instruction uses 64-bit R register
}
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Examples of improper 64-bit scalar register consumption
{
L2.uh=mpy(L3.uh,R5.uh):rnd // Multiply instruction uses 16-bit scalar register
L0.h=lut4(L1.uh,R1:0.h) // 64-bit register only reads lower 32-bit value
}
{
L2.h=#5 // Splat instruction uses an immediate value
L0.h=lut4(L1.uh,R1:0.h) // 64-bit register only reads lower 32-bit value
}
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## HLX instruction latency
HLX packets execute over multiple clock cycles in a pipelined manner to issue and complete a packet on every context cycle. The contexts are time interleaved to share the hardware such that using all contexts might be required to reach peak compute bandwidth.
Latencies are implementation-defined and can change with future versions.
### Avoiding accumulator stalls
A 3 vector source using an accumulator (Lx) must be produced in the prior packet to avoid stalling. The PMU event HLXFIFO\_ACC\_ORDER indicates stalling due to not following this rule.
Example of accumulator stall with 3 vector source instructions:
{
L8.uh = shr(L0.uh,L1.h)
}
{
L3:2.uw += shr(L5:4.uw,R1.h) // Previous packet does not produces L3:2 so stalls
}
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Examples of accumulator no stall with 3 vector source instructions:
// Example 1
{
L3:2.uw = shr(L15:14.uw,L10.h)
}
{
L3:2.uw += shr(L5:4.uw,R1.h) // Previous packet produces L3:2 so no stall
}
// Example 2
{
L3:2.uw = xor(L3:2.uw,L3:2.uw) // Sets L3:2 to 0
}
{
L3:2.uw += shr(L5:4.uw,R1.h) // Previous packet produces L3:2
}
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Last Published: Oct 06, 2026
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