# ISA quick reference Hexagon™ Processor Registers | Name | Description | | --- | --- | | R0-R31 | General registers | | [Rx:Ry](Rx:Ry) | 64-bit register pair | | Rx.H-Rx.L | Most and least significant halfwords | | SP | Stack pointer (R29) | | FP | Frame pointer (R30) | | LR | Link register (R31) | | P0-P3 | Predicate registers | | LC0-LC1 | Loop count | | SA0-SA1 | Loop start address | | M0-M1 | Modify registers | | CS0-CS1 | Circular start registers | | USR | User status register | | UGP | User general pointer | | GP | Global pointer | | PC | Program counter | | UPCYCLELO | Cycle count register (low) | | UPCYCLEHI | Cycle count register (high) | | FRAMELIMIT | Frame limit register | | FRAMEKEY | Frame key register | | PKTCOUNTLO | Packet count register (low) | | PKTCOUNTHI | Packet count register (high) | | UTIMERLO | Qtimer register (low) | | UTIMERHI | Qtimer register (high) | Register Operands | Symbol | Description | | --- | --- | | Rs, Rt, Ru | 32-bit source | | Rd | 32-bit destination | | Rx | 32-bit source/destination | | Rss, Rtt, Ruu | 64-bit source | | Rdd | 64-bit destination | | Rxx | 64-bit source/destination | Constant Operands | Symbol | Description | | --- | --- | | #uN | N-bit unsigned value | | #sN | N-bit signed value | | #mN | Same as #sN, but minimum value is -(2(N-1)-1) | | #rN | N-bit PC-relative value | | #xN:M | Bit field N:M in N-bit value | | ## | Same as #, but associated value is 32 bits | Instruction Packets | Slot 0 | Slot 1 | Slot 2 | Slot 3 | | --- | --- | --- | --- | | LD | | | | | ST | | | | | ALU32 | | | | | MEMOP | | | | | NV | | | | | SYSTEM | | | | | LD | | | | | ST | | | | | ALU32 | | | | | XTYPE | | | | | ALU32 | | | | | J | | | | | JR | | | | | XTYPE | | | | | ALU32 | | | | | J | | | | | CR | | | | ## Quick reference ISA ### [Add](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-add) - Rd=add(Rs,Rt) - Rd=add(Rs,Rt):sat - Rd=add(Rs,#s16) - Rx=add(Rx,#s7) - Rd=add(r29,#u6:2) - Rd=add(Rs,#1) - Rd=add(Rs,#-1) - Rx=add(Rx,Rs) ### [Logical operations](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-logical-operations) - Rd=and(Rs,Rt) - Rd=or(Rs,Rt) - Rd=xor(Rs,Rt) - Rd=not(Rs) - Rd=and(Rt,~Rs) - Rd=or(Rt,~Rs) - Rd=and(Rs,#s10) - Rd=or(Rs,#s10) - Rd=and(Rs,#255) - Rd=and(Rs,#1) ### [Negate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-negate) - Rd=neg(Rs) ### [Nop](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-nop) - nop ### [Subtract](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-subtract) - Rd=sub(Rt,Rs) - Rd=sub(Rt,Rs):sat - Rd=sub(#s10,Rs) ### [Sign extend](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-sign-extend) - Rd=sxtb(Rs) - Rd=sxth(Rs) - Rd=sxtb(Rs) - Rd=sxth(Rs) ### [Transfer immediate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-transfer-immediate) - Rd=#s16 - Rdd=#s8 - Rx.L=#u16 - Rx.H=#u16 - Rd=#u6 - Rd=#-1 ### [Transfer register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-transfer-register) - Rd=Rs - Rdd=Rss - Rd=Rs ### [Vector add halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-vector-add-halfwords) - Rd=vaddh(Rs,Rt) - Rd=vaddh(Rs,Rt):sat - Rd=vadduh(Rs,Rt):sat ### [Vector average halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-vector-average-halfwords) - Rd=vavgh(Rs,Rt) - Rd=vavgh(Rs,Rt):rnd - Rd=vnavgh(Rt,Rs) ### [Vector subtract halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-vector-subtract-halfwords) - Rd=vsubh(Rt,Rs) - Rd=vsubh(Rt,Rs):sat - Rd=vsubuh(Rt,Rs):sat ### [Zero extend](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-alu-zero-extend) - Rd=zxtb(Rs) - Rd=zxth(Rs) - Rd=zxth(Rs) ### [Combine words into doubleword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-perm-combine-words-into-doubleword) - Rdd=combine(Rs,Rt) - Rdd=combine(Rs,#s8) - Rdd=combine(#s8,Rs) - Rdd=combine(#s8,#S8) - Rdd=combine(#s8,#U6) - Rd=combine(Rt.H,Rs.H) - Rd=combine(Rt.H,Rs.L) - Rd=combine(Rt.L,Rs.H) - Rd=combine(Rt.L,Rs.L) - Rdd=combine(#0,Rs) - Rdd=combine(Rs,#0) - Rdd=combine(#0,#u2) - Rdd=combine(#1,#u2) - Rdd=combine(#2,#u2) - Rdd=combine(#3,#u2) ### [Mux](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-perm-mux) - Rd=mux(Pu,Rs,Rt) - Rd=mux(Pu,#s8,#S8) - Rd=mux(Pu,Rs,#s8) - Rd=mux(Pu,#s8,Rs) ### [Shift word by 16](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-perm-shift-word-by-16) - Rd=aslh(Rs) - Rd=asrh(Rs) ### [Pack high and low halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-perm-pack-high-and-low-halfwords) - Rdd=packhl(Rs,Rt) - Rdd=packhl(Rs,Rt):deprecated ### [Conditional add](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-pred-conditional-add) - if (Pu) Rd=add(Rs,Rt) - if (!Pu) Rd=add(Rs,Rt) - if (Pu.new) Rd=add(Rs,Rt) - if (!Pu.new) Rd=add(Rs,Rt) - if (Pu) Rd=add(Rs,#s8) - if (!Pu) Rd=add(Rs,#s8) - if (Pu.new) Rd=add(Rs,#s8) - if (!Pu.new) Rd=add(Rs,#s8) ### [Conditional shift halfword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-pred-conditional-shift-halfword) - if (Pu) Rd=aslh(Rs) - if (!Pu) Rd=aslh(Rs) - if (Pu.new) Rd=aslh(Rs) - if (!Pu.new) Rd=aslh(Rs) - if (Pu) Rd=asrh(Rs) - if (!Pu) Rd=asrh(Rs) - if (Pu.new) Rd=asrh(Rs) - if (!Pu.new) Rd=asrh(Rs) ### [Conditional combine](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-pred-conditional-combine) - if (Pu.new) Rdd=combine(Rs,Rt) - if (!Pu.new) Rdd=combine(Rs,Rt) - if (Pu) Rdd=combine(Rs,Rt) - if (!Pu) Rdd=combine(Rs,Rt) ### [Conditional logical operations](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-pred-conditional-logical-operations) - if (Pu) Rd=xor(Rs,Rt) - if (!Pu) Rd=xor(Rs,Rt) - if (Pu.new) Rd=xor(Rs,Rt) - if (!Pu.new) Rd=xor(Rs,Rt) - if (Pu) Rd=and(Rs,Rt) - if (!Pu) Rd=and(Rs,Rt) - if (Pu.new) Rd=and(Rs,Rt) - if (!Pu.new) Rd=and(Rs,Rt) - if (Pu) Rd=or(Rs,Rt) - if (!Pu) Rd=or(Rs,Rt) - if (Pu.new) Rd=or(Rs,Rt) - if (!Pu.new) Rd=or(Rs,Rt) ### [Conditional subtract](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-pred-conditional-subtract) - if (Pu) Rd=sub(Rt,Rs) - if (!Pu) Rd=sub(Rt,Rs) - if (Pu.new) Rd=sub(Rt,Rs) - if (!Pu.new) Rd=sub(Rt,Rs) ### [Conditional sign extend](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-pred-conditional-sign-extend) - if (Pu) Rd=sxtb(Rs) - if (!Pu) Rd=sxtb(Rs) - if (Pu.new) Rd=sxtb(Rs) - if (!Pu.new) Rd=sxtb(Rs) - if (Pu) Rd=sxth(Rs) - if (!Pu) Rd=sxth(Rs) - if (Pu.new) Rd=sxth(Rs) - if (!Pu.new) Rd=sxth(Rs) ### [Conditional transfer](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-pred-conditional-transfer) - if (Pu) Rd=Rs - if (!Pu) Rd=Rs - if (Pu.new) Rd=Rs - if (!Pu.new) Rd=Rs - if (Pu) Rdd=Rss - if (!Pu) Rdd=Rss - if (Pu.new) Rdd=Rss - if (!Pu.new) Rdd=Rss - if (Pu.new) Rd=#s12 - if (!Pu.new) Rd=#s12 - if (Pu) Rd=#s12 - if (!Pu) Rd=#s12 - if (p0.new) Rd=#0 - if (!p0.new) Rd=#0 - if (p0) Rd=#0 - if (!p0) Rd=#0 ### [Conditional zero extend](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-pred-conditional-zero-extend) - if (Pu) Rd=zxtb(Rs) - if (!Pu) Rd=zxtb(Rs) - if (Pu.new) Rd=zxtb(Rs) - if (!Pu.new) Rd=zxtb(Rs) - if (Pu) Rd=zxth(Rs) - if (!Pu) Rd=zxth(Rs) - if (Pu.new) Rd=zxth(Rs) - if (!Pu.new) Rd=zxth(Rs) ### [Compare](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-pred-compare) - Pd=cmp.eq(Rs,Rt) - Pd=cmp.gt(Rs,Rt) - Pd=cmp.gtu(Rs,Rt) - Pd=cmp.eq(Rs,#s10) - Pd=cmp.gt(Rs,#s10) - Pd=cmp.gtu(Rs,#u9) - Pd=cmp.ge(Rs,#s8) - Pd=cmp.geu(Rs,#u8) - Pd=cmp.lt(Rs,Rt) - Pd=cmp.ltu(Rs,Rt) - Pd=!cmp.eq(Rs,#s10) - Pd=!cmp.gt(Rs,#s10) - Pd=!cmp.gtu(Rs,#u9) - Pd=!cmp.eq(Rs,Rt) - Pd=!cmp.gt(Rs,Rt) - Pd=!cmp.gtu(Rs,Rt) - p0=cmp.eq(Rs,#u2) ### [Compare to general register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-alu32-pred-compare-to-general-register) - Rd=cmp.eq(Rs,#s8) - Rd=!cmp.eq(Rs,#s8) - Rd=cmp.eq(Rs,Rt) - Rd=!cmp.eq(Rs,Rt) #### [Call subroutine from register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cfi-call-subroutine-from-register) - callr\_rb Rs - if (Pu) callr\_rb Rs - if (!Pu) callr\_rb Rs #### [Hinted call subroutine from register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cfi-hinted-call-subroutine-from-register) - callrh\_rb Rs #### [Jump to address from register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cfi-jump-to-address-from-register) - jumpr\_rb Rs - if (Pu) jumpr\_rb:nt Rs - if (!Pu) jumpr\_rb:nt Rs - if (Pu) jumpr\_rb:t Rs - if (!Pu) jumpr\_rb:t Rs - if (Pu.new) jumpr\_rb:nt Rs - if (!Pu.new) jumpr\_rb:nt Rs - if (Pu.new) jumpr\_rb:t Rs - if (!Pu.new) jumpr\_rb:t Rs #### [Hinted jump to address from register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cfi-hinted-jump-to-address-from-register) - jumprh\_rb Rs #### [Nop](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cfi-nop) - nop\_rb #### [Restricted Allocate stack frame](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cfi-restricted-allocate-stack-frame) - allocframe\_rb(Rx,#u11:3):raw - allocframe\_rb(#u11:3) - allocframe\_rb(#u5:3) #### [End loop instructions](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cr-end-loop-instructions) - endloop01 - endloop0 - endloop1 #### [Corner detection acceleration](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cr-corner-detection-acceleration) - Pd=fastcorner9(Ps,Pt) - Pd=!fastcorner9(Ps,Pt) #### [Logical reductions on predicates](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cr-logical-reductions-on-predicates) - Pd=any8(Ps) - Pd=all8(Ps) #### [Looping instructions](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cr-looping-instructions) - loop0(#r7:2,Rs) - loop1(#r7:2,Rs) - loop0(#r7:2,#U10) - loop1(#r7:2,#U10) #### [Add to PC](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cr-add-to-pc) - Rd=add(pc,#u6) #### [Pipelined loop instructions](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cr-pipelined-loop-instructions) - p3=sp1loop0(#r7:2,Rs) - p3=sp1loop0(#r7:2,#U10) - p3=sp2loop0(#r7:2,Rs) - p3=sp2loop0(#r7:2,#U10) - p3=sp3loop0(#r7:2,Rs) - p3=sp3loop0(#r7:2,#U10) #### [Logical operations on predicates](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cr-logical-operations-on-predicates) - Pd=and(Pt,Ps) - Pd=or(Pt,Ps) - Pd=xor(Ps,Pt) - Pd=and(Pt,!Ps) - Pd=not(Ps) - Pd=or(Pt,!Ps) - Pd=and(Ps,and(Pt,Pu)) - Pd=and(Ps,or(Pt,Pu)) - Pd=or(Ps,and(Pt,Pu)) - Pd=or(Ps,or(Pt,Pu)) - Pd=and(Ps,and(Pt,!Pu)) - Pd=and(Ps,or(Pt,!Pu)) - Pd=or(Ps,and(Pt,!Pu)) - Pd=or(Ps,or(Pt,!Pu)) - Pd=Ps #### [User control register transfer](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-cr-user-control-register-transfer) - Rd=Cs - Cd=Rs - Rdd=Css - Cdd=Rss #### [Call subroutine from register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-jr-call-subroutine-from-register) - callr Rs - if (Pu) callr Rs - if (!Pu) callr Rs #### [Hinted call subroutine from register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-jr-hinted-call-subroutine-from-register) - callrh Rs #### [Hint an indirect jump address](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-jr-hint-an-indirect-jump-address) - hintjr(Rs) #### [Jump to address from register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-jr-jump-to-address-from-register) - jumpr Rs - if (Pu) jumpr:nt Rs - if (!Pu) jumpr:nt Rs - if (Pu) jumpr:t Rs - if (!Pu) jumpr:t Rs - if (Pu) jumpr Rs - if (!Pu) jumpr Rs - if (Pu.new) jumpr:nt Rs - if (!Pu.new) jumpr:nt Rs - if (Pu.new) jumpr:t Rs - if (!Pu.new) jumpr:t Rs - jumpr r31 - if (p0) jumpr r31 - if (!p0) jumpr r31 - if (p0.new) jumpr:nt r31 - if (!p0.new) jumpr:nt r31 #### [Hinted jump to address from register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-jr-hinted-jump-to-address-from-register) - jumprh Rs #### [Call subroutine](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-j-call-subroutine) - call #r22:2 - if (Pu) call #r15:2 - if (!Pu) call #r15:2 #### [Compare and jump](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-j-compare-and-jump) - p0=cmp.eq(Rs,#U5); if (p0.new) jump:nt #r9:2 - p0=cmp.eq(Rs,#U5); if (!p0.new) jump:nt #r9:2 - p0=cmp.eq(Rs,#U5); if (p0.new) jump:t #r9:2 - p0=cmp.eq(Rs,#U5); if (!p0.new) jump:t #r9:2 - p1=cmp.eq(Rs,#U5); if (p1.new) jump:nt #r9:2 - p1=cmp.eq(Rs,#U5); if (!p1.new) jump:nt #r9:2 - p1=cmp.eq(Rs,#U5); if (p1.new) jump:t #r9:2 - p1=cmp.eq(Rs,#U5); if (!p1.new) jump:t #r9:2 - p0=cmp.gt(Rs,#U5); if (p0.new) jump:nt #r9:2 - p0=cmp.gt(Rs,#U5); if (!p0.new) jump:nt #r9:2 - p0=cmp.gt(Rs,#U5); if (p0.new) jump:t #r9:2 - p0=cmp.gt(Rs,#U5); if (!p0.new) jump:t #r9:2 - p1=cmp.gt(Rs,#U5); if (p1.new) jump:nt #r9:2 - p1=cmp.gt(Rs,#U5); if (!p1.new) jump:nt #r9:2 - p1=cmp.gt(Rs,#U5); if (p1.new) jump:t #r9:2 - p1=cmp.gt(Rs,#U5); if (!p1.new) jump:t #r9:2 - p0=cmp.gtu(Rs,#U5); if (p0.new) jump:nt #r9:2 - p0=cmp.gtu(Rs,#U5); if (!p0.new) jump:nt #r9:2 - p0=cmp.gtu(Rs,#U5); if (p0.new) jump:t #r9:2 - p0=cmp.gtu(Rs,#U5); if (!p0.new) jump:t #r9:2 - p1=cmp.gtu(Rs,#U5); if (p1.new) jump:nt #r9:2 - p1=cmp.gtu(Rs,#U5); if (!p1.new) jump:nt #r9:2 - p1=cmp.gtu(Rs,#U5); if (p1.new) jump:t #r9:2 - p1=cmp.gtu(Rs,#U5); if (!p1.new) jump:t #r9:2 - p0=cmp.eq(Rs,#-1); if (p0.new) jump:nt #r9:2 - p0=cmp.eq(Rs,#-1); if (!p0.new) jump:nt #r9:2 - p0=cmp.eq(Rs,#-1); if (p0.new) jump:t #r9:2 - p0=cmp.eq(Rs,#-1); if (!p0.new) jump:t #r9:2 - p1=cmp.eq(Rs,#-1); if (p1.new) jump:nt #r9:2 - p1=cmp.eq(Rs,#-1); if (!p1.new) jump:nt #r9:2 - p1=cmp.eq(Rs,#-1); if (p1.new) jump:t #r9:2 - p1=cmp.eq(Rs,#-1); if (!p1.new) jump:t #r9:2 - p0=cmp.gt(Rs,#-1); if (p0.new) jump:nt #r9:2 - p0=cmp.gt(Rs,#-1); if (!p0.new) jump:nt #r9:2 - p0=cmp.gt(Rs,#-1); if (p0.new) jump:t #r9:2 - p0=cmp.gt(Rs,#-1); if (!p0.new) jump:t #r9:2 - p1=cmp.gt(Rs,#-1); if (p1.new) jump:nt #r9:2 - p1=cmp.gt(Rs,#-1); if (!p1.new) jump:nt #r9:2 - p1=cmp.gt(Rs,#-1); if (p1.new) jump:t #r9:2 - p1=cmp.gt(Rs,#-1); if (!p1.new) jump:t #r9:2 - p0=tstbit(Rs,#0); if (p0.new) jump:nt #r9:2 - p0=tstbit(Rs,#0); if (!p0.new) jump:nt #r9:2 - p0=tstbit(Rs,#0); if (p0.new) jump:t #r9:2 - p0=tstbit(Rs,#0); if (!p0.new) jump:t #r9:2 - p1=tstbit(Rs,#0); if (p1.new) jump:nt #r9:2 - p1=tstbit(Rs,#0); if (!p1.new) jump:nt #r9:2 - p1=tstbit(Rs,#0); if (p1.new) jump:t #r9:2 - p1=tstbit(Rs,#0); if (!p1.new) jump:t #r9:2 - p0=cmp.eq(Rs,Rt); if (p0.new) jump:nt #r9:2 - p0=cmp.eq(Rs,Rt); if (!p0.new) jump:nt #r9:2 - p0=cmp.eq(Rs,Rt); if (p0.new) jump:t #r9:2 - p0=cmp.eq(Rs,Rt); if (!p0.new) jump:t #r9:2 - p1=cmp.eq(Rs,Rt); if (p1.new) jump:nt #r9:2 - p1=cmp.eq(Rs,Rt); if (!p1.new) jump:nt #r9:2 - p1=cmp.eq(Rs,Rt); if (p1.new) jump:t #r9:2 - p1=cmp.eq(Rs,Rt); if (!p1.new) jump:t #r9:2 - p0=cmp.gt(Rs,Rt); if (p0.new) jump:nt #r9:2 - p0=cmp.gt(Rs,Rt); if (!p0.new) jump:nt #r9:2 - p0=cmp.gt(Rs,Rt); if (p0.new) jump:t #r9:2 - p0=cmp.gt(Rs,Rt); if (!p0.new) jump:t #r9:2 - p1=cmp.gt(Rs,Rt); if (p1.new) jump:nt #r9:2 - p1=cmp.gt(Rs,Rt); if (!p1.new) jump:nt #r9:2 - p1=cmp.gt(Rs,Rt); if (p1.new) jump:t #r9:2 - p1=cmp.gt(Rs,Rt); if (!p1.new) jump:t #r9:2 - p0=cmp.gtu(Rs,Rt); if (p0.new) jump:nt #r9:2 - p0=cmp.gtu(Rs,Rt); if (!p0.new) jump:nt #r9:2 - p0=cmp.gtu(Rs,Rt); if (p0.new) jump:t #r9:2 - p0=cmp.gtu(Rs,Rt); if (!p0.new) jump:t #r9:2 - p1=cmp.gtu(Rs,Rt); if (p1.new) jump:nt #r9:2 - p1=cmp.gtu(Rs,Rt); if (!p1.new) jump:nt #r9:2 - p1=cmp.gtu(Rs,Rt); if (p1.new) jump:t #r9:2 - p1=cmp.gtu(Rs,Rt); if (!p1.new) jump:t #r9:2 #### [Jump to address](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-j-jump-to-address) - jump #r22:2 - if (Pu) jump:nt #r15:2 - if (!Pu) jump:nt #r15:2 - if (Pu) jump:t #r15:2 - if (!Pu) jump:t #r15:2 - if (Pu) jump #r15:2 - if (!Pu) jump #r15:2 #### [Jump to address conditioned on new predicate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-j-jump-to-address-conditioned-on-new-predicate) - if (Pu.new) jump:nt #r15:2 - if (!Pu.new) jump:nt #r15:2 - if (Pu.new) jump:t #r15:2 - if (!Pu.new) jump:t #r15:2 #### [Jump to address conditioned on register value](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-j-jump-to-address-conditioned-on-register-value) - if (Rs!=#0) jump:nt #r13:2 - if (Rs==#0) jump:nt #r13:2 - if (Rs!=#0) jump:t #r13:2 - if (Rs==#0) jump:t #r13:2 - if (Rs>=#0) jump:nt #r13:2 - if (Rs>=#0) jump:t #r13:2 - if (Rs<=#0) jump:nt #r13:2 - if (Rs<=#0) jump:t #r13:2 #### [Transfer and jump](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-j-transfer-and-jump) - Rd=#U6 ; jump #r9:2 - Rd=Rs ; jump #r9:2 #### [Load doubleword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-doubleword) - Rdd=memd(Rs+#s11:3) - Rdd=memd(Rt<<#u2+#U6) - Rdd=memd(Re=#U6) - Rdd=memd(Rx++Mu) - Rdd=memd(Rx++Mu:brev) - Rdd=memd(Rx++#s4:3) - Rdd=memd(Rx++#s4:3:circ(Mu)) - Rdd=memd(Rx++I:circ(Mu)) - Rdd=memd(Rs) - Rdd=memd(Rs+Rt<<#u2) - Rdd=memd(gp+#u16:3) - Rdd=memd(r29+#u5:3) #### [Load-acquire doubleword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-acquire-doubleword) - Rdd=memd\_aq(Rs) #### [Load doubleword conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-doubleword-conditionally) - if (Pt) Rdd=memd(Rs+#u6:3) - if (Pt) Rdd=memd(Rx++#s4:3) - if (!Pt) Rdd=memd(Rs+#u6:3) - if (!Pt) Rdd=memd(Rx++#s4:3) - if (Pt.new) Rdd=memd(Rs+#u6:3) - if (!Pt.new) Rdd=memd(Rs+#u6:3) - if (Pv) Rdd=memd(Rs+Rt<<#u2) - if (!Pv) Rdd=memd(Rs+Rt<<#u2) - if (Pv.new) Rdd=memd(Rs+Rt<<#u2) - if (!Pv.new) Rdd=memd(Rs+Rt<<#u2) - if (Pt.new) Rdd=memd(Rx++#s4:3) - if (!Pt.new) Rdd=memd(Rx++#s4:3) - if (Pt) Rdd=memd(#u6) - if (!Pt) Rdd=memd(#u6) - if (Pt.new) Rdd=memd(#u6) - if (!Pt.new) Rdd=memd(#u6) - if (Pt) Rdd=memd(Rs) - if (!Pt) Rdd=memd(Rs) - if (Pt.new) Rdd=memd(Rs) - if (!Pt.new) Rdd=memd(Rs) #### [Load byte](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-byte) - Rd=memb(Rs+#s11:0) - Rd=memb(Rt<<#u2+#U6) - Rd=memb(Re=#U6) - Rd=memb(Rx++Mu) - Rd=memb(Rx++Mu:brev) - Rd=memb(Rx++#s4:0) - Rd=memb(Rx++#s4:0:circ(Mu)) - Rd=memb(Rx++I:circ(Mu)) - Rd=memb(Rs) - Rd=memb(Rs+Rt<<#u2) - Rd=memb(gp+#u16:0) - Rd=memb(Rs+#u3:0) #### [Load byte conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-byte-conditionally) - if (Pt) Rd=memb(Rs+#u6:0) - if (Pt) Rd=memb(Rx++#s4:0) - if (!Pt) Rd=memb(Rs+#u6:0) - if (!Pt) Rd=memb(Rx++#s4:0) - if (Pt.new) Rd=memb(Rs+#u6:0) - if (!Pt.new) Rd=memb(Rs+#u6:0) - if (Pv) Rd=memb(Rs+Rt<<#u2) - if (!Pv) Rd=memb(Rs+Rt<<#u2) - if (Pv.new) Rd=memb(Rs+Rt<<#u2) - if (!Pv.new) Rd=memb(Rs+Rt<<#u2) - if (Pt.new) Rd=memb(Rx++#s4:0) - if (!Pt.new) Rd=memb(Rx++#s4:0) - if (Pt) Rd=memb(#u6) - if (!Pt) Rd=memb(#u6) - if (Pt.new) Rd=memb(#u6) - if (!Pt.new) Rd=memb(#u6) - if (Pt) Rd=memb(Rs) - if (!Pt) Rd=memb(Rs) - if (Pt.new) Rd=memb(Rs) - if (!Pt.new) Rd=memb(Rs) #### [Load byte into shifted vector](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-byte-into-shifted-vector) - Ryy=memb\_fifo(Rs+#s11:0) - Ryy=memb\_fifo(Rt<<#u2+#U6) - Ryy=memb\_fifo(Re=#U6) - Ryy=memb\_fifo(Rx++Mu) - Ryy=memb\_fifo(Rx++Mu:brev) - Ryy=memb\_fifo(Rx++#s4:0) - Ryy=memb\_fifo(Rx++#s4:0:circ(Mu)) - Ryy=memb\_fifo(Rx++I:circ(Mu)) - Ryy=memb\_fifo(Rs) #### [Load half into shifted vector](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-half-into-shifted-vector) - Ryy=memh\_fifo(Rs+#s11:1) - Ryy=memh\_fifo(Rt<<#u2+#U6) - Ryy=memh\_fifo(Re=#U6) - Ryy=memh\_fifo(Rx++Mu) - Ryy=memh\_fifo(Rx++Mu:brev) - Ryy=memh\_fifo(Rx++#s4:1) - Ryy=memh\_fifo(Rx++#s4:1:circ(Mu)) - Ryy=memh\_fifo(Rx++I:circ(Mu)) - Ryy=memh\_fifo(Rs) #### [Load halfword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-halfword) - Rd=memh(Rs+#s11:1) - Rd=memh(Rt<<#u2+#U6) - Rd=memh(Re=#U6) - Rd=memh(Rx++Mu) - Rd=memh(Rx++Mu:brev) - Rd=memh(Rx++#s4:1) - Rd=memh(Rx++#s4:1:circ(Mu)) - Rd=memh(Rx++I:circ(Mu)) - Rd=memh(Rs) - Rd=memh(Rs+Rt<<#u2) - Rd=memh(gp+#u16:1) - Rd=memh(Rs+#u3:1) #### [Load halfword conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-halfword-conditionally) - if (Pt) Rd=memh(Rs+#u6:1) - if (Pt) Rd=memh(Rx++#s4:1) - if (!Pt) Rd=memh(Rs+#u6:1) - if (!Pt) Rd=memh(Rx++#s4:1) - if (Pt.new) Rd=memh(Rs+#u6:1) - if (!Pt.new) Rd=memh(Rs+#u6:1) - if (Pv) Rd=memh(Rs+Rt<<#u2) - if (!Pv) Rd=memh(Rs+Rt<<#u2) - if (Pv.new) Rd=memh(Rs+Rt<<#u2) - if (!Pv.new) Rd=memh(Rs+Rt<<#u2) - if (Pt.new) Rd=memh(Rx++#s4:1) - if (!Pt.new) Rd=memh(Rx++#s4:1) - if (Pt) Rd=memh(#u6) - if (!Pt) Rd=memh(#u6) - if (Pt.new) Rd=memh(#u6) - if (!Pt.new) Rd=memh(#u6) - if (Pt) Rd=memh(Rs) - if (!Pt) Rd=memh(Rs) - if (Pt.new) Rd=memh(Rs) - if (!Pt.new) Rd=memh(Rs) #### [Load unsigned byte](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-unsigned-byte) - Rd=memub(Rs+#s11:0) - Rd=memub(Rt<<#u2+#U6) - Rd=memub(Re=#U6) - Rd=memub(Rx++Mu) - Rd=memub(Rx++Mu:brev) - Rd=memub(Rx++#s4:0) - Rd=memub(Rx++#s4:0:circ(Mu)) - Rd=memub(Rx++I:circ(Mu)) - Rd=memub(Rs) - Rd=memub(Rs+Rt<<#u2) - Rd=memub(gp+#u16:0) - Rd=memub(Rs+#u4:0) #### [Load unsigned byte conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-unsigned-byte-conditionally) - if (Pt) Rd=memub(Rs+#u6:0) - if (Pt) Rd=memub(Rx++#s4:0) - if (!Pt) Rd=memub(Rs+#u6:0) - if (!Pt) Rd=memub(Rx++#s4:0) - if (Pt.new) Rd=memub(Rs+#u6:0) - if (!Pt.new) Rd=memub(Rs+#u6:0) - if (Pv) Rd=memub(Rs+Rt<<#u2) - if (!Pv) Rd=memub(Rs+Rt<<#u2) - if (Pv.new) Rd=memub(Rs+Rt<<#u2) - if (!Pv.new) Rd=memub(Rs+Rt<<#u2) - if (Pt.new) Rd=memub(Rx++#s4:0) - if (!Pt.new) Rd=memub(Rx++#s4:0) - if (Pt) Rd=memub(#u6) - if (!Pt) Rd=memub(#u6) - if (Pt.new) Rd=memub(#u6) - if (!Pt.new) Rd=memub(#u6) - if (Pt) Rd=memub(Rs) - if (!Pt) Rd=memub(Rs) - if (Pt.new) Rd=memub(Rs) - if (!Pt.new) Rd=memub(Rs) #### [Load unsigned halfword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-unsigned-halfword) - Rd=memuh(Rs+#s11:1) - Rd=memuh(Rt<<#u2+#U6) - Rd=memuh(Re=#U6) - Rd=memuh(Rx++Mu) - Rd=memuh(Rx++Mu:brev) - Rd=memuh(Rx++#s4:1) - Rd=memuh(Rx++#s4:1:circ(Mu)) - Rd=memuh(Rx++I:circ(Mu)) - Rd=memuh(Rs) - Rd=memuh(Rs+Rt<<#u2) - Rd=memuh(gp+#u16:1) - Rd=memuh(Rs+#u3:1) #### [Load unsigned halfword conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-unsigned-halfword-conditionally) - if (Pt) Rd=memuh(Rs+#u6:1) - if (Pt) Rd=memuh(Rx++#s4:1) - if (!Pt) Rd=memuh(Rs+#u6:1) - if (!Pt) Rd=memuh(Rx++#s4:1) - if (Pt.new) Rd=memuh(Rs+#u6:1) - if (!Pt.new) Rd=memuh(Rs+#u6:1) - if (Pv) Rd=memuh(Rs+Rt<<#u2) - if (!Pv) Rd=memuh(Rs+Rt<<#u2) - if (Pv.new) Rd=memuh(Rs+Rt<<#u2) - if (!Pv.new) Rd=memuh(Rs+Rt<<#u2) - if (Pt.new) Rd=memuh(Rx++#s4:1) - if (!Pt.new) Rd=memuh(Rx++#s4:1) - if (Pt) Rd=memuh(#u6) - if (!Pt) Rd=memuh(#u6) - if (Pt.new) Rd=memuh(#u6) - if (!Pt.new) Rd=memuh(#u6) - if (Pt) Rd=memuh(Rs) - if (!Pt) Rd=memuh(Rs) - if (Pt.new) Rd=memuh(Rs) - if (!Pt.new) Rd=memuh(Rs) #### [Load word](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-word) - Rd=memw(Rs+#s11:2) - Rd=memw(Rt<<#u2+#U6) - Rd=memw(Re=#U6) - Rd=memw(Rx++Mu) - Rd=memw(Rx++Mu:brev) - Rd=memw(Rx++#s4:2) - Rd=memw(Rx++#s4:2:circ(Mu)) - Rd=memw(Rx++I:circ(Mu)) - Rd=memw(Rs) - Rd=memw(Rs+Rt<<#u2) - Rd=memw(gp+#u16:2) - Rd=memw(Rs+#u4:2) - Rd=memw(r29+#u5:2) #### [Load-acquire word](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-acquire-word) - Rd=memw\_aq(Rs) #### [Load word conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-word-conditionally) - if (Pt) Rd=memw(Rs+#u6:2) - if (Pt) Rd=memw(Rx++#s4:2) - if (!Pt) Rd=memw(Rs+#u6:2) - if (!Pt) Rd=memw(Rx++#s4:2) - if (Pt.new) Rd=memw(Rs+#u6:2) - if (!Pt.new) Rd=memw(Rs+#u6:2) - if (Pv) Rd=memw(Rs+Rt<<#u2) - if (!Pv) Rd=memw(Rs+Rt<<#u2) - if (Pv.new) Rd=memw(Rs+Rt<<#u2) - if (!Pv.new) Rd=memw(Rs+Rt<<#u2) - if (Pt.new) Rd=memw(Rx++#s4:2) - if (!Pt.new) Rd=memw(Rx++#s4:2) - if (Pt) Rd=memw(#u6) - if (!Pt) Rd=memw(#u6) - if (Pt.new) Rd=memw(#u6) - if (!Pt.new) Rd=memw(#u6) - if (Pt) Rd=memw(Rs) - if (!Pt) Rd=memw(Rs) - if (Pt.new) Rd=memw(Rs) - if (!Pt.new) Rd=memw(Rs) #### [Deallocate stack frame](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-deallocate-stack-frame) - Rdd=deallocframe(Rs):raw - deallocframe - deallocframe #### [Deallocate frame and return](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-deallocate-frame-and-return) - Rdd=dealloc\_return(Rs):raw - dealloc\_return - if (Pv) Rdd=dealloc\_return(Rs):raw - if (!Pv) Rdd=dealloc\_return(Rs):raw - if (Pv) dealloc\_return - if (!Pv) dealloc\_return - if (Pv.new) Rdd=dealloc\_return(Rs):t:raw - if (!Pv.new) Rdd=dealloc\_return(Rs):t:raw - if (Pv.new) dealloc\_return:t - if (!Pv.new) dealloc\_return:t - if (Pv.new) Rdd=dealloc\_return(Rs):nt:raw - if (!Pv.new) Rdd=dealloc\_return(Rs):nt:raw - if (Pv.new) dealloc\_return:nt - if (!Pv.new) dealloc\_return:nt - dealloc\_return - if (p0) dealloc\_return - if (!p0) dealloc\_return - if (p0.new) dealloc\_return:nt - if (!p0.new) dealloc\_return:nt #### [Load and unpack bytes to halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-ld-load-and-unpack-bytes-to-halfwords) - Rd=memubh(Rs+#s11:1) - Rd=memubh(Rt<<#u2+#U6) - Rd=memubh(Re=#U6) - Rd=memubh(Rx++Mu) - Rd=memubh(Rx++Mu:brev) - Rd=memubh(Rx++#s4:1) - Rd=memubh(Rx++#s4:1:circ(Mu)) - Rd=memubh(Rx++I:circ(Mu)) - Rd=memubh(Rs) - Rdd=memubh(Rs+#s11:2) - Rdd=memubh(Rt<<#u2+#U6) - Rdd=memubh(Re=#U6) - Rdd=memubh(Rx++Mu) - Rdd=memubh(Rx++Mu:brev) - Rdd=memubh(Rx++#s4:2) - Rdd=memubh(Rx++#s4:2:circ(Mu)) - Rdd=memubh(Rx++I:circ(Mu)) - Rdd=memubh(Rs) - Rd=membh(Rs+#s11:1) - Rd=membh(Rt<<#u2+#U6) - Rd=membh(Re=#U6) - Rd=membh(Rx++Mu) - Rd=membh(Rx++Mu:brev) - Rd=membh(Rx++#s4:1) - Rd=membh(Rx++#s4:1:circ(Mu)) - Rd=membh(Rx++I:circ(Mu)) - Rd=membh(Rs) - Rdd=membh(Rs+#s11:2) - Rdd=membh(Rt<<#u2+#U6) - Rdd=membh(Re=#U6) - Rdd=membh(Rx++Mu) - Rdd=membh(Rx++Mu:brev) - Rdd=membh(Rx++#s4:2) - Rdd=membh(Rx++#s4:2:circ(Mu)) - Rdd=membh(Rx++I:circ(Mu)) - Rdd=membh(Rs) #### [Operation on memory byte](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-memop-operation-on-memory-byte) - memb(Rs+#u6:0)+=Rt - memb(Rs)+=Rt - memb(Rs+#u6:0)-=Rt - memb(Rs)-=Rt - memb(Rs+#u6:0)&=Rt - memb(Rs)&=Rt - memb(Rs+#u6:0)|=Rt - memb(Rs)|=Rt - memb(Rs+#u6:0)+=#U5 - memb(Rs)+=#U5 - memb(Rs+#u6:0)-=#U5 - memb(Rs)-=#U5 - memb(Rs+#u6:0)=clrbit(#U5) - memb(Rs)=clrbit(#U5) - memb(Rs+#u6:0)=setbit(#U5) - memb(Rs)=setbit(#U5) #### [Operation on memory halfword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-memop-operation-on-memory-halfword) - memh(Rs+#u6:1)+=Rt - memh(Rs)+=Rt - memh(Rs+#u6:1)-=Rt - memh(Rs)-=Rt - memh(Rs+#u6:1)&=Rt - memh(Rs)&=Rt - memh(Rs+#u6:1)|=Rt - memh(Rs)|=Rt - memh(Rs+#u6:1)+=#U5 - memh(Rs)+=#U5 - memh(Rs+#u6:1)-=#U5 - memh(Rs)-=#U5 - memh(Rs+#u6:1)=clrbit(#U5) - memh(Rs)=clrbit(#U5) - memh(Rs+#u6:1)=setbit(#U5) - memh(Rs)=setbit(#U5) #### [Operation on memory word](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-memop-operation-on-memory-word) - memw(Rs+#u6:2)+=Rt - memw(Rs)+=Rt - memw(Rs+#u6:2)-=Rt - memw(Rs)-=Rt - memw(Rs+#u6:2)&=Rt - memw(Rs)&=Rt - memw(Rs+#u6:2)|=Rt - memw(Rs)|=Rt - memw(Rs+#u6:2)+=#U5 - memw(Rs)+=#U5 - memw(Rs+#u6:2)-=#U5 - memw(Rs)-=#U5 - memw(Rs+#u6:2)=clrbit(#U5) - memw(Rs)=clrbit(#U5) - memw(Rs+#u6:2)=setbit(#U5) - memw(Rs)=setbit(#U5) ### [Jump to address conditioned on new register value](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-nv-j-jump-to-address-conditioned-on-new-register-value) - if (cmp.eq(Ns.new,#U5)) jump:t #r9:2 - if (cmp.eq(Ns.new,#U5)) jump:nt #r9:2 - if (!cmp.eq(Ns.new,#U5)) jump:t #r9:2 - if (!cmp.eq(Ns.new,#U5)) jump:nt #r9:2 - if (cmp.gt(Ns.new,#U5)) jump:t #r9:2 - if (cmp.gt(Ns.new,#U5)) jump:nt #r9:2 - if (!cmp.gt(Ns.new,#U5)) jump:t #r9:2 - if (!cmp.gt(Ns.new,#U5)) jump:nt #r9:2 - if (cmp.gtu(Ns.new,#U5)) jump:t #r9:2 - if (cmp.gtu(Ns.new,#U5)) jump:nt #r9:2 - if (!cmp.gtu(Ns.new,#U5)) jump:t #r9:2 - if (!cmp.gtu(Ns.new,#U5)) jump:nt #r9:2 - if (cmp.eq(Ns.new,#-1)) jump:t #r9:2 - if (cmp.eq(Ns.new,#-1)) jump:nt #r9:2 - if (!cmp.eq(Ns.new,#-1)) jump:t #r9:2 - if (!cmp.eq(Ns.new,#-1)) jump:nt #r9:2 - if (cmp.gt(Ns.new,#-1)) jump:t #r9:2 - if (cmp.gt(Ns.new,#-1)) jump:nt #r9:2 - if (!cmp.gt(Ns.new,#-1)) jump:t #r9:2 - if (!cmp.gt(Ns.new,#-1)) jump:nt #r9:2 - if (tstbit(Ns.new,#0)) jump:t #r9:2 - if (tstbit(Ns.new,#0)) jump:nt #r9:2 - if (!tstbit(Ns.new,#0)) jump:t #r9:2 - if (!tstbit(Ns.new,#0)) jump:nt #r9:2 - if (cmp.eq(Ns.new,Rt)) jump:t #r9:2 - if (cmp.eq(Ns.new,Rt)) jump:nt #r9:2 - if (cmp.gt(Ns.new,Rt)) jump:t #r9:2 - if (cmp.gt(Ns.new,Rt)) jump:nt #r9:2 - if (cmp.gtu(Ns.new,Rt)) jump:t #r9:2 - if (cmp.gtu(Ns.new,Rt)) jump:nt #r9:2 - if (cmp.gt(Rt,Ns.new)) jump:t #r9:2 - if (cmp.gt(Rt,Ns.new)) jump:nt #r9:2 - if (cmp.gtu(Rt,Ns.new)) jump:t #r9:2 - if (cmp.gtu(Rt,Ns.new)) jump:nt #r9:2 - if (!cmp.eq(Ns.new,Rt)) jump:t #r9:2 - if (!cmp.eq(Ns.new,Rt)) jump:nt #r9:2 - if (!cmp.gt(Ns.new,Rt)) jump:t #r9:2 - if (!cmp.gt(Ns.new,Rt)) jump:nt #r9:2 - if (!cmp.gtu(Ns.new,Rt)) jump:t #r9:2 - if (!cmp.gtu(Ns.new,Rt)) jump:nt #r9:2 - if (!cmp.gt(Rt,Ns.new)) jump:t #r9:2 - if (!cmp.gt(Rt,Ns.new)) jump:nt #r9:2 - if (!cmp.gtu(Rt,Ns.new)) jump:t #r9:2 - if (!cmp.gtu(Rt,Ns.new)) jump:nt #r9:2 ### [Store new-value byte](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-nv-st-store-new-value-byte) - memb(Rs+#s11:0)=Nt.new - memb(Rx++#s4:0)=Nt.new - memb(Re=#U6)=Nt.new - memb(Rx++Mu)=Nt.new - memb(Ru<<#u2+#U6)=Nt.new - memb(Rx++Mu:brev)=Nt.new - memb(Rx++#s4:0:circ(Mu))=Nt.new - memb(Rx++I:circ(Mu))=Nt.new - memb(Rs)=Nt.new - memb(Rs+Ru<<#u2)=Nt.new - memb(gp+#u16:0)=Nt.new ### [Store new-value byte conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-nv-st-store-new-value-byte-conditionally) - if (Pv) memb(Rs+#u6:0)=Nt.new - if (Pv) memb(Rx++#s4:0)=Nt.new - if (!Pv) memb(Rs+#u6:0)=Nt.new - if (!Pv) memb(Rx++#s4:0)=Nt.new - if (Pv) memb(Rs+Ru<<#u2)=Nt.new - if (!Pv) memb(Rs+Ru<<#u2)=Nt.new - if (Pv.new) memb(Rs+#u6:0)=Nt.new - if (!Pv.new) memb(Rs+#u6:0)=Nt.new - if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new - if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new - if (Pv.new) memb(Rx++#s4:0)=Nt.new - if (!Pv.new) memb(Rx++#s4:0)=Nt.new - if (Pv) memb(#u6)=Nt.new - if (!Pv) memb(#u6)=Nt.new - if (Pv.new) memb(#u6)=Nt.new - if (!Pv.new) memb(#u6)=Nt.new - if (Pv) memb(Rs)=Nt.new - if (!Pv) memb(Rs)=Nt.new - if (Pv.new) memb(Rs)=Nt.new - if (!Pv.new) memb(Rs)=Nt.new ### [Store new-value halfword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-nv-st-store-new-value-halfword) - memh(Rs+#s11:1)=Nt.new - memh(Rx++#s4:1)=Nt.new - memh(Re=#U6)=Nt.new - memh(Rx++Mu)=Nt.new - memh(Ru<<#u2+#U6)=Nt.new - memh(Rx++Mu:brev)=Nt.new - memh(Rx++#s4:1:circ(Mu))=Nt.new - memh(Rx++I:circ(Mu))=Nt.new - memh(Rs)=Nt.new - memh(Rs+Ru<<#u2)=Nt.new - memh(gp+#u16:1)=Nt.new ### [Store new-value halfword conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-nv-st-store-new-value-halfword-conditionally) - if (Pv) memh(Rs+#u6:1)=Nt.new - if (Pv) memh(Rx++#s4:1)=Nt.new - if (!Pv) memh(Rs+#u6:1)=Nt.new - if (!Pv) memh(Rx++#s4:1)=Nt.new - if (Pv) memh(Rs+Ru<<#u2)=Nt.new - if (!Pv) memh(Rs+Ru<<#u2)=Nt.new - if (Pv.new) memh(Rs+#u6:1)=Nt.new - if (!Pv.new) memh(Rs+#u6:1)=Nt.new - if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new - if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new - if (Pv.new) memh(Rx++#s4:1)=Nt.new - if (!Pv.new) memh(Rx++#s4:1)=Nt.new - if (Pv) memh(#u6)=Nt.new - if (!Pv) memh(#u6)=Nt.new - if (Pv.new) memh(#u6)=Nt.new - if (!Pv.new) memh(#u6)=Nt.new - if (Pv) memh(Rs)=Nt.new - if (!Pv) memh(Rs)=Nt.new - if (Pv.new) memh(Rs)=Nt.new - if (!Pv.new) memh(Rs)=Nt.new ### [Store new-value word](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-nv-st-store-new-value-word) - memw(Rs+#s11:2)=Nt.new - memw(Rx++#s4:2)=Nt.new - memw(Re=#U6)=Nt.new - memw(Rx++Mu)=Nt.new - memw(Ru<<#u2+#U6)=Nt.new - memw(Rx++Mu:brev)=Nt.new - memw(Rx++#s4:2:circ(Mu))=Nt.new - memw(Rx++I:circ(Mu))=Nt.new - memw(Rs)=Nt.new - memw(Rs+Ru<<#u2)=Nt.new - memw(gp+#u16:2)=Nt.new ### [Store new-value word conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-nv-st-store-new-value-word-conditionally) - if (Pv) memw(Rs+#u6:2)=Nt.new - if (Pv) memw(Rx++#s4:2)=Nt.new - if (!Pv) memw(Rs+#u6:2)=Nt.new - if (!Pv) memw(Rx++#s4:2)=Nt.new - if (Pv) memw(Rs+Ru<<#u2)=Nt.new - if (!Pv) memw(Rs+Ru<<#u2)=Nt.new - if (Pv.new) memw(Rs+#u6:2)=Nt.new - if (!Pv.new) memw(Rs+#u6:2)=Nt.new - if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new - if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new - if (Pv.new) memw(Rx++#s4:2)=Nt.new - if (!Pv.new) memw(Rx++#s4:2)=Nt.new - if (Pv) memw(#u6)=Nt.new - if (!Pv) memw(#u6)=Nt.new - if (Pv.new) memw(#u6)=Nt.new - if (!Pv.new) memw(#u6)=Nt.new - if (Pv) memw(Rs)=Nt.new - if (!Pv) memw(Rs)=Nt.new - if (Pv.new) memw(Rs)=Nt.new - if (!Pv.new) memw(Rs)=Nt.new #### [Store doubleword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-store-doubleword) - memd(Rs+#s11:3)=Rtt - memd(Rx++#s4:3)=Rtt - memd(Re=#U6)=Rtt - memd(Rx++Mu)=Rtt - memd(Ru<<#u2+#U6)=Rtt - memd(Rx++Mu:brev)=Rtt - memd(Rx++#s4:3:circ(Mu))=Rtt - memd(Rx++I:circ(Mu))=Rtt - memd(Rs)=Rtt - memd(Rx++#s4:3):nt=Rtt - memd(Rs+Ru<<#u2)=Rtt - memd(gp+#u16:3)=Rtt - memd(r29+#s6:3)=Rtt #### [Store-release doubleword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-store-release-doubleword) - memd\_rl(Rs):at=Rtt - memd\_rl(Rs):st=Rtt #### [Store doubleword conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-store-doubleword-conditionally) - if (!Pv) memd(Rx++#s4:3):nt=Rtt - if (Pv) memd(Rx++#s4:3):nt=Rtt - if (Pv) memd(Rs+#u6:3)=Rtt - if (Pv) memd(Rx++#s4:3)=Rtt - if (!Pv) memd(Rs+#u6:3)=Rtt - if (!Pv) memd(Rx++#s4:3)=Rtt - if (Pv) memd(Rs+Ru<<#u2)=Rtt - if (!Pv) memd(Rs+Ru<<#u2)=Rtt - if (Pv.new) memd(Rs+#u6:3)=Rtt - if (!Pv.new) memd(Rs+#u6:3)=Rtt - if (Pv.new) memd(Rs+Ru<<#u2)=Rtt - if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt - if (Pv.new) memd(Rx++#s4:3)=Rtt - if (!Pv.new) memd(Rx++#s4:3)=Rtt - if (Pv) memd(#u6)=Rtt - if (!Pv) memd(#u6)=Rtt - if (Pv.new) memd(#u6)=Rtt - if (!Pv.new) memd(#u6)=Rtt - if (Pv) memd(Rs)=Rtt - if (!Pv) memd(Rs)=Rtt - if (Pv.new) memd(Rs)=Rtt - if (!Pv.new) memd(Rs)=Rtt #### [Store byte](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-store-byte) - memb(Rs+#s11:0)=Rt - memb(Rx++#s4:0)=Rt - memb(Re=#U6)=Rt - memb(Rx++Mu)=Rt - memb(Ru<<#u2+#U6)=Rt - memb(Rx++Mu:brev)=Rt - memb(Rx++#s4:0:circ(Mu))=Rt - memb(Rx++I:circ(Mu))=Rt - memb(Rs)=Rt - memb(Rx++#s4:0):nt=Rt - memb(Rs+Ru<<#u2)=Rt - memb(Rs+#u6:0)=#S8 - memb(Rs)=#S8 - memb(gp+#u16:0)=Rt - memb(Rs+#u4:0)=Rt - memb(Rs+#u4:0)=#0 - memb(Rs+#u4:0)=#1 #### [Store byte conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-store-byte-conditionally) - if (!Pv) memb(Rx++#s4:0):nt=Rt - if (Pv) memb(Rx++#s4:0):nt=Rt - if (Pv) memb(Rs+#u6:0)=Rt - if (Pv) memb(Rx++#s4:0)=Rt - if (!Pv) memb(Rs+#u6:0)=Rt - if (!Pv) memb(Rx++#s4:0)=Rt - if (Pv) memb(Rs+Ru<<#u2)=Rt - if (!Pv) memb(Rs+Ru<<#u2)=Rt - if (Pv.new) memb(Rs+#u6:0)=Rt - if (!Pv.new) memb(Rs+#u6:0)=Rt - if (Pv.new) memb(Rs+Ru<<#u2)=Rt - if (!Pv.new) memb(Rs+Ru<<#u2)=Rt - if (Pv.new) memb(Rx++#s4:0)=Rt - if (!Pv.new) memb(Rx++#s4:0)=Rt - if (Pv) memb(#u6)=Rt - if (!Pv) memb(#u6)=Rt - if (Pv.new) memb(#u6)=Rt - if (!Pv.new) memb(#u6)=Rt - if (Pv) memb(Rs)=Rt - if (!Pv) memb(Rs)=Rt - if (Pv.new) memb(Rs)=Rt - if (!Pv.new) memb(Rs)=Rt - if (Pv) memb(Rs+#u6:0)=#S6 - if (!Pv) memb(Rs+#u6:0)=#S6 - if (Pv.new) memb(Rs+#u6:0)=#S6 - if (!Pv.new) memb(Rs+#u6:0)=#S6 - if (Pv) memb(Rs)=#S6 - if (!Pv) memb(Rs)=#S6 - if (Pv.new) memb(Rs)=#S6 - if (!Pv.new) memb(Rs)=#S6 #### [Store halfword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-store-halfword) - memh(Rs+#s11:1)=Rt - memh(Rx++#s4:1)=Rt - memh(Re=#U6)=Rt - memh(Rx++Mu)=Rt - memh(Ru<<#u2+#U6)=Rt - memh(Rx++Mu:brev)=Rt - memh(Rx++#s4:1:circ(Mu))=Rt - memh(Rx++I:circ(Mu))=Rt - memh(Rs)=Rt - memh(Rs+#s11:1)=Rt.H - memh(Rx++#s4:1)=Rt.H - memh(Re=#U6)=Rt.H - memh(Rx++Mu)=Rt.H - memh(Ru<<#u2+#U6)=Rt.H - memh(Rx++Mu:brev)=Rt.H - memh(Rx++#s4:1:circ(Mu))=Rt.H - memh(Rx++I:circ(Mu))=Rt.H - memh(Rs)=Rt.H - memh(Rx++#s4:1):nt=Rt - memh(Rs+Ru<<#u2)=Rt - memh(Rs+Ru<<#u2)=Rt.H - memh(Rs+#u6:1)=#S8 - memh(Rs)=#S8 - memh(gp+#u16:1)=Rt - memh(gp+#u16:1)=Rt.H - memh(Rs+#u3:1)=Rt #### [Store halfword conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-store-halfword-conditionally) - if (!Pv) memh(Rx++#s4:1):nt=Rt - if (Pv) memh(Rx++#s4:1):nt=Rt - if (Pv) memh(Rs+#u6:1)=Rt - if (Pv) memh(Rx++#s4:1)=Rt - if (!Pv) memh(Rs+#u6:1)=Rt - if (!Pv) memh(Rx++#s4:1)=Rt - if (Pv) memh(Rs+Ru<<#u2)=Rt - if (!Pv) memh(Rs+Ru<<#u2)=Rt - if (Pv.new) memh(Rs+#u6:1)=Rt - if (!Pv.new) memh(Rs+#u6:1)=Rt - if (Pv.new) memh(Rs+Ru<<#u2)=Rt - if (!Pv.new) memh(Rs+Ru<<#u2)=Rt - if (Pv.new) memh(Rx++#s4:1)=Rt - if (!Pv.new) memh(Rx++#s4:1)=Rt - if (Pv) memh(#u6)=Rt - if (!Pv) memh(#u6)=Rt - if (Pv.new) memh(#u6)=Rt - if (!Pv.new) memh(#u6)=Rt - if (Pv) memh(Rs)=Rt - if (!Pv) memh(Rs)=Rt - if (Pv.new) memh(Rs)=Rt - if (!Pv.new) memh(Rs)=Rt - if (Pv) memh(Rs+#u6:1)=Rt.H - if (Pv) memh(Rx++#s4:1)=Rt.H - if (!Pv) memh(Rs+#u6:1)=Rt.H - if (!Pv) memh(Rx++#s4:1)=Rt.H - if (Pv) memh(Rs+Ru<<#u2)=Rt.H - if (!Pv) memh(Rs+Ru<<#u2)=Rt.H - if (Pv.new) memh(Rs+#u6:1)=Rt.H - if (!Pv.new) memh(Rs+#u6:1)=Rt.H - if (Pv.new) memh(Rs+Ru<<#u2)=Rt.H - if (!Pv.new) memh(Rs+Ru<<#u2)=Rt.H - if (Pv.new) memh(Rx++#s4:1)=Rt.H - if (!Pv.new) memh(Rx++#s4:1)=Rt.H - if (Pv) memh(#u6)=Rt.H - if (!Pv) memh(#u6)=Rt.H - if (Pv.new) memh(#u6)=Rt.H - if (!Pv.new) memh(#u6)=Rt.H - if (Pv) memh(Rs)=Rt.H - if (!Pv) memh(Rs)=Rt.H - if (Pv.new) memh(Rs)=Rt.H - if (!Pv.new) memh(Rs)=Rt.H - if (Pv) memh(Rs+#u6:1)=#S6 - if (!Pv) memh(Rs+#u6:1)=#S6 - if (Pv.new) memh(Rs+#u6:1)=#S6 - if (!Pv.new) memh(Rs+#u6:1)=#S6 - if (Pv) memh(Rs)=#S6 - if (!Pv) memh(Rs)=#S6 - if (Pv.new) memh(Rs)=#S6 - if (!Pv.new) memh(Rs)=#S6 #### [Release](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-release) - release(Rs):at - release(Rs):st #### [Store word](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-store-word) - memw(Rs+#s11:2)=Rt - memw(Rx++#s4:2)=Rt - memw(Re=#U6)=Rt - memw(Rx++Mu)=Rt - memw(Ru<<#u2+#U6)=Rt - memw(Rx++Mu:brev)=Rt - memw(Rx++#s4:2:circ(Mu))=Rt - memw(Rx++I:circ(Mu))=Rt - memw(Rs)=Rt - memw(Rx++#s4:2):nt=Rt - memw(Rs+Ru<<#u2)=Rt - memw(Rs+#u6:2)=#S8 - memw(Rs)=#S8 - memw(gp+#u16:2)=Rt - memw(Rs+#u4:2)=Rt - memw(r29+#u5:2)=Rt - memw(Rs+#u4:2)=#0 - memw(Rs+#u4:2)=#1 #### [Store-release word](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-store-release-word) - memw\_rl(Rs):at=Rt - memw\_rl(Rs):st=Rt #### [Store word conditionally](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-store-word-conditionally) - if (!Pv) memw(Rx++#s4:2):nt=Rt - if (Pv) memw(Rx++#s4:2):nt=Rt - if (Pv) memw(Rs+#u6:2)=Rt - if (Pv) memw(Rx++#s4:2)=Rt - if (!Pv) memw(Rs+#u6:2)=Rt - if (!Pv) memw(Rx++#s4:2)=Rt - if (Pv) memw(Rs+Ru<<#u2)=Rt - if (!Pv) memw(Rs+Ru<<#u2)=Rt - if (Pv.new) memw(Rs+#u6:2)=Rt - if (!Pv.new) memw(Rs+#u6:2)=Rt - if (Pv.new) memw(Rs+Ru<<#u2)=Rt - if (!Pv.new) memw(Rs+Ru<<#u2)=Rt - if (Pv.new) memw(Rx++#s4:2)=Rt - if (!Pv.new) memw(Rx++#s4:2)=Rt - if (Pv) memw(#u6)=Rt - if (!Pv) memw(#u6)=Rt - if (Pv.new) memw(#u6)=Rt - if (!Pv.new) memw(#u6)=Rt - if (Pv) memw(Rs)=Rt - if (!Pv) memw(Rs)=Rt - if (Pv.new) memw(Rs)=Rt - if (!Pv.new) memw(Rs)=Rt - if (Pv) memw(Rs+#u6:2)=#S6 - if (!Pv) memw(Rs+#u6:2)=#S6 - if (Pv.new) memw(Rs+#u6:2)=#S6 - if (!Pv.new) memw(Rs+#u6:2)=#S6 - if (Pv) memw(Rs)=#S6 - if (!Pv) memw(Rs)=#S6 - if (Pv.new) memw(Rs)=#S6 - if (!Pv.new) memw(Rs)=#S6 #### [Allocate stack frame](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-st-allocate-stack-frame) - allocframe(Rx,#u11:3):raw - allocframe(#u11:3) - allocframe(#u5:3) ### [Load locked](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-load-locked) - Rd=memw\_locked(Rs) - Rdd=memd\_locked(Rs) ### [Store conditional](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-store-conditional) - memw\_locked(Rs,Pd)=Rt - memd\_locked(Rs,Pd)=Rtt ### [Zero a cache line](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-zero-a-cache-line) - dczeroa(Rs) - dczeroa(Rs):nt ### [Memory barrier](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-memory-barrier) - barrier ### [Breakpoint](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-breakpoint) - brkpt ### [Data cache prefetch](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-data-cache-prefetch) - dcfetch(Rs+#u11:3):nt - dcfetch(Rs+#u11:3) - dcfetch(Rs) ### [Data cache maintenance user operations](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-data-cache-maintenance-user-operations) - dccleana(Rs) - dccleaninva(Rs) - dcinva(Rs) ### [Send value to DIAG trace](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-send-value-to-diag-trace) - diag(Rs) - diag0(Rss,Rtt) - diag1(Rss,Rtt) ### [Instruction cache maintenance user operations](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-instruction-cache-maintenance-user-operations) - icinva(Rs) ### [Instruction synchronization](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-instruction-synchronization) - isync ### [L2 cache prefetch](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-l2-cache-prefetch) - l2fetch(Rs,Rt) - l2fetch(Rs,Rtt) ### [Pause](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-pause) - pause(#u10) ### [Memory thread synchronization](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-memory-thread-synchronization) - syncht ### [Send value to ETM trace](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-send-value-to-etm-trace) - trace(Rs) ### [Trap](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-trap) - trap0(#u8) - trap1(Rx,#u8) - trap2(#u8) - trap1(#u8) ### [Unpause](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-system-user-unpause) - unpause ### [Absolute value doubleword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-absolute-value-doubleword) - Rdd=abs(Rss) ### [Absolute value word](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-absolute-value-word) - Rd=abs(Rs) - Rd=abs(Rs):sat ### [Add/Subtract and accumulate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-add-subtract-and-accumulate) - Rd=add(Rs,add(Ru,#s6)) - Rd=add(Rs,sub(#s6,Ru)) - Rx+=add(Rs,Rt) - Rx+=add(Rs,#s8) - Rx-=add(Rs,Rt) - Rx-=add(Rs,#s8) - Rx+=sub(Rt,Rs) ### [Add doublewords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-add-doublewords) - Rdd=add(Rss,Rtt) - Rdd=add(Rss,Rtt):sat - Rdd=add(Rss,Rtt):raw:lo - Rdd=add(Rss,Rtt):raw:hi - Rdd=add(Rs,Rtt) - Rd=add(Rs,Rt):sat:deprecated ### [Add halfword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-add-halfword) - Rd=add(Rt.L,Rs.L) - Rd=add(Rt.L,Rs.H) - Rd=add(Rt.L,Rs.L):sat - Rd=add(Rt.L,Rs.H):sat - Rd=add(Rt.L,Rs.L):<<16 - Rd=add(Rt.L,Rs.H):<<16 - Rd=add(Rt.H,Rs.L):<<16 - Rd=add(Rt.H,Rs.H):<<16 - Rd=add(Rt.L,Rs.L):sat:<<16 - Rd=add(Rt.L,Rs.H):sat:<<16 - Rd=add(Rt.H,Rs.L):sat:<<16 - Rd=add(Rt.H,Rs.H):sat:<<16 ### [Add or subtract doublewords with carry](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-add-or-subtract-doublewords-with-carry) - Rdd=add(Rss,Rtt,Px):carry - Rdd=sub(Rss,Rtt,Px):carry ### [Clip to unsigned](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-clip-to-unsigned) - Rd=clip(Rs,#u5) ### [Logical doublewords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-logical-doublewords) - Rdd=and(Rtt,~Rss) - Rdd=or(Rtt,~Rss) - Rdd=and(Rss,Rtt) - Rdd=or(Rss,Rtt) - Rdd=xor(Rss,Rtt) - Rdd=not(Rss) ### [Logical-logical doublewords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-logical-logical-doublewords) - Rxx^=xor(Rss,Rtt) ### [Logical-logical words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-logical-logical-words) - Rx^=xor(Rs,Rt) - Rx&=and(Rs,Rt) - Rx&=and(Rs,~Rt) - Rx&=or(Rs,Rt) - Rx&=xor(Rs,Rt) - Rx|=and(Rs,Rt) - Rx|=and(Rs,~Rt) - Rx|=or(Rs,Rt) - Rx|=xor(Rs,Rt) - Rx=or(Ru,and(Rx,#s10)) - Rx|=and(Rs,#s10) - Rx|=or(Rs,#s10) - Rx^=and(Rs,Rt) - Rx^=or(Rs,Rt) - Rx^=and(Rs,~Rt) ### [Maximum words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-maximum-words) - Rd=max(Rs,Rt) - Rd=maxu(Rs,Rt) ### [Maximum doublewords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-maximum-doublewords) - Rdd=max(Rss,Rtt) - Rdd=maxu(Rss,Rtt) ### [Minimum words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-minimum-words) - Rd=min(Rt,Rs) - Rd=minu(Rt,Rs) ### [Minimum doublewords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-minimum-doublewords) - Rdd=min(Rtt,Rss) - Rdd=minu(Rtt,Rss) ### [Modulo wrap](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-modulo-wrap) - Rd=modwrap(Rs,Rt) ### [Negate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-negate) - Rd=neg(Rs):sat - Rdd=neg(Rss) ### [Round](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-round) - Rd=round(Rss):sat - Rd=round(Rs,#u5) - Rd=round(Rs,Rt) - Rd=round(Rs,#u5):sat - Rd=round(Rs,Rt):sat - Rd=cround(Rs,#u5) - Rd=cround(Rs,Rt) - Rdd=cround(Rss,#u6) - Rdd=cround(Rss,Rt) ### [Subtract doublewords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-subtract-doublewords) - Rdd=sub(Rtt,Rss) - Rd=sub(Rt,Rs):sat:deprecated ### [Subtract halfword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-subtract-halfword) - Rd=sub(Rt.L,Rs.L) - Rd=sub(Rt.L,Rs.H) - Rd=sub(Rt.L,Rs.L):sat - Rd=sub(Rt.L,Rs.H):sat - Rd=sub(Rt.L,Rs.L):<<16 - Rd=sub(Rt.L,Rs.H):<<16 - Rd=sub(Rt.H,Rs.L):<<16 - Rd=sub(Rt.H,Rs.H):<<16 - Rd=sub(Rt.L,Rs.L):sat:<<16 - Rd=sub(Rt.L,Rs.H):sat:<<16 - Rd=sub(Rt.H,Rs.L):sat:<<16 - Rd=sub(Rt.H,Rs.H):sat:<<16 ### [Sign extend word to doubleword](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-sign-extend-word-to-doubleword) - Rdd=sxtw(Rs) ### [Vector absolute value halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-absolute-value-halfwords) - Rdd=vabsh(Rss) - Rdd=vabsh(Rss):sat ### [Vector absolute value words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-absolute-value-words) - Rdd=vabsw(Rss) - Rdd=vabsw(Rss):sat ### [Vector absolute difference bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-absolute-difference-bytes) - Rdd=vabsdiffb(Rtt,Rss) - Rdd=vabsdiffub(Rtt,Rss) ### [Vector absolute difference halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-absolute-difference-halfwords) - Rdd=vabsdiffh(Rtt,Rss) ### [Vector absolute difference words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-absolute-difference-words) - Rdd=vabsdiffw(Rtt,Rss) ### [Vector add compare and select maximum halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-add-compare-and-select-maximum-halfwords) - Rxx,Pe=vacsh(Rss,Rtt) ### [Vector add halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-add-halfwords) - Rdd=vaddh(Rss,Rtt) - Rdd=vaddh(Rss,Rtt):sat - Rdd=vadduh(Rss,Rtt):sat ### [Vector add halfwords with saturate and pack to unsigned bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-add-halfwords-with-saturate-and-pack-to-unsigned-bytes) - Rd=vaddhub(Rss,Rtt):sat ### [Vector reduce add unsigned bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-reduce-add-unsigned-bytes) - Rdd=vraddub(Rss,Rtt) - Rxx+=vraddub(Rss,Rtt) ### [Vector reduce add halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-reduce-add-halfwords) - Rd=vraddh(Rss,Rtt) - Rd=vradduh(Rss,Rtt) ### [Vector add bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-add-bytes) - Rdd=vaddub(Rss,Rtt) - Rdd=vaddb(Rss,Rtt) - Rdd=vaddub(Rss,Rtt):sat ### [Vector add words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-add-words) - Rdd=vaddw(Rss,Rtt) - Rdd=vaddw(Rss,Rtt):sat ### [Vector average halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-average-halfwords) - Rdd=vavguh(Rss,Rtt) - Rdd=vavgh(Rss,Rtt) - Rdd=vnavgh(Rtt,Rss) - Rdd=vavgh(Rss,Rtt):crnd - Rdd=vnavgh(Rtt,Rss):crnd:sat - Rdd=vavguh(Rss,Rtt):rnd - Rdd=vavgh(Rss,Rtt):rnd - Rdd=vnavgh(Rtt,Rss):rnd:sat ### [Vector average unsigned bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-average-unsigned-bytes) - Rdd=vavgub(Rss,Rtt) - Rdd=vavgub(Rss,Rtt):rnd ### [Vector average words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-average-words) - Rdd=vavgw(Rss,Rtt) - Rdd=vnavgw(Rtt,Rss) - Rdd=vavgw(Rss,Rtt):rnd - Rdd=vnavgw(Rtt,Rss):rnd:sat - Rdd=vavgw(Rss,Rtt):crnd - Rdd=vnavgw(Rtt,Rss):crnd:sat - Rdd=vavguw(Rss,Rtt) - Rdd=vavguw(Rss,Rtt):rnd ### [Vector clip to unsigned](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-clip-to-unsigned) - Rdd=vclip(Rss,#u5) ### [Vector conditional negate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-conditional-negate) - Rdd=vcnegh(Rss,Rt) - Rxx+=vrcnegh(Rss,Rt) ### [Vector maximum bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-maximum-bytes) - Rdd=vmaxb(Rtt,Rss) - Rdd=vmaxub(Rtt,Rss) ### [Vector maximum halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-maximum-halfwords) - Rdd=vmaxh(Rtt,Rss) - Rdd=vmaxuh(Rtt,Rss) ### [Vector reduce maximum halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-reduce-maximum-halfwords) - Rxx=vrmaxh(Rss,Ru) - Rxx=vrmaxuh(Rss,Ru) ### [Vector reduce maximum words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-reduce-maximum-words) - Rxx=vrmaxw(Rss,Ru) - Rxx=vrmaxuw(Rss,Ru) ### [Vector maximum words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-maximum-words) - Rdd=vmaxw(Rtt,Rss) - Rdd=vmaxuw(Rtt,Rss) ### [Vector minimum bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-minimum-bytes) - Rdd=vminb(Rtt,Rss) - Rdd=vminub(Rtt,Rss) - Rdd,Pe=vminub(Rtt,Rss) ### [Vector minimum halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-minimum-halfwords) - Rdd=vminh(Rtt,Rss) - Rdd=vminuh(Rtt,Rss) ### [Vector reduce minimum halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-reduce-minimum-halfwords) - Rxx=vrminh(Rss,Ru) - Rxx=vrminuh(Rss,Ru) ### [Vector reduce minimum words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-reduce-minimum-words) - Rxx=vrminw(Rss,Ru) - Rxx=vrminuw(Rss,Ru) ### [Vector minimum words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-minimum-words) - Rdd=vminw(Rtt,Rss) - Rdd=vminuw(Rtt,Rss) ### [Vector sum of absolute differences unsigned bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-sum-of-absolute-differences-unsigned-bytes) - Rdd=vrsadub(Rss,Rtt) - Rxx+=vrsadub(Rss,Rtt) ### [Vector subtract halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-subtract-halfwords) - Rdd=vsubh(Rtt,Rss) - Rdd=vsubh(Rtt,Rss):sat - Rdd=vsubuh(Rtt,Rss):sat ### [Vector subtract bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-subtract-bytes) - Rdd=vsubub(Rtt,Rss) - Rdd=vsubb(Rss,Rtt) - Rdd=vsubub(Rtt,Rss):sat ### [Vector subtract words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-alu-vector-subtract-words) - Rdd=vsubw(Rtt,Rss) - Rdd=vsubw(Rtt,Rss):sat ### [Count leading](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-count-leading) - Rd=normamt(Rs) - Rd=add(clb(Rs),#s6) - Rd=normamt(Rss) - Rd=add(clb(Rss),#s6) - Rd=clb(Rs) - Rd=cl0(Rs) - Rd=cl1(Rs) - Rd=clb(Rss) - Rd=cl0(Rss) - Rd=cl1(Rss) ### [Count population](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-count-population) - Rd=popcount(Rss) ### [Count trailing](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-count-trailing) - Rd=ct0(Rs) - Rd=ct1(Rs) - Rd=ct0(Rss) - Rd=ct1(Rss) ### [Extract bitfield](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-extract-bitfield) - Rd=extract(Rs,#u5,#U5) - Rd=extractu(Rs,#u5,#U5) - Rdd=extract(Rss,#u6,#U6) - Rdd=extractu(Rss,#u6,#U6) - Rd=extract(Rs,Rtt) - Rd=extractu(Rs,Rtt) - Rdd=extract(Rss,Rtt) - Rdd=extractu(Rss,Rtt) ### [Insert bitfield](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-insert-bitfield) - Rx=insert(Rs,#u5,#U5) - Rxx=insert(Rss,#u6,#U6) - Rx=insert(Rs,Rtt) - Rxx=insert(Rss,Rtt) ### [Interleave/deinterleave](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-interleave-deinterleave) - Rdd=interleave(Rss) - Rdd=deinterleave(Rss) ### [Linear feedback-shift iteration](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-linear-feedback-shift-iteration) - Rdd=lfs(Rss,Rtt) ### [Masked parity](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-masked-parity) - Rd=parity(Rs,Rt) - Rd=parity(Rss,Rtt) ### [Bit reverse](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-bit-reverse) - Rd=brev(Rs) - Rdd=brev(Rss) ### [Set/clear/toggle bit](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-set-clear-toggle-bit) - Rd=setbit(Rs,#u5) - Rd=togglebit(Rs,#u5) - Rd=clrbit(Rs,#u5) - Rd=setbit(Rs,Rt) - Rd=togglebit(Rs,Rt) - Rd=clrbit(Rs,Rt) ### [Split bitfield](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-split-bitfield) - Rdd=bitsplit(Rs,#u5) - Rdd=bitsplit(Rs,Rt) ### [Table index](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-bit-table-index) - Rx=tableidxb(Rs,#u4,#S6):raw - Rx=tableidxh(Rs,#u4,#S6):raw - Rx=tableidxw(Rs,#u4,#S6):raw - Rx=tableidxd(Rs,#u4,#S6):raw - Rx=tableidxb(Rs,#u4,#U5) - Rx=tableidxh(Rs,#u4,#U5) - Rx=tableidxw(Rs,#u4,#U5) - Rx=tableidxd(Rs,#u4,#U5) ### [Complex add/sub halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-complex-add-sub-halfwords) - Rdd=vxaddsubh(Rss,Rtt):sat - Rdd=vxsubaddh(Rss,Rtt):sat - Rdd=vxaddsubh(Rss,Rtt):rnd:>>1:sat - Rdd=vxsubaddh(Rss,Rtt):rnd:>>1:sat ### [Complex add/sub words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-complex-add-sub-words) - Rdd=vxaddsubw(Rss,Rtt):sat - Rdd=vxsubaddw(Rss,Rtt):sat ### [Complex multiply](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-complex-multiply) - Rxx+=cmpy(Rs,Rt):sat - Rxx+=cmpy(Rs,Rt):<<1:sat - Rxx+=cmpy(Rs,Rt\*):sat - Rxx+=cmpy(Rs,Rt\*):<<1:sat - Rdd=cmpy(Rs,Rt):sat - Rdd=cmpy(Rs,Rt):<<1:sat - Rdd=cmpy(Rs,Rt\*):sat - Rdd=cmpy(Rs,Rt\*):<<1:sat - Rxx-=cmpy(Rs,Rt):sat - Rxx-=cmpy(Rs,Rt):<<1:sat - Rxx-=cmpy(Rs,Rt\*):sat - Rxx-=cmpy(Rs,Rt\*):<<1:sat ### [Complex multiply real or imaginary](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-complex-multiply-real-or-imaginary) - Rxx+=cmpyi(Rs,Rt) - Rxx+=cmpyr(Rs,Rt) - Rdd=cmpyi(Rs,Rt) - Rdd=cmpyr(Rs,Rt) ### [Complex multiply with round and pack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-complex-multiply-with-round-and-pack) - Rd=cmpy(Rs,Rt):rnd:sat - Rd=cmpy(Rs,Rt):<<1:rnd:sat - Rd=cmpy(Rs,Rt\*):rnd:sat - Rd=cmpy(Rs,Rt\*):<<1:rnd:sat ### [Complex multiply 32x16](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-complex-multiply-32x16) - Rd=cmpyiwh(Rss,Rt):<<1:rnd:sat - Rd=cmpyrwh(Rss,Rt):<<1:rnd:sat - Rd=cmpyiwh(Rss,Rt\*):<<1:rnd:sat - Rd=cmpyrwh(Rss,Rt\*):<<1:rnd:sat ### [Complex multiply real or imaginary 32-bit](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-complex-multiply-real-or-imaginary-32-bit) - Rdd=cmpyrw(Rss,Rtt) - Rxx+=cmpyrw(Rss,Rtt) - Rdd=cmpyrw(Rss,Rtt\*) - Rxx+=cmpyrw(Rss,Rtt\*) - Rdd=cmpyiw(Rss,Rtt) - Rxx+=cmpyiw(Rss,Rtt) - Rdd=cmpyiw(Rss,Rtt\*) - Rxx+=cmpyiw(Rss,Rtt\*) - Rd=cmpyrw(Rss,Rtt):<<1:sat - Rd=cmpyrw(Rss,Rtt\*):<<1:sat - Rd=cmpyiw(Rss,Rtt):<<1:sat - Rd=cmpyiw(Rss,Rtt\*):<<1:sat - Rd=cmpyrw(Rss,Rtt):<<1:rnd:sat - Rd=cmpyrw(Rss,Rtt\*):<<1:rnd:sat - Rd=cmpyiw(Rss,Rtt):<<1:rnd:sat - Rd=cmpyiw(Rss,Rtt\*):<<1:rnd:sat ### [Vector complex multiply real or imaginary](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-vector-complex-multiply-real-or-imaginary) - Rdd=vcmpyi(Rss,Rtt):sat - Rdd=vcmpyr(Rss,Rtt):sat - Rdd=vcmpyi(Rss,Rtt):<<1:sat - Rdd=vcmpyr(Rss,Rtt):<<1:sat - Rxx+=vcmpyi(Rss,Rtt):sat - Rxx+=vcmpyr(Rss,Rtt):sat ### [Vector complex conjugate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-vector-complex-conjugate) - Rdd=vconj(Rss):sat ### [Vector complex rotate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-vector-complex-rotate) - Rdd=vcrotate(Rss,Rt) ### [Vector reduce complex multiply real or imaginary](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-vector-reduce-complex-multiply-real-or-imaginary) - Rxx+=vrcmpyi(Rss,Rtt) - Rxx+=vrcmpyr(Rss,Rtt) - Rxx+=vrcmpyi(Rss,Rtt\*) - Rxx+=vrcmpyr(Rss,Rtt\*) - Rdd=vrcmpyi(Rss,Rtt) - Rdd=vrcmpyr(Rss,Rtt) - Rdd=vrcmpyi(Rss,Rtt\*) - Rdd=vrcmpyr(Rss,Rtt\*) ### [Vector reduce complex multiply by scalar](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-vector-reduce-complex-multiply-by-scalar) - Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:hi - Rdd=vrcmpys(Rss,Rtt):<<1:sat:raw:lo - Rdd=vrcmpys(Rss,Rt):<<1:sat - Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:hi - Rxx+=vrcmpys(Rss,Rtt):<<1:sat:raw:lo - Rxx+=vrcmpys(Rss,Rt):<<1:sat ### [Vector reduce complex multiply by scalar with round and pack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-vector-reduce-complex-multiply-by-scalar-with-round-and-pack) - Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:hi - Rd=vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:lo - Rd=vrcmpys(Rss,Rt):<<1:rnd:sat ### [Vector reduce complex rotate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-complex-vector-reduce-complex-rotate) - Rxx+=vrcrotate(Rss,Rt,#u2) - Rdd=vrcrotate(Rss,Rt,#u2) ### [Floating point addition](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-addition) - Rd=sfadd(Rs,Rt) - Rdd=dfadd(Rss,Rtt) ### [Classify floating-point value](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-classify-floating-point-value) - Pd=sfclass(Rs,#u5) - Pd=dfclass(Rss,#u5) ### [Compare floating-point value](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-compare-floating-point-value) - Pd=sfcmp.eq(Rs,Rt) - Pd=sfcmp.gt(Rs,Rt) - Pd=sfcmp.ge(Rs,Rt) - Pd=sfcmp.uo(Rs,Rt) - Pd=dfcmp.eq(Rss,Rtt) - Pd=dfcmp.gt(Rss,Rtt) - Pd=dfcmp.ge(Rss,Rtt) - Pd=dfcmp.uo(Rss,Rtt) ### [Convert floating-point value to other format](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-convert-floating-point-value-to-other-format) - Rdd=convert\_sf2df(Rs) - Rd=convert\_df2sf(Rss) ### [Convert integer to floating-point value](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-convert-integer-to-floating-point-value) - Rd=convert\_uw2sf(Rs) - Rdd=convert\_uw2df(Rs) - Rd=convert\_w2sf(Rs) - Rdd=convert\_w2df(Rs) - Rd=convert\_ud2sf(Rss) - Rdd=convert\_ud2df(Rss) - Rd=convert\_d2sf(Rss) - Rdd=convert\_d2df(Rss) ### [Convert floating-point value to integer](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-convert-floating-point-value-to-integer) - Rd=convert\_sf2uw(Rs) - Rd=convert\_sf2w(Rs) - Rdd=convert\_sf2ud(Rs) - Rdd=convert\_sf2d(Rs) - Rd=convert\_df2uw(Rss) - Rd=convert\_df2w(Rss) - Rdd=convert\_df2ud(Rss) - Rdd=convert\_df2d(Rss) - Rd=convert\_sf2uw(Rs):chop - Rd=convert\_sf2w(Rs):chop - Rdd=convert\_sf2ud(Rs):chop - Rdd=convert\_sf2d(Rs):chop - Rd=convert\_df2uw(Rss):chop - Rd=convert\_df2w(Rss):chop - Rdd=convert\_df2ud(Rss):chop - Rdd=convert\_df2d(Rss):chop ### [Floating point extreme value assistance](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-extreme-value-assistance) - Rd=sffixupn(Rs,Rt) - Rd=sffixupd(Rs,Rt) - Rd=sffixupr(Rs) ### [Floating point fused multiply-add](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-fused-multiply-add) - Rx+=sfmpy(Rs,Rt) - Rx-=sfmpy(Rs,Rt) - Rxx+=dfmpylh(Rss,Rtt) - Rxx+=dfmpyhh(Rss,Rtt) ### [Floating point fused multiply-add with scaling](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-fused-multiply-add-with-scaling) - Rx+=sfmpy(Rs,Rt,Pu):scale ### [Floating point reciprocal square root approximation](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-reciprocal-square-root-approximation) - Rd,Pe=sfinvsqrta(Rs) ### [Floating point fused multiply-add for library routines](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-fused-multiply-add-for-library-routines) - Rx+=sfmpy(Rs,Rt):lib - Rx-=sfmpy(Rs,Rt):lib ### [Create floating-point constant](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-create-floating-point-constant) - Rd=sfmake(#u10):pos - Rd=sfmake(#u10):neg - Rdd=dfmake(#u10):pos - Rdd=dfmake(#u10):neg ### [Floating point maximum](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-maximum) - Rd=sfmax(Rs,Rt) - Rdd=dfmax(Rss,Rtt) ### [Floating point minimum](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-minimum) - Rd=sfmin(Rs,Rt) - Rdd=dfmin(Rss,Rtt) ### [Floating point multiply](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-multiply) - Rd=sfmpy(Rs,Rt) - Rdd=dfmpyfix(Rss,Rtt) - Rdd=dfmpyll(Rss,Rtt) ### [Floating point reciprocal approximation](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-reciprocal-approximation) - Rd,Pe=sfrecipa(Rs,Rt) ### [Floating point subtraction](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-floating-point-subtraction) - Rd=sfsub(Rs,Rt) - Rdd=dfsub(Rss,Rtt) ### [Vector floating point add/sub](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-vector-floating-point-add-sub) - Rdd=vsfadd(Rss,Rtt) - Rdd=vsfsub(Rss,Rtt) ### [Vector floating point multiply](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-fp-vector-floating-point-multiply) - Rdd=vsfmpy(Rss,Rtt) - Rxx+=vsfmpy(Rss,Rtt) - Rxx-=vsfmpy(Rss,Rtt) ### [Multiply and use lower result](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-multiply-and-use-lower-result) - Rd=+mpyi(Rs,#u8) - Rd=-mpyi(Rs,#u8) - Rd=mpyi(Rs,#m9) - Rx+=mpyi(Rs,#u8) - Rx-=mpyi(Rs,#u8) - Rd=mpyi(Rs,Rt) - Rd=mpyui(Rs,Rt) - Rx+=mpyi(Rs,Rt) - Rx-=mpyi(Rs,Rt) - Ry=add(Ru,mpyi(Ry,Rs)) - Rd=add(Ru,mpyi(#u6:2,Rs)) - Rd=add(Ru,mpyi(Rs,#u6)) - Rd=add(#u6,mpyi(Rs,#U6)) - Rd=add(#u6,mpyi(Rs,Rt)) ### [Vector multiply word by signed half (32x16)](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-multiply-word-by-signed-half-32x16) - Rxx+=vmpyweh(Rss,Rtt):sat - Rxx+=vmpyweh(Rss,Rtt):<<1:sat - Rxx+=vmpywoh(Rss,Rtt):sat - Rxx+=vmpywoh(Rss,Rtt):<<1:sat - Rdd=vmpyweh(Rss,Rtt):sat - Rdd=vmpyweh(Rss,Rtt):<<1:sat - Rdd=vmpywoh(Rss,Rtt):sat - Rdd=vmpywoh(Rss,Rtt):<<1:sat - Rxx+=vmpyweh(Rss,Rtt):rnd:sat - Rxx+=vmpyweh(Rss,Rtt):<<1:rnd:sat - Rxx+=vmpywoh(Rss,Rtt):rnd:sat - Rxx+=vmpywoh(Rss,Rtt):<<1:rnd:sat - Rdd=vmpyweh(Rss,Rtt):rnd:sat - Rdd=vmpyweh(Rss,Rtt):<<1:rnd:sat - Rdd=vmpywoh(Rss,Rtt):rnd:sat - Rdd=vmpywoh(Rss,Rtt):<<1:rnd:sat ### [Vector multiply word by unsigned half (32x16)](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-multiply-word-by-unsigned-half-32x16) - Rxx+=vmpyweuh(Rss,Rtt):sat - Rxx+=vmpyweuh(Rss,Rtt):<<1:sat - Rxx+=vmpywouh(Rss,Rtt):sat - Rxx+=vmpywouh(Rss,Rtt):<<1:sat - Rdd=vmpyweuh(Rss,Rtt):sat - Rdd=vmpyweuh(Rss,Rtt):<<1:sat - Rdd=vmpywouh(Rss,Rtt):sat - Rdd=vmpywouh(Rss,Rtt):<<1:sat - Rxx+=vmpyweuh(Rss,Rtt):rnd:sat - Rxx+=vmpyweuh(Rss,Rtt):<<1:rnd:sat - Rxx+=vmpywouh(Rss,Rtt):rnd:sat - Rxx+=vmpywouh(Rss,Rtt):<<1:rnd:sat - Rdd=vmpyweuh(Rss,Rtt):rnd:sat - Rdd=vmpyweuh(Rss,Rtt):<<1:rnd:sat - Rdd=vmpywouh(Rss,Rtt):rnd:sat - Rdd=vmpywouh(Rss,Rtt):<<1:rnd:sat ### [Multiply signed halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-multiply-signed-halfwords) - Rx+=mpy(Rs.H,Rt.H) - Rx+=mpy(Rs.H,Rt.H):<<1 - Rx+=mpy(Rs.H,Rt.L) - Rx+=mpy(Rs.H,Rt.L):<<1 - Rx+=mpy(Rs.L,Rt.H) - Rx+=mpy(Rs.L,Rt.H):<<1 - Rx+=mpy(Rs.L,Rt.L) - Rx+=mpy(Rs.L,Rt.L):<<1 - Rx-=mpy(Rs.H,Rt.H) - Rx-=mpy(Rs.H,Rt.H):<<1 - Rx-=mpy(Rs.H,Rt.L) - Rx-=mpy(Rs.H,Rt.L):<<1 - Rx-=mpy(Rs.L,Rt.H) - Rx-=mpy(Rs.L,Rt.H):<<1 - Rx-=mpy(Rs.L,Rt.L) - Rx-=mpy(Rs.L,Rt.L):<<1 - Rx+=mpy(Rs.H,Rt.H):sat - Rx+=mpy(Rs.H,Rt.H):<<1:sat - Rx+=mpy(Rs.H,Rt.L):sat - Rx+=mpy(Rs.H,Rt.L):<<1:sat - Rx+=mpy(Rs.L,Rt.H):sat - Rx+=mpy(Rs.L,Rt.H):<<1:sat - Rx+=mpy(Rs.L,Rt.L):sat - Rx+=mpy(Rs.L,Rt.L):<<1:sat - Rx-=mpy(Rs.H,Rt.H):sat - Rx-=mpy(Rs.H,Rt.H):<<1:sat - Rx-=mpy(Rs.H,Rt.L):sat - Rx-=mpy(Rs.H,Rt.L):<<1:sat - Rx-=mpy(Rs.L,Rt.H):sat - Rx-=mpy(Rs.L,Rt.H):<<1:sat - Rx-=mpy(Rs.L,Rt.L):sat - Rx-=mpy(Rs.L,Rt.L):<<1:sat - Rd=mpy(Rs.H,Rt.H) - Rd=mpy(Rs.H,Rt.H):<<1 - Rd=mpy(Rs.H,Rt.L) - Rd=mpy(Rs.H,Rt.L):<<1 - Rd=mpy(Rs.L,Rt.H) - Rd=mpy(Rs.L,Rt.H):<<1 - Rd=mpy(Rs.L,Rt.L) - Rd=mpy(Rs.L,Rt.L):<<1 - Rd=mpy(Rs.H,Rt.H):sat - Rd=mpy(Rs.H,Rt.H):<<1:sat - Rd=mpy(Rs.H,Rt.L):sat - Rd=mpy(Rs.H,Rt.L):<<1:sat - Rd=mpy(Rs.L,Rt.H):sat - Rd=mpy(Rs.L,Rt.H):<<1:sat - Rd=mpy(Rs.L,Rt.L):sat - Rd=mpy(Rs.L,Rt.L):<<1:sat - Rd=mpy(Rs.H,Rt.H):rnd - Rd=mpy(Rs.H,Rt.H):<<1:rnd - Rd=mpy(Rs.H,Rt.L):rnd - Rd=mpy(Rs.H,Rt.L):<<1:rnd - Rd=mpy(Rs.L,Rt.H):rnd - Rd=mpy(Rs.L,Rt.H):<<1:rnd - Rd=mpy(Rs.L,Rt.L):rnd - Rd=mpy(Rs.L,Rt.L):<<1:rnd - Rd=mpy(Rs.H,Rt.H):rnd:sat - Rd=mpy(Rs.H,Rt.H):<<1:rnd:sat - Rd=mpy(Rs.H,Rt.L):rnd:sat - Rd=mpy(Rs.H,Rt.L):<<1:rnd:sat - Rd=mpy(Rs.L,Rt.H):rnd:sat - Rd=mpy(Rs.L,Rt.H):<<1:rnd:sat - Rd=mpy(Rs.L,Rt.L):rnd:sat - Rd=mpy(Rs.L,Rt.L):<<1:rnd:sat - Rxx+=mpy(Rs.H,Rt.H) - Rxx+=mpy(Rs.H,Rt.H):<<1 - Rxx+=mpy(Rs.H,Rt.L) - Rxx+=mpy(Rs.H,Rt.L):<<1 - Rxx+=mpy(Rs.L,Rt.H) - Rxx+=mpy(Rs.L,Rt.H):<<1 - Rxx+=mpy(Rs.L,Rt.L) - Rxx+=mpy(Rs.L,Rt.L):<<1 - Rxx-=mpy(Rs.H,Rt.H) - Rxx-=mpy(Rs.H,Rt.H):<<1 - Rxx-=mpy(Rs.H,Rt.L) - Rxx-=mpy(Rs.H,Rt.L):<<1 - Rxx-=mpy(Rs.L,Rt.H) - Rxx-=mpy(Rs.L,Rt.H):<<1 - Rxx-=mpy(Rs.L,Rt.L) - Rxx-=mpy(Rs.L,Rt.L):<<1 - Rdd=mpy(Rs.H,Rt.H) - Rdd=mpy(Rs.H,Rt.H):<<1 - Rdd=mpy(Rs.H,Rt.L) - Rdd=mpy(Rs.H,Rt.L):<<1 - Rdd=mpy(Rs.L,Rt.H) - Rdd=mpy(Rs.L,Rt.H):<<1 - Rdd=mpy(Rs.L,Rt.L) - Rdd=mpy(Rs.L,Rt.L):<<1 - Rdd=mpy(Rs.H,Rt.H):rnd - Rdd=mpy(Rs.H,Rt.H):<<1:rnd - Rdd=mpy(Rs.H,Rt.L):rnd - Rdd=mpy(Rs.H,Rt.L):<<1:rnd - Rdd=mpy(Rs.L,Rt.H):rnd - Rdd=mpy(Rs.L,Rt.H):<<1:rnd - Rdd=mpy(Rs.L,Rt.L):rnd - Rdd=mpy(Rs.L,Rt.L):<<1:rnd ### [Multiply unsigned halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-multiply-unsigned-halfwords) - Rx+=mpyu(Rs.H,Rt.H) - Rx+=mpyu(Rs.H,Rt.H):<<1 - Rx+=mpyu(Rs.H,Rt.L) - Rx+=mpyu(Rs.H,Rt.L):<<1 - Rx+=mpyu(Rs.L,Rt.H) - Rx+=mpyu(Rs.L,Rt.H):<<1 - Rx+=mpyu(Rs.L,Rt.L) - Rx+=mpyu(Rs.L,Rt.L):<<1 - Rx-=mpyu(Rs.H,Rt.H) - Rx-=mpyu(Rs.H,Rt.H):<<1 - Rx-=mpyu(Rs.H,Rt.L) - Rx-=mpyu(Rs.H,Rt.L):<<1 - Rx-=mpyu(Rs.L,Rt.H) - Rx-=mpyu(Rs.L,Rt.H):<<1 - Rx-=mpyu(Rs.L,Rt.L) - Rx-=mpyu(Rs.L,Rt.L):<<1 - Rd=mpyu(Rs.H,Rt.H) - Rd=mpyu(Rs.H,Rt.H):<<1 - Rd=mpyu(Rs.H,Rt.L) - Rd=mpyu(Rs.H,Rt.L):<<1 - Rd=mpyu(Rs.L,Rt.H) - Rd=mpyu(Rs.L,Rt.H):<<1 - Rd=mpyu(Rs.L,Rt.L) - Rd=mpyu(Rs.L,Rt.L):<<1 - Rxx+=mpyu(Rs.H,Rt.H) - Rxx+=mpyu(Rs.H,Rt.H):<<1 - Rxx+=mpyu(Rs.H,Rt.L) - Rxx+=mpyu(Rs.H,Rt.L):<<1 - Rxx+=mpyu(Rs.L,Rt.H) - Rxx+=mpyu(Rs.L,Rt.H):<<1 - Rxx+=mpyu(Rs.L,Rt.L) - Rxx+=mpyu(Rs.L,Rt.L):<<1 - Rxx-=mpyu(Rs.H,Rt.H) - Rxx-=mpyu(Rs.H,Rt.H):<<1 - Rxx-=mpyu(Rs.H,Rt.L) - Rxx-=mpyu(Rs.H,Rt.L):<<1 - Rxx-=mpyu(Rs.L,Rt.H) - Rxx-=mpyu(Rs.L,Rt.H):<<1 - Rxx-=mpyu(Rs.L,Rt.L) - Rxx-=mpyu(Rs.L,Rt.L):<<1 - Rdd=mpyu(Rs.H,Rt.H) - Rdd=mpyu(Rs.H,Rt.H):<<1 - Rdd=mpyu(Rs.H,Rt.L) - Rdd=mpyu(Rs.H,Rt.L):<<1 - Rdd=mpyu(Rs.L,Rt.H) - Rdd=mpyu(Rs.L,Rt.H):<<1 - Rdd=mpyu(Rs.L,Rt.L) - Rdd=mpyu(Rs.L,Rt.L):<<1 ### [Polynomial multiply words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-polynomial-multiply-words) - Rdd=pmpyw(Rs,Rt) - Rxx^=pmpyw(Rs,Rt) ### [Vector reduce multiply word by signed half (32x16)](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-reduce-multiply-word-by-signed-half-32x16) - Rdd=vrmpyweh(Rss,Rtt) - Rdd=vrmpyweh(Rss,Rtt):<<1 - Rxx+=vrmpyweh(Rss,Rtt) - Rxx+=vrmpyweh(Rss,Rtt):<<1 - Rdd=vrmpywoh(Rss,Rtt) - Rdd=vrmpywoh(Rss,Rtt):<<1 - Rxx+=vrmpywoh(Rss,Rtt) - Rxx+=vrmpywoh(Rss,Rtt):<<1 ### [Multiply and use upper result](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-multiply-and-use-upper-result) - Rd=mpy(Rs,Rt) - Rd=mpy(Rs,Rt):<<1 - Rd=mpy(Rs,Rt):<<1:sat - Rd=mpyu(Rs,Rt) - Rd=mpysu(Rs,Rt) - Rd=mpy(Rs,Rt):rnd - Rx+=mpy(Rs,Rt):<<1:sat - Rx-=mpy(Rs,Rt):<<1:sat - Rd=mpy(Rs,Rt.L):<<1:rnd:sat - Rd=mpy(Rs,Rt.H):<<1:rnd:sat - Rd=mpy(Rs,Rt.L):<<1:sat - Rd=mpy(Rs,Rt.H):<<1:sat ### [Multiply and use full result](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-multiply-and-use-full-result) - Rdd=mpy(Rs,Rt) - Rxx+=mpy(Rs,Rt) - Rxx-=mpy(Rs,Rt) - Rdd=mpyu(Rs,Rt) - Rxx+=mpyu(Rs,Rt) - Rxx-=mpyu(Rs,Rt) ### [Vector dual multiply](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-dual-multiply) - Rxx+=vdmpy(Rss,Rtt):sat - Rxx+=vdmpy(Rss,Rtt):<<1:sat - Rdd=vdmpy(Rss,Rtt):sat - Rdd=vdmpy(Rss,Rtt):<<1:sat ### [Vector dual multiply with round and pack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-dual-multiply-with-round-and-pack) - Rd=vdmpy(Rss,Rtt):rnd:sat - Rd=vdmpy(Rss,Rtt):<<1:rnd:sat ### [Vector reduce multiply bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-reduce-multiply-bytes) - Rdd=vrmpybu(Rss,Rtt) - Rxx+=vrmpybu(Rss,Rtt) - Rdd=vrmpybsu(Rss,Rtt) - Rxx+=vrmpybsu(Rss,Rtt) ### [Vector dual multiply signed by unsigned bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-dual-multiply-signed-by-unsigned-bytes) - Rdd=vdmpybsu(Rss,Rtt):sat - Rxx+=vdmpybsu(Rss,Rtt):sat ### [Vector multiply even halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-multiply-even-halfwords) - Rdd=vmpyeh(Rss,Rtt):sat - Rdd=vmpyeh(Rss,Rtt):<<1:sat - Rxx+=vmpyeh(Rss,Rtt):sat - Rxx+=vmpyeh(Rss,Rtt):<<1:sat - Rxx+=vmpyeh(Rss,Rtt) ### [Vector multiply halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-multiply-halfwords) - Rdd=vmpyh(Rs,Rt):sat - Rdd=vmpyh(Rs,Rt):<<1:sat - Rxx+=vmpyh(Rs,Rt):sat - Rxx+=vmpyh(Rs,Rt):<<1:sat - Rxx+=vmpyh(Rs,Rt) ### [Vector multiply halfwords with round and pack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-multiply-halfwords-with-round-and-pack) - Rd=vmpyh(Rs,Rt):rnd:sat - Rd=vmpyh(Rs,Rt):<<1:rnd:sat ### [Vector multiply halfwords, signed by unsigned](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-multiply-halfwords-signed-by-unsigned) - Rdd=vmpyhsu(Rs,Rt):sat - Rdd=vmpyhsu(Rs,Rt):<<1:sat - Rxx+=vmpyhsu(Rs,Rt):sat - Rxx+=vmpyhsu(Rs,Rt):<<1:sat ### [Vector reduce multiply halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-reduce-multiply-halfwords) - Rxx+=vrmpyh(Rss,Rtt) - Rdd=vrmpyh(Rss,Rtt) ### [Vector multiply bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-multiply-bytes) - Rdd=vmpybu(Rs,Rt) - Rdd=vmpybsu(Rs,Rt) - Rxx+=vmpybu(Rs,Rt) - Rxx+=vmpybsu(Rs,Rt) ### [Vector polynomial multiply halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-mpy-vector-polynomial-multiply-halfwords) - Rdd=vpmpyh(Rs,Rt) - Rxx^=vpmpyh(Rs,Rt) ### [CABAC decode bin](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-cabac-decode-bin) - Rdd=decbin(Rss,Rtt) ### [Saturate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-saturate) - Rd=sat(Rss) - Rd=sath(Rs) - Rd=satuh(Rs) - Rd=satub(Rs) - Rd=satb(Rs) ### [Swizzle bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-swizzle-bytes) - Rd=swiz(Rs) ### [Vector align](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-align) - Rdd=valignb(Rtt,Rss,#u3) - Rdd=valignb(Rtt,Rss,Pu) ### [Vector round and pack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-round-and-pack) - Rd=vrndwh(Rss) - Rd=vrndwh(Rss):sat ### [Vector saturate and pack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-saturate-and-pack) - Rd=vsathub(Rss) - Rd=vsathub(Rs) - Rd=vsathb(Rs) - Rd=vsathb(Rss) - Rd=vsatwh(Rss) - Rd=vsatwuh(Rss) ### [Vector saturate without pack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-saturate-without-pack) - Rdd=vsathub(Rss) - Rdd=vsathb(Rss) - Rdd=vsatwh(Rss) - Rdd=vsatwuh(Rss) ### [Vector shuffle](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-shuffle) - Rdd=shuffob(Rtt,Rss) - Rdd=shuffeb(Rss,Rtt) - Rdd=shuffoh(Rtt,Rss) - Rdd=shuffeh(Rss,Rtt) ### [Vector splat bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-splat-bytes) - Rd=vsplatb(Rs) - Rdd=vsplatb(Rs) ### [Vector splat halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-splat-halfwords) - Rdd=vsplath(Rs) ### [Vector splice](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-splice) - Rdd=vspliceb(Rss,Rtt,#u3) - Rdd=vspliceb(Rss,Rtt,Pu) ### [Vector sign extend](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-sign-extend) - Rdd=vsxtbh(Rs) - Rdd=vsxthw(Rs) ### [Vector truncate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-truncate) - Rd=vtrunohb(Rss) - Rdd=vtrunewh(Rss,Rtt) - Rdd=vtrunowh(Rss,Rtt) - Rd=vtrunehb(Rss) - Rdd=vtrunehb(Rss,Rtt) - Rdd=vtrunohb(Rss,Rtt) ### [Vector zero extend](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-perm-vector-zero-extend) - Rdd=vzxtbh(Rs) - Rdd=vzxthw(Rs) ### [Bounds check](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-bounds-check) - Pd=boundscheck(Rss,Rtt):raw:hi - Pd=boundscheck(Rss,Rtt):raw:lo - Pd=boundscheck(Rs,Rtt) ### [Compare byte](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-compare-byte) - Pd=cmpb.eq(Rs,Rt) - Pd=cmpb.eq(Rs,#u8) - Pd=cmpb.gtu(Rs,Rt) - Pd=cmpb.gtu(Rs,#u7) - Pd=cmpb.gt(Rs,Rt) - Pd=cmpb.gt(Rs,#s8) ### [Compare half](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-compare-half) - Pd=cmph.eq(Rs,Rt) - Pd=cmph.gt(Rs,Rt) - Pd=cmph.gtu(Rs,Rt) - Pd=cmph.eq(Rs,#s8) - Pd=cmph.gt(Rs,#s8) - Pd=cmph.gtu(Rs,#u7) ### [Compare doublewords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-compare-doublewords) - Pd=cmp.eq(Rss,Rtt) - Pd=cmp.gt(Rss,Rtt) - Pd=cmp.gtu(Rss,Rtt) ### [Compare bit mask](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-compare-bit-mask) - Pd=bitsset(Rs,Rt) - Pd=bitsclr(Rs,Rt) - Pd=!bitsset(Rs,Rt) - Pd=!bitsclr(Rs,Rt) - Pd=bitsclr(Rs,#u6) - Pd=!bitsclr(Rs,#u6) ### [Mask generate from predicate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-mask-generate-from-predicate) - Rdd=mask(Pt) ### [Predicate transfer](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-predicate-transfer) - Rd=Ps - Pd=Rs ### [Test bit](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-test-bit) - Pd=tstbit(Rs,#u5) - Pd=!tstbit(Rs,#u5) - Pd=tstbit(Rs,Rt) - Pd=!tstbit(Rs,Rt) ### [Vector compare halfwords](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-vector-compare-halfwords) - Pd=vcmph.eq(Rss,Rtt) - Pd=vcmph.gt(Rss,Rtt) - Pd=vcmph.gtu(Rss,Rtt) - Pd=vcmph.eq(Rss,#s8) - Pd=vcmph.gt(Rss,#s8) - Pd=vcmph.gtu(Rss,#u7) ### [Vector compare bytes for any match](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-vector-compare-bytes-for-any-match) - Pd=any8(vcmpb.eq(Rss,Rtt)) - Pd=!any8(vcmpb.eq(Rss,Rtt)) ### [Vector compare bytes](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-vector-compare-bytes) - Pd=vcmpb.eq(Rss,Rtt) - Pd=vcmpb.eq(Rss,#u8) - Pd=vcmpb.gtu(Rss,Rtt) - Pd=vcmpb.gtu(Rss,#u7) - Pd=vcmpb.gt(Rss,Rtt) - Pd=vcmpb.gt(Rss,#s8) ### [Vector compare words](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-vector-compare-words) - Pd=vcmpw.eq(Rss,Rtt) - Pd=vcmpw.gt(Rss,Rtt) - Pd=vcmpw.gtu(Rss,Rtt) - Pd=vcmpw.eq(Rss,#s8) - Pd=vcmpw.gt(Rss,#s8) - Pd=vcmpw.gtu(Rss,#u7) ### [Viterbi pack even and odd predicate bits](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-viterbi-pack-even-and-odd-predicate-bits) - Rd=vitpack(Ps,Pt) ### [Vector mux](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-pred-vector-mux) - Rdd=vmux(Pu,Rss,Rtt) ### [Mask generate from immedidate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-mask-generate-from-immedidate) - Rd=mask(#u5,#U5) ### [Shift by immediate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-shift-by-immediate) - Rd=asr(Rs,#u5) - Rd=lsr(Rs,#u5) - Rd=asl(Rs,#u5) - Rd=rol(Rs,#u5) - Rdd=asr(Rss,#u6) - Rdd=lsr(Rss,#u6) - Rdd=asl(Rss,#u6) - Rdd=rol(Rss,#u6) ### [Shift by immediate and accumulate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-shift-by-immediate-and-accumulate) - Rx+=asr(Rs,#u5) - Rx+=lsr(Rs,#u5) - Rx+=asl(Rs,#u5) - Rx+=rol(Rs,#u5) - Rxx+=asr(Rss,#u6) - Rxx+=lsr(Rss,#u6) - Rxx+=asl(Rss,#u6) - Rxx+=rol(Rss,#u6) - Rx-=asr(Rs,#u5) - Rx-=lsr(Rs,#u5) - Rx-=asl(Rs,#u5) - Rx-=rol(Rs,#u5) - Rxx-=asr(Rss,#u6) - Rxx-=lsr(Rss,#u6) - Rxx-=asl(Rss,#u6) - Rxx-=rol(Rss,#u6) - Rx=add(#u8,asl(Rx,#U5)) - Rx=sub(#u8,asl(Rx,#U5)) - Rx=add(#u8,lsr(Rx,#U5)) - Rx=sub(#u8,lsr(Rx,#U5)) ### [Shift by immediate and add](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-shift-by-immediate-and-add) - Rd=addasl(Rt,Rs,#u3) ### [Shift by immediate and logical](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-shift-by-immediate-and-logical) - Rx^=lsr(Rs,#u5) - Rx^=asl(Rs,#u5) - Rx^=rol(Rs,#u5) - Rxx^=lsr(Rss,#u6) - Rxx^=asl(Rss,#u6) - Rxx^=rol(Rss,#u6) - Rx&=asr(Rs,#u5) - Rx&=lsr(Rs,#u5) - Rx&=asl(Rs,#u5) - Rx&=rol(Rs,#u5) - Rx|=asr(Rs,#u5) - Rx|=lsr(Rs,#u5) - Rx|=asl(Rs,#u5) - Rx|=rol(Rs,#u5) - Rxx&=asr(Rss,#u6) - Rxx&=lsr(Rss,#u6) - Rxx&=asl(Rss,#u6) - Rxx&=rol(Rss,#u6) - Rxx|=asr(Rss,#u6) - Rxx|=lsr(Rss,#u6) - Rxx|=asl(Rss,#u6) - Rxx|=rol(Rss,#u6) - Rx=and(#u8,asl(Rx,#U5)) - Rx=or(#u8,asl(Rx,#U5)) - Rx=and(#u8,lsr(Rx,#U5)) - Rx=or(#u8,lsr(Rx,#U5)) ### [Shift right by immediate with rounding](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-shift-right-by-immediate-with-rounding) - Rd=asr(Rs,#u5):rnd - Rd=asrrnd(Rs,#u5) - Rdd=asr(Rss,#u6):rnd - Rdd=asrrnd(Rss,#u6) ### [Shift left by immediate with saturation](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-shift-left-by-immediate-with-saturation) - Rd=asl(Rs,#u5):sat ### [Shift by register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-shift-by-register) - Rd=asr(Rs,Rt) - Rd=asl(Rs,Rt) - Rd=lsr(Rs,Rt) - Rd=lsl(Rs,Rt) - Rdd=asr(Rss,Rt) - Rdd=asl(Rss,Rt) - Rdd=lsr(Rss,Rt) - Rdd=lsl(Rss,Rt) - Rd=lsl(#s6,Rt) ### [Shift by register and accumulate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-shift-by-register-and-accumulate) - Rx+=asr(Rs,Rt) - Rx+=asl(Rs,Rt) - Rx+=lsr(Rs,Rt) - Rx+=lsl(Rs,Rt) - Rxx+=asr(Rss,Rt) - Rxx+=asl(Rss,Rt) - Rxx+=lsr(Rss,Rt) - Rxx+=lsl(Rss,Rt) - Rx-=asr(Rs,Rt) - Rx-=asl(Rs,Rt) - Rx-=lsr(Rs,Rt) - Rx-=lsl(Rs,Rt) - Rxx-=asr(Rss,Rt) - Rxx-=asl(Rss,Rt) - Rxx-=lsr(Rss,Rt) - Rxx-=lsl(Rss,Rt) ### [Shift by register and logical](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-shift-by-register-and-logical) - Rx&=asr(Rs,Rt) - Rx&=asl(Rs,Rt) - Rx&=lsr(Rs,Rt) - Rx&=lsl(Rs,Rt) - Rx|=asr(Rs,Rt) - Rx|=asl(Rs,Rt) - Rx|=lsr(Rs,Rt) - Rx|=lsl(Rs,Rt) - Rxx&=asr(Rss,Rt) - Rxx&=asl(Rss,Rt) - Rxx&=lsr(Rss,Rt) - Rxx&=lsl(Rss,Rt) - Rxx|=asr(Rss,Rt) - Rxx|=asl(Rss,Rt) - Rxx|=lsr(Rss,Rt) - Rxx|=lsl(Rss,Rt) - Rxx^=asr(Rss,Rt) - Rxx^=asl(Rss,Rt) - Rxx^=lsr(Rss,Rt) - Rxx^=lsl(Rss,Rt) ### [Shift by register with saturation](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-shift-by-register-with-saturation) - Rd=asr(Rs,Rt):sat - Rd=asl(Rs,Rt):sat ### [Vector shift halfwords by immediate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-vector-shift-halfwords-by-immediate) - Rdd=vasrh(Rss,#u4) - Rdd=vlsrh(Rss,#u4) - Rdd=vaslh(Rss,#u4) ### [Vector arithmetic shift halfwords with round](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-vector-arithmetic-shift-halfwords-with-round) - Rdd=vasrh(Rss,#u4):raw - Rdd=vasrh(Rss,#u4):rnd ### [Vector arithmetic shift halfwords with saturate and pack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-vector-arithmetic-shift-halfwords-with-saturate-and-pack) - Rd=vasrhub(Rss,#u4):raw - Rd=vasrhub(Rss,#u4):rnd:sat - Rd=vasrhub(Rss,#u4):sat ### [Vector shift halfwords by register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-vector-shift-halfwords-by-register) - Rdd=vasrh(Rss,Rt) - Rdd=vaslh(Rss,Rt) - Rdd=vlsrh(Rss,Rt) - Rdd=vlslh(Rss,Rt) ### [Vector shift words by immediate](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-vector-shift-words-by-immediate) - Rdd=vasrw(Rss,#u5) - Rdd=vlsrw(Rss,#u5) - Rdd=vaslw(Rss,#u5) ### [Vector shift words by register](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-vector-shift-words-by-register) - Rdd=vasrw(Rss,Rt) - Rdd=vaslw(Rss,Rt) - Rdd=vlsrw(Rss,Rt) - Rdd=vlslw(Rss,Rt) ### [Vector shift words with truncate and pack](https://docs.qualcomm.com/doc/80-N3040-23/topic/80-n2040-69_v83_prm_src_instruction-set.html#v83-xtype-shift-vector-shift-words-with-truncate-and-pack) - Rd=vasrw(Rss,#u5) - Rd=vasrw(Rss,Rt) Last Published: Oct 06, 2026 [Previous Topic Vector shift words with truncate and pack](https://docs.qualcomm.com/bundle/publicresource/80-N3040-23/topics/80-n2040-69_v83_prm_src_instruction-set.md) [Next Topic Hexagon V83 HVX Programmer’s Reference Manual](https://docs.qualcomm.com/bundle/publicresource/80-N3040-23/topics/index_80-n2040-70_v83_hvx_prm.md)