# HVX PMU events

The Hexagon processor architecture defines a performance monitor unit
(PMU) to provide on- target performance tracking.

The PMU allows for easy collection of aggregate performance data like
cache performance and instructions per packet. This data is valuable
for system planning and architecture purposes because it drives
performance and power statistical models.

In V69 and later versions, the PMU event space is expanded to 1024
events. Events 0 to 255 describe core events. Coprocessors use events
384 and above; which are described in the
*Qualcomm Hexagon V75 Programmer’s Reference Manual* (80-N2040-53)

[HVX PMU events](https://docs.qualcomm.com/doc/80-N3040-23/topic/v75-hvx-pmu-events.html#tbl-v75-hvx-processor-event-symbols) document the HVX events.

hvx v75 processor event symbols

| **Event** | **Symbol** | **Definition** | **Maskable** |
| --- | --- | --- | --- |
| 0x100 | HVX\_ACTIVE | VFIFO not empty | Not maskable |
| 0x101 | HVX\_REG\_ORDER | Stall cycles due to interlocks | Not maskable |
| 0x102 | HVX\_ACC\_ORDER | Stall cycles due to accumulator not produced in previous context cycle. | Not maskable |
| 0x103 | HVX\_LD\_L2\_OUTSTANDING | Stall cycles due to load pending | Not maskable |
| 0x104 | HVX\_ST\_L2\_OUTSTANDING | Stall cycles due to store not yet allocated in L2 | Not maskable |
| 0x105 | HVX\_VTCM\_OUTSTANDING | Stall cycles due to VTCM transaction pending. | Not maskable |
| 0x106 | HVX\_SCATGATH\_FULL | Scatter/gather: Network scoreboard not updated | Not maskable |
| 0x107 | HVX\_SCATGATH\_IN\_FULL | scatter/gather input buffer full | Not maskable |
| 0x108 | HVX\_ST\_FULL | store buffer full | Not maskable |
| 0x109 | HVX\_VOLTAGE\_VIRUS\_OVER | Throttling: Voltage virus overshoot | Not maskable |
| 0x10a | HVX\_VOLTAGE\_UNDER | Throttling: Voltage model would exceed undershoot threshold | Not maskable |
| 0x10b | HVX\_POWER\_OVER | Throttling: Sustained power exceeds budget | Not maskable |
| 0x10c | HVX\_PKT\_PARTIAL | Stall cycles due to multi-issue packet | Not maskable |
| 0x111 | HVX\_PKT | Increments by 2 per packet in 128-byte mode. Packets with HVX instructions | Not maskable |
| 0x112 | HVX\_PKT\_THREAD | Committed packets on a thread with the XE bit set, whether executed in Q6 or coprocessor | Not maskable |
| 0x113 | HVX\_CORE\_VFIFO\_FULL\_STALL | Number of cycles a thread had to stall due to VFIFO | Not maskable |
| 0x115 | CYCLES\_1\_HVX\_CONTEXTS\_RUNNING | Cycles 1 HVX context running | Not maskable |
| 0x116 | CYCLES\_2\_HVX\_CONTEXTS\_RUNNING | Cycles 2 HVX contexts running concurrently | Not maskable |
| 0x117 | CYCLES\_3\_HVX\_CONTEXTS\_RUNNING | Cycles 3 HVX contexts running concurrently | Not maskable |
| 0x118 | HVXLD\_L2 | L2 cacheable load access from HVX. Any load access from HVX that may cause a lookup in the L2 cache. Excludes cache ops, uncacheables, scalars | Not maskable |
| 0x119 | HVXLD\_L2\_TCM | TCM load access for HVX. HVX load from the L2 tcm space | Not maskable |
| 0x11a | HVXLD\_L2\_MISS | L2 cacheable miss from HVX. Of the events qualified by 0xFB, the ones that resulted in a miss i.e. the 64-byte address was not previously allocated in the L2 tag array and data will be fetched from backing memory | Not maskable |
| 0x11b | HVXLD\_L2\_SECONDARY\_MISS | Of the events in 0xFB, the ones where the load could not be returned due to the immediatately prior access for the line being a pending load or pending L2Fetch | Not maskable |
| 0x11c | HVXST\_L2\_WR | Vector write in L2. | Not maskable |
| 0x11d | HVXST\_SLD\_CONFLICT | Lower priority with respect to scalar load to access L2 return data bus | Not maskable |
| 0x11e | HVXST\_VTCM\_GATH\_CONFLICT | Lower priority with respect to gather | Not maskable |
| 0x11f | HVXST\_L2\_CONFLICT | Lost against another partition write to FIFO for L2 interleave. | Not maskable |
| 0x120 | HVXST\_VTCM\_CONFLICT | Lost against another partition write to FIFO for VTCM interleave. | Not maskable |
| 0x121 | HVXST\_L2\_FULL | write fifo full. | Not maskable |
| 0x122 | HVXST\_VTCM\_FULL | write fifo full. | Not maskable |
| 0x123 | HVXST\_L2 | Vector store to L2. | Not maskable |
| 0x124 | HVXST\_L2\_MISS | L2 cacheable miss from HVX store. Specifically the cases where the 128-byte-line address is not in the tag or a coalesce buffer. | Not maskable |
| 0x125 | HVXST\_L2TCM | TCM store access for HVX. HVX store to the L2 tcm space | Not maskable |
| 0x126 | HVXST\_VTCM | Vector store to VTCM. | Not maskable |
| 0x127 | HVXST\_L2\_SECODARY\_MISS | L2 cacheable secondary miss from HVX store. Specifically the cases where the 128-byte-line address is not in the tag or a coalesce buffer. | Not maskable |
| 0x128 | HVXPIPE\_ALU | Executed simple ALU instruction | Not maskable |
| 0x129 | HVXPIPE\_MPY | Executed multiply or abs-diff instruction | Not maskable |
| 0x12a | HVXPIPE\_SHIFT | Executed bit shift or bit count instruction | Not maskable |
| 0x12b | HVXPIPE\_PERM | Executed permute or cross-lane data movement instruction | Not maskable |
| 0x12c | CYCLES\_4\_HVX\_CONTEXTS\_RUNNING | Cycles 4 HVX contexts running concurrently | Not maskable |
| 0x190 | HVX\_VFIFO\_EMPTY | Number of cycles a thread had empty VFIFO | Not maskable |

Last Published: Oct 06, 2026

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