# CXO and SLEEP\_CLK routing

Source: [https://docs.qualcomm.com/doc/80-PV086-5P/topic/CXO-and-SLEEP_CLK-routing.html](https://docs.qualcomm.com/doc/80-PV086-5P/topic/CXO-and-SLEEP_CLK-routing.html)

All the CLK vias should be completely surrounded as they transition between layers. A
      C-shaped ring of vias should be standard for all clock and RF line transitions.

The QRB5165 device has two main clock inputs: CXO and SLEEP\_CLK. Route each of these clocks
      from the PM8250 to the QRB5165, while referencing a solid GND plane.

- These signals should be routed away from sensitive nets.
- The PM8250 clock driver output impedance can be controlled to match the line impedance and mitigate reflections.
- Both CXO and SLEEP\_CLK should immediately via down to inner layers when escaping the QRB5165 to remain isolated from the rest of the BGA fan-out.

**SLEEP\_CLK signal routing guidelines**

The SLEEP\_CLK signal routing guidelines are listed below.

- The SLEEP\_CLK buffer is redesigned to have a much slower edge rate; therefore, it is more
        favorable to multidestination routing of the clocks.
- Either star-routing or daisy-chain routing is acceptable.
    - If star-routing is used, ensure that the two-branch length difference is not too long
            (shorter than 30 mm is recommended).
    - If daisy-chain routing is used, ensure that the stub is as short as possible (shorter
            than 7 mm is recommended).

**Parent Topic:** [PCB layout guidelines](https://docs.qualcomm.com/doc/80-PV086-5P/topic/pcb-layout-guidelines.html)

Last Published: Jul 07, 2023

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