# USB 2.0 routing constraints

Source: [https://docs.qualcomm.com/doc/80-PV086-5P/topic/usb-2dot0-routing-constraints.html](https://docs.qualcomm.com/doc/80-PV086-5P/topic/usb-2dot0-routing-constraints.html)

The following table captures the routing constraints of USB 2.0 and DisplayPort.

| Metrics | Metrics | Metrics | Guidance |
| --- | --- | --- | --- |
| Data rate | Data rate | Data rate | 480 Mbps |
| Impedance | Differential | Field route | 75 – 105 Ω |
| Length match | Intralane match | Intralane match | 2 mm |
| Maximum PCB trace length | Maximum PCB trace length | Maximum PCB trace length | 250 mm |
| Spacing | To other signals | Field route | 3 × line width |

**Parent Topic:** [PCB layout guidelines](https://docs.qualcomm.com/doc/80-PV086-5P/topic/pcb-layout-guidelines.html)

Last Published: Jul 07, 2023

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