# USB 3.1/DisplayPort routing constraints

Source: [https://docs.qualcomm.com/doc/80-PV086-5P/topic/usb3dot1-displayport-routing-constraints.html](https://docs.qualcomm.com/doc/80-PV086-5P/topic/usb3dot1-displayport-routing-constraints.html)

The following table captures the routing constraints of USB 3.1 and DisplayPort.

| Metrics | Metrics | Metrics | Guidance | Guidance |
| --- | --- | --- | --- | --- |
| Data rate | Data rate | Data rate | 10 Gbps (Gen 2) | 5 Gbps (Gen 1) |
| Impedance [^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/usb3dot1-displayport-routing-constraints.html#fntarg_1) | Differential | Field route | 70 to 100 Ω | 70 to 100 Ω |
| Channel insertion loss budget | Channel insertion loss budget | Channel insertion loss budget | -7 dB at 5 GHz | -5.5 dB at 2.5 GHz |
| Length matching | USB SS or DisplayPort data lane intralane match | USB SS or DisplayPort data lane intralane match | 5 ps (700 µm) | 5 ps (700 µm) |
| Length matching | USB SS or DisplayPort data lane interlane match | USB SS or DisplayPort data lane interlane match | 70 ps (10 mm) | 70 ps (10 mm) |
| Length matching | DP\_AUX\_P/DP\_AUX\_M intralane match | DP\_AUX\_P/DP\_AUX\_M intralane match | 50 ps (7 mm) | 50 ps (7 mm) |
| Spacing | Rx-to-Tx | Field route | 4 × line width | 3 × line width |
| Spacing | Space to other signals | Field route | 4 × line width | 4 × line width |
| Component | AC capacitor | AC capacitor | 75 to 265 nF | 75 to 200 nF |
|  |  |  |  |  |
|  |  |  |  |  |

[^1^](https://docs.qualcomm.com/doc/80-PV086-5P/topic/usb3dot1-displayport-routing-constraints.html#fnsrc_1)  The range of PCB impedance includes manufacturing variation. The PCB designer is responsible for working with their PCB vendor to ensure each design falls within the published impedance range.

**Parent Topic:** [PCB layout guidelines](https://docs.qualcomm.com/doc/80-PV086-5P/topic/pcb-layout-guidelines.html)

Last Published: Jul 07, 2023

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